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cpu/stm32l1: adapted to centralized cpu conf

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This commit is contained in:
Hauke Petersen 2015-05-27 23:08:41 +02:00
parent 0e61ec097c
commit f48ea33805
4 changed files with 11 additions and 43 deletions
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8
cpu/stm32l1/cpu.c
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@ -26,14 +26,10 @@ static void clk_init(void);
void cpu_init(void) void cpu_init(void)
{ {
/* set PendSV priority to the lowest possible priority */ /* initialize the Cortex-M core */
NVIC_SetPriority(PendSV_IRQn, 0xff); cortexm_init();
/* initialize system clocks */ /* initialize system clocks */
clk_init(); clk_init();
/* configure the vector table location to internal flash */
SCB->VTOR = FLASH_BASE;
} }
/** /**

35
cpu/stm32l1/include/cpu_conf.h
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@ -28,28 +28,12 @@ extern "C" {
#endif #endif
/** /**
* @name Kernel configuration * @brief ARM Cortex-M specific CPU configuration
*
* @{ * @{
*/ */
#define THREAD_EXTRA_STACKSIZE_PRINTF (1024) #define CPU_DEFAULT_IRQ_PRIO (1U)
#define CPU_IRQ_NUMOF (57U)
#ifndef THREAD_STACKSIZE_DEFAULT #define CPU_FLASH_BASE FLASH_BASE
#define THREAD_STACKSIZE_DEFAULT (1024)
#endif
#define THREAD_STACKSIZE_IDLE (256)
/** @} */
/**
* @name UART0 buffer size definition for compatibility reasons
*
* TODO: remove once the remodeling of the uart0 driver is done
* @{
*/
#ifndef UART0_BUFSIZE
#define UART0_BUFSIZE (128)
#endif
/** @} */ /** @} */
/** /**
@ -57,17 +41,6 @@ extern "C" {
*/ */
#define CPUID_ID_LEN (12) #define CPUID_ID_LEN (12)
/**
* @name Definition of different panic modes
*/
typedef enum {
HARD_FAULT,
WATCHDOG,
BUS_FAULT,
USAGE_FAULT,
DUMMY_HANDLER
} panic_t;
#define TRANSCEIVER_BUFFER_SIZE (3) #define TRANSCEIVER_BUFFER_SIZE (3)
#ifdef __cplusplus #ifdef __cplusplus

2
cpu/stm32l1/include/stm32l1xx.h
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@ -179,7 +179,7 @@ typedef enum IRQn
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */

9
cpu/stm32l1/startup.c
View File

@ -82,8 +82,7 @@ void reset_handler(void)
*/ */
void dummy_handler(void) void dummy_handler(void)
{ {
core_panic(DUMMY_HANDLER, "DUMMY HANDLER"); core_panic(PANIC_DUMMY_HANDLER, "DUMMY HANDLER");
while (1) {asm ("nop");}
} }
void isr_nmi(void) void isr_nmi(void)
@ -103,19 +102,19 @@ void isr_debug_mon(void)
void isr_hard_fault(void) void isr_hard_fault(void)
{ {
core_panic(HARD_FAULT, "HARD FAULT"); core_panic(PANIC_HARD_FAULT, "HARD FAULT");
while (1) {asm ("nop");} while (1) {asm ("nop");}
} }
void isr_bus_fault(void) void isr_bus_fault(void)
{ {
core_panic(BUS_FAULT, "BUS FAULT"); core_panic(PANIC_BUS_FAULT, "BUS FAULT");
while (1) {asm ("nop");} while (1) {asm ("nop");}
} }
void isr_usage_fault(void) void isr_usage_fault(void)
{ {
core_panic(USAGE_FAULT, "USAGE FAULT"); core_panic(PANIC_USAGE_FAULT, "USAGE FAULT");
while (1) {asm ("nop");} while (1) {asm ("nop");}
} }