From f9631953cb67a92928d8e021b43f3a413bfd0217 Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Sun, 13 Oct 2019 17:18:08 +0200 Subject: [PATCH] boards: add common sodaq module --- boards/common/sodaq/Makefile | 3 + boards/common/sodaq/Makefile.dep | 3 + boards/common/sodaq/Makefile.features | 11 +++ boards/common/sodaq/Makefile.include | 14 ++++ boards/common/sodaq/board.c | 31 +++++++ boards/common/sodaq/include/board_common.h | 38 +++++++++ .../common/sodaq/include/cfg_clock_default.h | 83 +++++++++++++++++++ boards/common/sodaq/include/cfg_rtc_default.h | 44 ++++++++++ boards/common/sodaq/include/cfg_rtt_default.h | 50 +++++++++++ boards/common/sodaq/include/cfg_spi_default.h | 57 +++++++++++++ .../common/sodaq/include/cfg_timer_default.h | 80 ++++++++++++++++++ .../common/sodaq/include/cfg_usbdev_default.h | 50 +++++++++++ 12 files changed, 464 insertions(+) create mode 100644 boards/common/sodaq/Makefile create mode 100644 boards/common/sodaq/Makefile.dep create mode 100644 boards/common/sodaq/Makefile.features create mode 100644 boards/common/sodaq/Makefile.include create mode 100644 boards/common/sodaq/board.c create mode 100644 boards/common/sodaq/include/board_common.h create mode 100644 boards/common/sodaq/include/cfg_clock_default.h create mode 100644 boards/common/sodaq/include/cfg_rtc_default.h create mode 100644 boards/common/sodaq/include/cfg_rtt_default.h create mode 100644 boards/common/sodaq/include/cfg_spi_default.h create mode 100644 boards/common/sodaq/include/cfg_timer_default.h create mode 100644 boards/common/sodaq/include/cfg_usbdev_default.h diff --git a/boards/common/sodaq/Makefile b/boards/common/sodaq/Makefile new file mode 100644 index 0000000000..6792d1f556 --- /dev/null +++ b/boards/common/sodaq/Makefile @@ -0,0 +1,3 @@ +MODULE = boards_common_sodaq + +include $(RIOTBASE)/Makefile.base diff --git a/boards/common/sodaq/Makefile.dep b/boards/common/sodaq/Makefile.dep new file mode 100644 index 0000000000..5472bf8b8d --- /dev/null +++ b/boards/common/sodaq/Makefile.dep @@ -0,0 +1,3 @@ +ifneq (,$(filter saul_default,$(USEMODULE))) + USEMODULE += saul_gpio +endif diff --git a/boards/common/sodaq/Makefile.features b/boards/common/sodaq/Makefile.features new file mode 100644 index 0000000000..9db14a6d10 --- /dev/null +++ b/boards/common/sodaq/Makefile.features @@ -0,0 +1,11 @@ +CPU = samd21 + +# Put defined MCU peripherals here (in alphabetical order) +FEATURES_PROVIDED += periph_adc +FEATURES_PROVIDED += periph_i2c +FEATURES_PROVIDED += periph_rtc +FEATURES_PROVIDED += periph_rtt +FEATURES_PROVIDED += periph_spi +FEATURES_PROVIDED += periph_timer +FEATURES_PROVIDED += periph_uart +FEATURES_PROVIDED += periph_usbdev diff --git a/boards/common/sodaq/Makefile.include b/boards/common/sodaq/Makefile.include new file mode 100644 index 0000000000..8db3929a94 --- /dev/null +++ b/boards/common/sodaq/Makefile.include @@ -0,0 +1,14 @@ +PORT_LINUX ?= /dev/ttyACM0 +PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*))) + +# setup serial terminal +include $(RIOTMAKE)/tools/serial.inc.mk + +# Add board common includes +INCLUDES += -I$(RIOTBOARD)/common/sodaq/include + +# setup the flash tool used +# we use BOSSA to flash this board since there's an Arduino bootloader +# preflashed on it. ROM_OFFSET skips the space taken by such bootloader. +ROM_OFFSET ?= 0x2000 +include $(RIOTMAKE)/tools/bossa.inc.mk diff --git a/boards/common/sodaq/board.c b/boards/common/sodaq/board.c new file mode 100644 index 0000000000..5f0195d148 --- /dev/null +++ b/boards/common/sodaq/board.c @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2016 Kees Bakker, SODAQ + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_common_sodaq + * @{ + * + * @file + * @brief Board common implementations for the SODAQ boards + * + * @author Kees Bakker + * + * @} + */ + +#include "board.h" +#include "periph/gpio.h" + +void board_init(void) +{ + /* initialize the on-board LED */ + gpio_init(LED0_PIN, GPIO_OUT); + + /* initialize the CPU */ + cpu_init(); +} diff --git a/boards/common/sodaq/include/board_common.h b/boards/common/sodaq/include/board_common.h new file mode 100644 index 0000000000..176eab6de3 --- /dev/null +++ b/boards/common/sodaq/include/board_common.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2016 Kees Bakker, SODAQ + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @defgroup boards_common_sodaq SODAQ boards common + * @ingroup boards_common + * @brief Common support for all SODAQ boards + * @{ + * + * @file + * @brief Board common definitions for the SODAQ boards + * + * @author Kees Bakker + */ + +#ifndef BOARD_COMMON_H +#define BOARD_COMMON_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Initialize board specific hardware, including clock, LEDs and std-IO + */ +void board_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* BOARD_COMMON_H */ +/** @} */ diff --git a/boards/common/sodaq/include/cfg_clock_default.h b/boards/common/sodaq/include/cfg_clock_default.h new file mode 100644 index 0000000000..eccc6794b7 --- /dev/null +++ b/boards/common/sodaq/include/cfg_clock_default.h @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2016 Kees Bakker, SODAQ + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_common_sodaq + * @{ + * + * @file + * @brief Default clock configuration for SODAQ boards + * + * @author Kees Bakker + */ + +#ifndef CFG_CLOCK_DEFAULT_H +#define CFG_CLOCK_DEFAULT_H + +#include + +#include "cpu.h" +#include "periph_cpu.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name External oscillator and clock configuration + * + * For selection of the used CORECLOCK, we have implemented two choices: + * + * - usage of the PLL fed by the internal 8MHz oscillator divided by 8 + * - usage of the internal 8MHz oscillator directly, divided by N if needed + * + * + * The PLL option allows for the usage of a wider frequency range and a more + * stable clock with less jitter. This is why we use this option as default. + * + * The target frequency is computed from the PLL multiplier and the PLL divisor. + * Use the following formula to compute your values: + * + * CORECLOCK = ((PLL_MUL + 1) * 1MHz) / PLL_DIV + * + * NOTE: The PLL circuit does not run with less than 32MHz while the maximum PLL + * frequency is 96MHz. So PLL_MULL must be between 31 and 95! + * + * + * The internal Oscillator used directly can lead to a slightly better power + * efficiency to the cost of a less stable clock. Use this option when you know + * what you are doing! The actual core frequency is adjusted as follows: + * + * CORECLOCK = 8MHz / DIV + * + * NOTE: A core clock frequency below 1MHz is not recommended + * + * @{ + */ +#define CLOCK_USE_PLL (1) + +#if CLOCK_USE_PLL +/* edit these values to adjust the PLL output frequency */ +#define CLOCK_PLL_MUL (47U) /* must be >= 31 & <= 95 */ +#define CLOCK_PLL_DIV (1U) /* adjust to your needs */ +/* generate the actual used core clock frequency */ +#define CLOCK_CORECLOCK (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV) +#else +/* edit this value to your needs */ +#define CLOCK_DIV (1U) +/* generate the actual core clock frequency */ +#define CLOCK_CORECLOCK (8000000 / CLOCK_DIV) +#endif +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* CFG_CLOCK_DEFAULT_H */ +/** @} */ diff --git a/boards/common/sodaq/include/cfg_rtc_default.h b/boards/common/sodaq/include/cfg_rtc_default.h new file mode 100644 index 0000000000..945267e680 --- /dev/null +++ b/boards/common/sodaq/include/cfg_rtc_default.h @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2016 Kees Bakker, SODAQ + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_common_sodaq + * @{ + * + * @file + * @brief Default RTC configuration for SODAQ boards + * + * @author Kees Bakker + */ + +#ifndef CFG_RTC_DEFAULT_H +#define CFG_RTC_DEFAULT_H + +#include + +#include "cpu.h" +#include "periph_cpu.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name RTC configuration + * @{ + */ +#define RTC_NUMOF (1U) +#define RTC_DEV RTC->MODE2 +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* CFG_RTC_DEFAULT_H */ +/** @} */ diff --git a/boards/common/sodaq/include/cfg_rtt_default.h b/boards/common/sodaq/include/cfg_rtt_default.h new file mode 100644 index 0000000000..4f4df16d1e --- /dev/null +++ b/boards/common/sodaq/include/cfg_rtt_default.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2016 Kees Bakker, SODAQ + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_common_sodaq + * @{ + * + * @file + * @brief Default RTT configuration for SODAQ boards + * + * @author Kees Bakker + */ + +#ifndef CFG_RTT_DEFAULT_H +#define CFG_RTT_DEFAULT_H + +#include + +#include "cpu.h" +#include "periph_cpu.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name RTT configuration + * @{ + */ +#define RTT_NUMOF (1U) +#define RTT_DEV RTC->MODE0 +#define RTT_IRQ RTC_IRQn +#define RTT_IRQ_PRIO 10 +#define RTT_ISR isr_rtc +#define RTT_MAX_VALUE (0xffffffff) +#define RTT_FREQUENCY (32768U) /* in Hz. For changes see `rtt.c` */ +#define RTT_RUNSTDBY (1) /* Keep RTT running in sleep states */ +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* CFG_RTT_DEFAULT_H */ +/** @} */ diff --git a/boards/common/sodaq/include/cfg_spi_default.h b/boards/common/sodaq/include/cfg_spi_default.h new file mode 100644 index 0000000000..0ff93757bf --- /dev/null +++ b/boards/common/sodaq/include/cfg_spi_default.h @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2016 Kees Bakker, SODAQ + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_common_sodaq + * @{ + * + * @file + * @brief Default SPI configuration for SODAQ boards + * + * @author Kees Bakker + */ + +#ifndef CFG_SPI_DEFAULT_H +#define CFG_SPI_DEFAULT_H + +#include + +#include "cpu.h" +#include "periph_cpu.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name SPI configuration + * @{ + */ +static const spi_conf_t spi_config[] = { + { + .dev = &SERCOM3->SPI, + .miso_pin = GPIO_PIN(PA, 22), + .mosi_pin = GPIO_PIN(PA, 20), + .clk_pin = GPIO_PIN(PA, 21), + .miso_mux = GPIO_MUX_C, + .mosi_mux = GPIO_MUX_D, + .clk_mux = GPIO_MUX_D, + .miso_pad = SPI_PAD_MISO_0, + .mosi_pad = SPI_PAD_MOSI_2_SCK_3, + }, +}; + +#define SPI_NUMOF ARRAY_SIZE(spi_config) +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* CFG_SPI_DEFAULT_H */ +/** @} */ diff --git a/boards/common/sodaq/include/cfg_timer_default.h b/boards/common/sodaq/include/cfg_timer_default.h new file mode 100644 index 0000000000..9e81ea8b52 --- /dev/null +++ b/boards/common/sodaq/include/cfg_timer_default.h @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2016 Kees Bakker, SODAQ + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_sodaq-autonomo + * @{ + * + * @file + * @brief Default timer configuration for SODAQ boards + * + * @author Kees Bakker + */ + +#ifndef CFG_TIMER_DEFAULT_H +#define CFG_TIMER_DEFAULT_H + +#include + +#include "cpu.h" +#include "periph_cpu.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Timer peripheral configuration + * @{ + */ +static const tc32_conf_t timer_config[] = { + { /* Timer 0 - System Clock */ + .dev = TC3, + .irq = TC3_IRQn, + .pm_mask = PM_APBCMASK_TC3, + .gclk_ctrl = GCLK_CLKCTRL_ID_TCC2_TC3, +#if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL + .gclk_src = GCLK_CLKCTRL_GEN(1), + .prescaler = TC_CTRLA_PRESCALER_DIV1, +#else + .gclk_src = GCLK_CLKCTRL_GEN(0), + .prescaler = TC_CTRLA_PRESCALER_DIV8, +#endif + .flags = TC_CTRLA_MODE_COUNT16, + }, + { /* Timer 1 */ + .dev = TC4, + .irq = TC4_IRQn, + .pm_mask = PM_APBCMASK_TC4 | PM_APBCMASK_TC5, + .gclk_ctrl = GCLK_CLKCTRL_ID_TC4_TC5, +#if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL + .gclk_src = GCLK_CLKCTRL_GEN(1), + .prescaler = TC_CTRLA_PRESCALER_DIV1, +#else + .gclk_src = GCLK_CLKCTRL_GEN(0), + .prescaler = TC_CTRLA_PRESCALER_DIV8, +#endif + .flags = TC_CTRLA_MODE_COUNT32, + } +}; + +#define TIMER_0_MAX_VALUE 0xffff + +/* interrupt function name mapping */ +#define TIMER_0_ISR isr_tc3 +#define TIMER_1_ISR isr_tc4 + +#define TIMER_NUMOF ARRAY_SIZE(timer_config) +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* CFG_TIMER_DEFAULT_H */ +/** @} */ diff --git a/boards/common/sodaq/include/cfg_usbdev_default.h b/boards/common/sodaq/include/cfg_usbdev_default.h new file mode 100644 index 0000000000..49d93e506e --- /dev/null +++ b/boards/common/sodaq/include/cfg_usbdev_default.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2016 Kees Bakker, SODAQ + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_common_sodaq + * @{ + * + * @file + * @brief Default usbdev configuration for SODAQ boards + * + * @author Kees Bakker + */ + +#ifndef CFG_USBDEV_DEFAULT_H +#define CFG_USBDEV_DEFAULT_H + +#include + +#include "cpu.h" +#include "periph_cpu.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name USB peripheral configuration + * @{ + */ +static const sam0_common_usb_config_t sam_usbdev_config[] = { + { + .dm = GPIO_PIN(PA, 24), + .dp = GPIO_PIN(PA, 25), + .d_mux = GPIO_MUX_G, + .device = &USB->DEVICE, + } +}; +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* CFG_USBDEV_DEFAULT_H */ +/** @} */