From f98e286d08a4885c4b9f89a24e421c70f9561692 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Fri, 4 Aug 2017 13:49:37 +0200 Subject: [PATCH] k22f: Remove unused MK22F10.h header According to NXP material, there are no 100 MHz K22F parts in 144 pin packages, which is the reference manual that this header is supposed to correspond to. The header was originally included from Keil uVision Kinetis support packages. It is possible that this header was only used with engineering samples of the K22F. --- cpu/k22f/include/vendor/MK22F10.h | 8478 ----------------------------- 1 file changed, 8478 deletions(-) delete mode 100644 cpu/k22f/include/vendor/MK22F10.h diff --git a/cpu/k22f/include/vendor/MK22F10.h b/cpu/k22f/include/vendor/MK22F10.h deleted file mode 100644 index 21aaaac621..0000000000 --- a/cpu/k22f/include/vendor/MK22F10.h +++ /dev/null @@ -1,8478 +0,0 @@ -/* -** ################################################################### -** Compilers: ARM Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K22P144M100SF5RM, Rev.1, Nov 2012 -** Version: rev. 1.2, 2012-12-04 -** -** Abstract: -** CMSIS Peripheral Access Layer for MK22F10 -** -** Copyright: 1997 - 2012 Freescale, Inc. All Rights Reserved. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2012-06-06) -** Initial version. -** - rev. 1.1 (2012-11-12) -** Update according to reference manual rev.1, draft B -** - rev. 1.2 (2012-12-04) -** Update according to reference manual rev.1 -** -** ################################################################### -*/ - -/** - * @file MK22F10.h - * @version 1.2 - * @date 2012-12-04 - * @brief CMSIS Peripheral Access Layer for MK22F10 - * - * CMSIS Peripheral Access Layer for MK22F10 - */ - -#if !defined(MK22F10_H_) -#define MK22F10_H_ /**< Symbol preventing repeated inclusion */ - -/** Memory map major version (memory maps with equal major version number are - * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100u -/** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0002u - -/** - * @brief Macro to access a single bit of a peripheral register (bit band region - * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Value of the targeted bit in the bit band region. - */ -#define BITBAND_REG(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))))) - -/* ---------------------------------------------------------------------------- - -- Interrupt vector numbers - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup Interrupt_vector_numbers Interrupt vector numbers - * @{ - */ - -/** Interrupt Number Definitions */ -typedef enum IRQn { - /* Core interrupts */ - NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ - HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ - - /* Device specific interrupts */ - DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */ - DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */ - DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */ - DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */ - DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */ - DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */ - DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */ - DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */ - DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */ - DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */ - DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */ - DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */ - DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */ - DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */ - DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */ - DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */ - DMA_Error_IRQn = 16, /**< DMA Error Interrupt */ - MCM_IRQn = 17, /**< Normal Interrupt */ - FTFL_IRQn = 18, /**< FTFL Command complete interrupt */ - Read_Collision_IRQn = 19, /**< Read Collision Interrupt */ - LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */ - LLW_IRQn = 21, /**< Low Leakage Wakeup */ - Watchdog_IRQn = 22, /**< WDOG Interrupt */ - Reserved39_IRQn = 23, /**< Reserved Interrupt 39 */ - I2C0_IRQn = 24, /**< I2C0 interrupt */ - I2C1_IRQn = 25, /**< I2C1 interrupt */ - SPI0_IRQn = 26, /**< SPI0 Interrupt */ - SPI1_IRQn = 27, /**< SPI1 Interrupt */ - I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */ - I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */ - UART0_LON_IRQn = 30, /**< UART0 LON interrupt */ - UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */ - UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */ - UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */ - UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */ - UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */ - UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */ - UART3_RX_TX_IRQn = 37, /**< UART3 Receive/Transmit interrupt */ - UART3_ERR_IRQn = 38, /**< UART3 Error interrupt */ - ADC0_IRQn = 39, /**< ADC0 interrupt */ - CMP0_IRQn = 40, /**< CMP0 interrupt */ - CMP1_IRQn = 41, /**< CMP1 interrupt */ - FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */ - FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */ - FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */ - CMT_IRQn = 45, /**< CMT interrupt */ - RTC_IRQn = 46, /**< RTC interrupt */ - RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */ - PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */ - PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */ - PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */ - PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */ - PDB0_IRQn = 52, /**< PDB0 Interrupt */ - USB0_IRQn = 53, /**< USB0 interrupt */ - USBDCD_IRQn = 54, /**< USBDCD Interrupt */ - Reserved71_IRQn = 55, /**< Reserved interrupt 71 */ - DAC0_IRQn = 56, /**< DAC0 interrupt */ - MCG_IRQn = 57, /**< MCG Interrupt */ - LPTimer_IRQn = 58, /**< LPTimer interrupt */ - PORTA_IRQn = 59, /**< Port A interrupt */ - PORTB_IRQn = 60, /**< Port B interrupt */ - PORTC_IRQn = 61, /**< Port C interrupt */ - PORTD_IRQn = 62, /**< Port D interrupt */ - PORTE_IRQn = 63, /**< Port E interrupt */ - SWI_IRQn = 64, /**< Software interrupt */ - SPI2_IRQn = 65, /**< SPI2 Interrupt */ - UART4_RX_TX_IRQn = 66, /**< UART4 Receive/Transmit interrupt */ - UART4_ERR_IRQn = 67, /**< UART4 Error interrupt */ - UART5_RX_TX_IRQn = 68, /**< UART5 Receive/Transmit interrupt */ - UART5_ERR_IRQn = 69, /**< UART5 Error interrupt */ - CMP2_IRQn = 70, /**< CMP2 interrupt */ - FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */ - DAC1_IRQn = 72, /**< DAC1 interrupt */ - ADC1_IRQn = 73, /**< ADC1 interrupt */ - I2C2_IRQn = 74, /**< I2C2 interrupt */ - CAN0_ORed_Message_buffer_IRQn = 75, /**< CAN0 OR'd message buffers interrupt */ - CAN0_Bus_Off_IRQn = 76, /**< CAN0 bus off interrupt */ - CAN0_Error_IRQn = 77, /**< CAN0 error interrupt */ - CAN0_Tx_Warning_IRQn = 78, /**< CAN0 Tx warning interrupt */ - CAN0_Rx_Warning_IRQn = 79, /**< CAN0 Rx warning interrupt */ - CAN0_Wake_Up_IRQn = 80, /**< CAN0 wake up interrupt */ - SDHC_IRQn = 81 /**< SDHC interrupt */ -} IRQn_Type; - -/** - * @} - */ /* end of group Interrupt_vector_numbers */ - - -/* ---------------------------------------------------------------------------- - -- Cortex M4 Core Configuration - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration - * @{ - */ - -#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ -#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ -#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ -#define __FPU_PRESENT 1 /**< FPU present or not */ - -#include "core_cm4.h" /* Core Peripheral Access Layer */ - -/** - * @} - */ /* end of group Cortex_Core_Configuration */ - - -/* ---------------------------------------------------------------------------- - -- Device Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup Peripheral_access_layer Device Peripheral Access Layer - * @{ - */ - - -/* -** Start of section using anonymous unions -*/ - -#if defined(__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" - #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" - #pragma clang diagnostic ignored "-Wnested-anon-types" -#elif defined(__CWCC__) - #pragma push - #pragma cpp_extensions on -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/* ---------------------------------------------------------------------------- - -- ADC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer - * @{ - */ - -/** ADC - Register Layout Typedef */ -typedef struct { - __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */ - __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ - __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */ - __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */ - __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */ - __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */ - __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */ - __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */ - __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */ - __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */ - __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */ - __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */ - __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */ - __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */ - __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */ - __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */ - __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */ - __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */ - uint8_t RESERVED_0[4]; - __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */ - __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */ - __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */ - __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */ - __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ - __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ - __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ -} ADC_Type; - -/* ---------------------------------------------------------------------------- - -- ADC Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup ADC_Register_Masks ADC Register Masks - * @{ - */ - -/* SC1 Bit Fields */ -#define ADC_SC1_ADCH_MASK 0x1Fu -#define ADC_SC1_ADCH_SHIFT 0 -#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<= 6010050) - #pragma clang diagnostic pop -#elif defined(__CWCC__) - #pragma pop -#elif defined(__GNUC__) - /* leave anonymous unions enabled */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=default -#else - #error Not supported compiler type -#endif - -/** - * @} - */ /* end of group Peripheral_access_layer */ - - -/* ---------------------------------------------------------------------------- - -- Backward Compatibility - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup Backward_Compatibility_Symbols Backward Compatibility - * @{ - */ - -#define GPIOA_BASE PTA_BASE -#define GPIOB_BASE PTB_BASE -#define GPIOC_BASE PTC_BASE -#define GPIOD_BASE PTD_BASE -#define GPIOE_BASE PTE_BASE -#define GPIOF_BASE PTF_BASE -#define GPIOG_BASE PTG_BASE -#define GPIOA PTA -#define GPIOB PTB -#define GPIOC PTC -#define GPIOD PTD -#define GPIOE PTE -#define GPIOF PTF -#define GPIOG PTG -#define OSC0 OSC - -/** - * @} - */ /* end of group Backward_Compatibility_Symbols */ - - -#endif /* #if !defined(MK22F10_H_) */ - -/* MK22F10.h, eof. */