diff --git a/cpu/stm32/stmclk/stmclk_gx.c b/cpu/stm32/stmclk/stmclk_gx.c
index f02d80de9a..72eed33fc2 100644
--- a/cpu/stm32/stmclk/stmclk_gx.c
+++ b/cpu/stm32/stmclk/stmclk_gx.c
@@ -20,6 +20,7 @@
 #include "cpu.h"
 #include "stmclk.h"
 #include "periph_conf.h"
+#include "periph/gpio.h"
 
 #if defined(CPU_FAM_STM32G0)
 #define PLL_M_MIN                   (1)
@@ -131,10 +132,149 @@
 #endif
 #endif /* CPU_FAM_STM32G4 */
 
+/* Configure MCO */
+#ifndef CONFIG_CLOCK_ENABLE_MCO
+#define CONFIG_CLOCK_ENABLE_MCO     0   /* Don't enable MCO by default */
+#endif
+
+/* Configure the MCO clock source: options are PLLCLK (default), HSE, HSI, LSE, LSI or SYSCLK*/
+#ifndef CONFIG_CLOCK_MCO_USE_PLLCLK
+#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI) || \
+    IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSI) || \
+    IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK)
+#define CONFIG_CLOCK_MCO_USE_PLLCLK 0
+#else
+#define CONFIG_CLOCK_MCO_USE_PLLCLK 1   /* Use PLLCLK by default */
+#endif
+#endif /* CONFIG_CLOCK_MCO_USE_PLLCLK */
+
+#ifndef CONFIG_CLOCK_MCO_USE_HSE
+#define CONFIG_CLOCK_MCO_USE_HSE    0
+#endif /* CONFIG_CLOCK_MCO_USE_HSE */
+
+#ifndef CONFIG_CLOCK_MCO_USE_HSI
+#define CONFIG_CLOCK_MCO_USE_HSI    0
+#endif /* CONFIG_CLOCK_MCO_USE_HSI */
+
+#ifndef CONFIG_CLOCK_MCO_USE_LSE
+#define CONFIG_CLOCK_MCO_USE_LSE    0
+#endif /* CONFIG_CLOCK_MCO_USE_LSE */
+
+#ifndef CONFIG_CLOCK_MCO_USE_LSI
+#define CONFIG_CLOCK_MCO_USE_LSI    0
+#endif /* CONFIG_CLOCK_MCO_USE_LSI */
+
+#ifndef CONFIG_CLOCK_MCO_USE_SYSCLK
+#define CONFIG_CLOCK_MCO_USE_SYSCLK 0
+#endif /* CONFIG_CLOCK_MCO_USE_SYSCLK */
+
+#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_PLLCLK) && \
+    (IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI) || \
+     IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSI) || \
+     IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK))
+#error "Cannot use PLLCLK as MCO clock source with other clocks"
+#endif
+
+#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE) && \
+    (IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSE) || \
+     IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSI) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_PLLCLK) || \
+     IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK))
+#error "Cannot use HSE as MCO clock source with other clocks"
+#endif
+
+#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI) && \
+    (IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSE) || \
+     IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSI) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_PLLCLK) || \
+     IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK))
+#error "Cannot use HSI as MCO clock source with other clocks"
+#endif
+
+#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSE) && \
+    (IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI) || \
+     IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSI) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_PLLCLK) || \
+     IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK))
+#error "Cannot use LSE as MCO clock source with other clocks"
+#endif
+
+#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSI) && \
+    (IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI) || \
+     IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_PLLCLK) || \
+     IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK))
+#error "Cannot use LSI as MCO clock source with other clocks"
+#endif
+
+#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK) && \
+    (IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI) || \
+     IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSI) || \
+     IS_ACTIVE(CONFIG_CLOCK_MCO_USE_PLLCLK))
+#error "Cannot use SYSCLK as MCO clock source with other clocks"
+#endif
+
+#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK)
+#define CLOCK_MCO_SRC                           (RCC_CFGR_MCOSEL_0)
+#elif IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI)
+#define CLOCK_MCO_SRC                           (RCC_CFGR_MCOSEL_1 | RCC_CFGR_MCOSEL_0)
+#elif IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE)
+#define CLOCK_MCO_SRC                           (RCC_CFGR_MCOSEL_2)
+#elif IS_ACTIVE(CONFIG_CLOCK_MCO_USE_PLLCLK)
+#define CLOCK_MCO_SRC                           (RCC_CFGR_MCOSEL_2 | RCC_CFGR_MCOSEL_0)
+#elif IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSI)
+#define CLOCK_MCO_SRC                           (RCC_CFGR_MCOSEL_2 | RCC_CFGR_MCOSEL_1)
+#elif IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSE)
+#define CLOCK_MCO_SRC                           (RCC_CFGR_MCOSEL_2 | RCC_CFGR_MCOSEL_1 | RCC_CFGR_MCOSEL_0)
+#else
+#error "Invalid MCO clock source selection"
+#endif
+
+/* Configure the MCO prescaler: valid values are 1, 2, 4, 8, 16 on G4
+   and 1, 2, 4, 8, 16, 32, 64, 128 on G0 */
+#ifndef CONFIG_CLOCK_MCO_PRE
+#define CONFIG_CLOCK_MCO_PRE                    (1)
+#endif
+
+/* Define MCO prescalers for G0 for compatibility with G4 */
+#if defined(CPU_FAM_STM32G0)
+#if CONFIG_CLOCK_MCO_PRE == 1
+#define CLOCK_MCO_PRE                           (0)
+#elif CONFIG_CLOCK_MCO_PRE == 2
+#define CLOCK_MCO_PRE                           (RCC_CFGR_MCOPRE_0)
+#elif CONFIG_CLOCK_MCO_PRE == 4
+#define CLOCK_MCO_PRE                           (RCC_CFGR_MCOPRE_1)
+#elif CONFIG_CLOCK_MCO_PRE == 8
+#define CLOCK_MCO_PRE                           (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0)
+#elif CONFIG_CLOCK_MCO_PRE == 16
+#define CLOCK_MCO_PRE                           (RCC_CFGR_MCOPRE_2)
+#elif CONFIG_CLOCK_MCO_PRE == 32
+#define CLOCK_MCO_PRE                           (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_0)
+#elif CONFIG_CLOCK_MCO_PRE == 64
+#define CLOCK_MCO_PRE                           (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1)
+#elif CONFIG_CLOCK_MCO_PRE == 128
+#define CLOCK_MCO_PRE                           (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0)
+#else
+#error "Invalid MCO prescaler"
+#endif
+#else /* CPU_FAM_STM32G4 */
+#if CONFIG_CLOCK_MCO_PRE == 1
+#define CLOCK_MCO_PRE                           (RCC_CFGR_MCOPRE_DIV1)
+#elif CONFIG_CLOCK_MCO_PRE == 2
+#define CLOCK_MCO_PRE                           (RCC_CFGR_MCOPRE_DIV2)
+#elif CONFIG_CLOCK_MCO_PRE == 4
+#define CLOCK_MCO_PRE                           (RCC_CFGR_MCOPRE_DIV4)
+#elif CONFIG_CLOCK_MCO_PRE == 8
+#define CLOCK_MCO_PRE                           (RCC_CFGR_MCOPRE_DIV8)
+#elif CONFIG_CLOCK_MCO_PRE == 16
+#define CLOCK_MCO_PRE                           (RCC_CFGR_MCOPRE_DIV16)
+#else
+#error "Invalid MCO prescaler"
+#endif
+#endif
+
 /* Check whether PLL must be enabled:
   - When PLLCLK is used as SYSCLK
+  - When PLLCLK is used as MCO clock source
 */
-#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
+#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || \
+    (IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO) && IS_ACTIVE(CONFIG_CLOCK_MCO_USE_PLLCLK))
 #define CLOCK_ENABLE_PLL            1
 #else
 #define CLOCK_ENABLE_PLL            0
@@ -144,9 +284,11 @@
   - When HSE is used as SYSCLK
   - When PLL is used as SYSCLK and the board provides HSE (since HSE will be
     used as PLL input clock)
+  - When HSE is used as MCO clock source
 */
 #if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || \
-    (IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && IS_ACTIVE(CONFIG_USE_CLOCK_PLL))
+    (IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && IS_ACTIVE(CONFIG_USE_CLOCK_PLL)) || \
+    (IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO) && IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE))
 #define CLOCK_ENABLE_HSE            1
 #else
 #define CLOCK_ENABLE_HSE            0
@@ -156,14 +298,29 @@
   - When HSI is used as SYSCLK
   - When PLL is used as SYSCLK and the board doesn't provide HSE (since HSI will be
     used as PLL input clock)
+  - When HSI is used as MCO clock source
 */
 #if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) || \
-    (!IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && IS_ACTIVE(CONFIG_USE_CLOCK_PLL))
+    (!IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && IS_ACTIVE(CONFIG_USE_CLOCK_PLL)) || \
+    (IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO) && IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI))
 #define CLOCK_ENABLE_HSI            1
 #else
 #define CLOCK_ENABLE_HSI            0
 #endif
 
+/* Check whether LSE must be enabled */
+#if IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO) && IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSE)
+#define CLOCK_ENABLE_LSE            1
+#else
+#define CLOCK_ENABLE_LSE            0
+#endif
+
+/* Check whether LSI must be enabled */
+#if IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO) && IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSI)
+#define CLOCK_ENABLE_LSI            1
+#else
+#define CLOCK_ENABLE_LSI            0
+#endif
 
 /** Determine the required flash wait states from the core clock frequency */
 #if defined(CPU_FAM_STM32G0)
@@ -279,6 +436,38 @@ void stmclk_init_sysclk(void)
         stmclk_disable_hsi();
     }
 
+    /* Enable the LSE if required for MCO
+     * If available on the board, LSE might also be initialized for RTT/RTC
+     * peripherals. For the monent, this initialization is done in the
+     * corresponding peripheral drivers. */
+    if (IS_ACTIVE(CLOCK_ENABLE_LSE)) {
+        stmclk_dbp_unlock();
+        RCC->BDCR |= RCC_BDCR_LSEON;
+        while (!(RCC->BDCR & RCC_BDCR_LSERDY)) {}
+        stmclk_dbp_lock();
+    }
+
+    /* Enable the LSI if required for MCO
+     * If no LSE is available on the board, LSI might also be initialized for
+     * RTT/RTC peripherals. For the monent, this initialization is done in the
+     * corresponding peripheral drivers. */
+    if (IS_ACTIVE(CLOCK_ENABLE_LSI)) {
+        RCC->CSR |= RCC_CSR_LSION;
+        while (!(RCC->CSR & RCC_CSR_LSIRDY)) {}
+    }
+
+    /* Configure MCO */
+    if (IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO)) {
+        /* As stated in the manual, it is highly recommended to change the MCO
+           prescaler before enabling the MCO */
+        RCC->CFGR |= CLOCK_MCO_PRE;
+        RCC->CFGR |= CLOCK_MCO_SRC;
+
+        /* Configure MCO pin (PA8 with AF0) */
+        gpio_init(GPIO_PIN(PORT_A, 8), GPIO_OUT);
+        gpio_init_af(GPIO_PIN(PORT_A, 8), GPIO_AF0);
+    }
+
 #if IS_USED(MODULE_PERIPH_HWRNG)
     /* HWRNG is clocked by HSI48 so enable this clock when the peripheral is used */
     RCC->CRRCR |= RCC_CRRCR_HSI48ON;