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Merge pull request #7500 from OTAkeys/pr/stmclk_f0_f1

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cpu/stm32f[0|1|3] unify stmclk with stm32_common
This commit is contained in:
Alexandre Abadie 2017-09-01 10:21:25 +02:00 committed by GitHub
commit fc63f9956e
21 changed files with 589 additions and 574 deletions
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34
boards/nucleo-f030/include/periph_conf.h
View File

@ -28,20 +28,32 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
#define CLOCK_HSE (8000000U) /* external oscillator */ /* give the target core clock (HCLK) frequency [in Hz],
#define CLOCK_CORECLOCK (48000000U) /* desired core clock frequency */ * maximum: 48MHz */
#define CLOCK_CORECLOCK (48000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_APB1)
/* the actual PLL values are automatically generated */ /* PLL factors */
#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE) #define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (6)
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */ /** @} */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
/** @} */
/** /**
* @name Timer configuration * @name Timer configuration

34
boards/nucleo-f070/include/periph_conf.h
View File

@ -28,20 +28,32 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
#define CLOCK_HSE (8000000U) /* external oscillator */ /* give the target core clock (HCLK) frequency [in Hz],
#define CLOCK_CORECLOCK (48000000U) /* desired core clock frequency */ * maximum: 48MHz */
#define CLOCK_CORECLOCK (48000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_APB1)
/* the actual PLL values are automatically generated */ /* PLL factors */
#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE) #define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (6)
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */ /** @} */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
/** @} */
/** /**
* @name Timer configuration * @name Timer configuration

34
boards/nucleo-f072/include/periph_conf.h
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@ -27,20 +27,32 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
#define CLOCK_HSE (8000000U) /* external oscillator */ /* give the target core clock (HCLK) frequency [in Hz],
#define CLOCK_CORECLOCK (48000000U) /* desired core clock frequency */ * maximum: 48MHz */
#define CLOCK_CORECLOCK (48000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_APB1)
/* the actual PLL values are automatically generated */ /* PLL factors */
#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE) #define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (6)
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */ /** @} */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
/** @} */
/** /**
* @name Timer configuration * @name Timer configuration

32
boards/nucleo-f091/include/periph_conf.h
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@ -26,19 +26,31 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
#define CLOCK_HSE (8000000U) /* external oscillator */ /* give the target core clock (HCLK) frequency [in Hz],
#define CLOCK_CORECLOCK (48000000U) /* desired core clock frequency */ * maximum: 48MHz */
#define CLOCK_CORECLOCK (48000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_APB1)
/* the actual PLL values are automatically generated */ /* PLL factors */
#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE) #define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (6)
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
/** @} */ /** @} */
/** /**

53
boards/nucleo-f103/include/periph_conf.h
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@ -26,37 +26,32 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
**/
/* high speed clock configuration:
* 0 := use internal HSI oscillator (always 8MHz)
* HSE frequency value := use external HSE oscillator with given freq [in Hz]
* must be 4000000 <= value <= 16000000 */
#define CLOCK_HSE (8000000U)
/* low speed clock configuration:
* 0 := use internal LSI oscillator (~40kHz)
* 1 := use extern LSE oscillator, always 32.768kHz */
#define CLOCK_LSE (1)
/* targeted system clock speed [in Hz], must be <= 72MHz */
#define CLOCK_CORECLOCK (72000000U)
/* PLL configuration, set both values to zero to disable PLL usage. The values
* must be set to satisfy the following equation:
* CORECLOCK := CLOCK_SOURCE / PLL_DIV * PLL_MUL
* with
* 1 <= CLOCK_PLL_DIV <= 2
* 2 <= CLOCK_PLL_MUL <= 17 */
#define CLOCK_PLL_DIV (1)
#define CLOCK_PLL_MUL (9)
/* AHB and APBx bus clock configuration, keep in mind the following constraints:
* ABP1 <= 36MHz
*/ */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* give the target core clock (HCLK) frequency [in Hz],
#define CLOCK_AHB (CLOCK_CORECLOCK / 1) * maximum: 72MHz */
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 #define CLOCK_CORECLOCK (72000000U)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) /* 0: no external high speed crystal available
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 * else: actual crystal frequency [in Hz] */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) #define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (9)
/** @} */ /** @} */
/** /**

33
boards/nucleo-f302/include/periph_conf.h
View File

@ -30,23 +30,32 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
#define CLOCK_HSE (8000000U) /* external oscillator */ /* give the target core clock (HCLK) frequency [in Hz],
#define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */ * maximum: 72MHz */
#define CLOCK_CORECLOCK (72000000U)
/* the actual PLL values are automatically generated */ /* 0: no external high speed crystal available
#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE) * else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1) #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (9)
/** @} */ /** @} */
/** /**

33
boards/nucleo-f303/include/periph_conf.h
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@ -28,23 +28,32 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
#define CLOCK_HSE (8000000U) /* external oscillator */ /* give the target core clock (HCLK) frequency [in Hz],
#define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */ * maximum: 72MHz */
#define CLOCK_CORECLOCK (72000000U)
/* the actual PLL values are automatically generated */ /* 0: no external high speed crystal available
#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE) * else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1) #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (9)
/** @} */ /** @} */
/** /**

35
boards/nucleo-f334/include/periph_conf.h
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@ -27,23 +27,32 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
**/ */
#define CLOCK_HSE (8000000U) /* external oscillator */ /* give the target core clock (HCLK) frequency [in Hz],
#define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */ * maximum: 72MHz */
#define CLOCK_CORECLOCK (72000000U)
/* the actual PLL values are automatically generated */ /* 0: no external high speed crystal available
#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE) * else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1) #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (9)
/** @} */ /** @} */
/** /**

33
boards/nucleo144-f303/include/periph_conf.h
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@ -26,23 +26,32 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
#define CLOCK_HSE (8000000U) /* external oscillator */ /* give the target core clock (HCLK) frequency [in Hz],
#define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */ * maximum: 72MHz */
#define CLOCK_CORECLOCK (72000000U)
/* the actual PLL values are automatically generated */ /* 0: no external high speed crystal available
#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE) * else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1) #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (9)
/** @} */ /** @} */
/** /**

32
boards/nucleo32-f031/include/periph_conf.h
View File

@ -27,19 +27,31 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
#define CLOCK_HSI (8000000U) /* internal oscillator */ /* give the target core clock (HCLK) frequency [in Hz],
#define CLOCK_CORECLOCK (48000000U) /* desired core clock frequency */ * maximum: 48MHz */
#define CLOCK_CORECLOCK (48000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (0U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (0)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_APB1)
/* the actual PLL values are automatically generated */ /* PLL factors */
#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSI) #define CLOCK_PLL_PREDIV (2)
#define CLOCK_PLL_MUL (12)
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/** @} */ /** @} */
/** /**

31
boards/nucleo32-f042/include/periph_conf.h
View File

@ -26,21 +26,34 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
#define CLOCK_HSI (8000000U) /* internal oscillator */ /* give the target core clock (HCLK) frequency [in Hz],
#define CLOCK_CORECLOCK (48000000U) /* desired core clock frequency */ * maximum: 48MHz */
#define CLOCK_CORECLOCK (48000000U)
/* the actual PLL values are automatically generated */ /* 0: no external high speed crystal available
#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSI) * else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (0U)
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */ /* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (0)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1) #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1) #define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) #define CLOCK_APB2 (CLOCK_APB1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (2)
#define CLOCK_PLL_MUL (12)
/** @} */ /** @} */
/** /**
* @name Timer configuration * @name Timer configuration
* @{ * @{

33
boards/nucleo32-f303/include/periph_conf.h
View File

@ -26,23 +26,32 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
#define CLOCK_HSI (8000000U) /* external oscillator */ /* give the target core clock (HCLK) frequency [in Hz],
#define CLOCK_CORECLOCK (64000000U) /* desired core clock frequency */ * maximum: 72MHz */
#define CLOCK_CORECLOCK (64000000U)
#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSI) /* 0: no external high speed crystal available
/* the actual PLL values are automatically generated */ * else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (0U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (0)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1) #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (2)
#define CLOCK_PLL_MUL (16)
/** @} */ /** @} */
/** /**

32
boards/stm32f0discovery/include/periph_conf.h
View File

@ -26,19 +26,31 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
#define CLOCK_HSE (8000000U) /* external oscillator */ /* give the target core clock (HCLK) frequency [in Hz],
#define CLOCK_CORECLOCK (48000000U) /* desired core clock frequency */ * maximum: 48MHz */
#define CLOCK_CORECLOCK (48000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (0)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_APB1)
/* the actual PLL values are automatically generated */ /* PLL factors */
#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE) #define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (6)
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
/** @} */ /** @} */
/** /**

33
boards/stm32f3discovery/include/periph_conf.h
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@ -26,23 +26,32 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
#define CLOCK_HSE (8000000U) /* external oscillator */ /* give the target core clock (HCLK) frequency [in Hz],
#define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */ * maximum: 72MHz */
#define CLOCK_CORECLOCK (72000000U)
/* the actual PLL values are automatically generated */ /* 0: no external high speed crystal available
#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE) * else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_2
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1) #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (9)
/** @} */ /** @} */
/** /**

49
cpu/stm32_common/dist/clk_conf/clk_conf.c vendored
View File

@ -300,6 +300,9 @@ int main(int argc, char **argv)
bool use_alt_48MHz = false; bool use_alt_48MHz = false;
unsigned clock_48MHz = cfg->need_48MHz ? 48000000U : 0; unsigned clock_48MHz = cfg->need_48MHz ? 48000000U : 0;
if ((cfg->hsi_prediv) && (pll_src == HSI)) {
m = cfg->hsi_prediv;
}
/* main PLL */ /* main PLL */
/* try to match coreclock with P output and 48MHz for Q output (USB) */ /* try to match coreclock with P output and 48MHz for Q output (USB) */
@ -402,9 +405,11 @@ int main(int argc, char **argv)
break; break;
} }
} }
for (apb2_pre = 1; apb2_pre <= 16; apb2_pre <<= 1) { if (cfg->family == STM32F0) {
if (coreclock / apb2_pre <= cfg->max_apb2) { for (apb2_pre = 1; apb2_pre <= 16; apb2_pre <<= 1) {
break; if (coreclock / apb2_pre <= cfg->max_apb2) {
break;
}
} }
} }
@ -432,18 +437,32 @@ int main(int argc, char **argv)
printf("/* peripheral clock setup */\n"); printf("/* peripheral clock setup */\n");
printf("#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1\n" printf("#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1\n"
"#define CLOCK_AHB (CLOCK_CORECLOCK / 1)\n"); "#define CLOCK_AHB (CLOCK_CORECLOCK / 1)\n");
printf("#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV%u /* max %uMHz */\n" if (cfg->family == STM32F0) {
"#define CLOCK_APB1 (CLOCK_CORECLOCK / %u)\n", printf("#define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV%u /* max %uMHz */\n"
apb1_pre, cfg->max_apb1 / 1000000U, apb1_pre); "#define CLOCK_APB1 (CLOCK_CORECLOCK / %u)\n",
printf("#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV%u /* max %uMHz */\n" apb1_pre, cfg->max_apb1 / 1000000U, apb1_pre);
"#define CLOCK_APB2 (CLOCK_CORECLOCK / %u)\n", printf("#define CLOCK_APB2 (CLOCK_APB1)\n");
apb2_pre, cfg->max_apb2 / 1000000U, apb2_pre); }
printf("\n/* Main PLL factors */\n"); else {
printf("#define CLOCK_PLL_M (%u)\n", m); printf("#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV%u /* max %uMHz */\n"
printf("#define CLOCK_PLL_N (%u)\n", n); "#define CLOCK_APB1 (CLOCK_CORECLOCK / %u)\n",
printf("#define CLOCK_PLL_P (%u)\n", p); apb1_pre, cfg->max_apb1 / 1000000U, apb1_pre);
printf("#define CLOCK_PLL_Q (%u)\n", q); printf("#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV%u /* max %uMHz */\n"
"#define CLOCK_APB2 (CLOCK_CORECLOCK / %u)\n",
apb2_pre, cfg->max_apb2 / 1000000U, apb2_pre);
}
if (cfg->family == STM32F0 || cfg->family == STM32F1 || cfg->family == STM32F3) {
printf("\n/* PLL factors */\n");
printf("#define CLOCK_PLL_PREDIV (%u)\n", m);
printf("#define CLOCK_PLL_MUL (%u)\n", n);
}
else {
printf("\n/* Main PLL factors */\n");
printf("#define CLOCK_PLL_M (%u)\n", m);
printf("#define CLOCK_PLL_N (%u)\n", n);
printf("#define CLOCK_PLL_P (%u)\n", p);
printf("#define CLOCK_PLL_Q (%u)\n", q);
}
if (pll_i2s_p_out || pll_i2s_q_out) { if (pll_i2s_p_out || pll_i2s_q_out) {
printf("\n/* PLL I2S configuration */\n"); printf("\n/* PLL I2S configuration */\n");

175
cpu/stm32_common/dist/clk_conf/clk_conf.h vendored
View File

@ -44,11 +44,41 @@ enum fam {
* @{ * @{
*/ */
enum { enum {
STM32F030,
STM32F070,
STM32F031,
STM32F051,
STM32F071,
STM32F091,
STM32F042,
STM32F072,
STM32F038,
STM32F048,
STM32F058,
STM32F078,
STM32F098,
STM32F100,
STM32F101,
STM32F102,
STM32F103,
STM32F205, STM32F205,
STM32F207, STM32F207,
STM32F215, STM32F215,
STM32F217, STM32F217,
STM32F301,
STM32F302,
STM32F303,
STM32F334,
STM32F373,
STM32F318,
STM32F328,
STM32F358,
STM32F378,
STM32F398,
STM32F401, STM32F401,
STM32F405, STM32F405,
STM32F407, STM32F407,
@ -148,6 +178,8 @@ typedef struct {
bool has_pll_sai_m; /**< PLL SAI has a M factor */ bool has_pll_sai_m; /**< PLL SAI has a M factor */
bool has_pll_i2s_alt_input; /**< PLL I2S has an external input available */ bool has_pll_i2s_alt_input; /**< PLL I2S has an external input available */
unsigned hsi_prediv; /**< Value if HSI has a fixed prediv, 0 otherwise */
int has_alt_48MHz; /**< 48MHz can be generated by an alternate source */ int has_alt_48MHz; /**< 48MHz can be generated by an alternate source */
bool need_48MHz; /**< 48MHz is needed */ bool need_48MHz; /**< 48MHz is needed */
} clk_cfg_t; } clk_cfg_t;
@ -165,14 +197,45 @@ typedef struct {
/** @} */ /** @} */
#define STM32F(x) [STM32F##x] = x #define STM32F(x) [STM32F##x] = x
#define STM32F0(x) [STM32F0##x] = x
/** List of supported models */ /** List of supported models */
static const unsigned stm32_model[] = { static const unsigned stm32_model[] = {
STM32F0(30),
STM32F0(70),
STM32F0(31),
STM32F0(51),
STM32F0(71),
STM32F0(91),
STM32F0(42),
STM32F0(72),
STM32F0(38),
STM32F0(48),
STM32F0(58),
STM32F0(78),
STM32F0(98),
STM32F(100),
STM32F(101),
STM32F(102),
STM32F(103),
STM32F(205), STM32F(205),
STM32F(207), STM32F(207),
STM32F(215), STM32F(215),
STM32F(217), STM32F(217),
STM32F(301),
STM32F(302),
STM32F(303),
STM32F(334),
STM32F(373),
STM32F(318),
STM32F(328),
STM32F(358),
STM32F(378),
STM32F(398),
STM32F(401), STM32F(401),
STM32F(405), STM32F(405),
STM32F(407), STM32F(407),
@ -245,6 +308,90 @@ static const unsigned stm32_model[] = {
* @brief Clock config for supported cpu * @brief Clock config for supported cpu
*/ */
static const clk_cfg_t stm32_clk_cfg[] = { static const clk_cfg_t stm32_clk_cfg[] = {
[STM32F030 ... STM32F098] = {
.family = STM32F0,
.max_coreclock = 48000000U,
.max_apb1 = 48000000U,
.max_apb2 = 0,
.hsi = 8000000U,
.pll = {
.min_vco_input = 1000000U,
.max_vco_input = 24000000U,
.min_vco_output = 16000000U,
.max_vco_output = 48000000U,
.min_m = 1,
.max_m = 16,
.inc_m = 1,
.min_n = 2,
.max_n = 16,
.inc_n = 1,
.min_p = 1,
.max_p = 1,
.inc_p = 1,
},
.has_pll_i2s = false,
.has_pll_sai = false,
.has_pll_i2s_alt_input = false,
.has_alt_48MHz = 0,
.hsi_prediv = 2,
.need_48MHz = false,
},
[STM32F100] = {
.family = STM32F1,
.max_coreclock = 24000000U,
.max_apb1 = 24000000U,
.max_apb2 = 24000000U,
.hsi = 8000000U,
.pll = {
.min_vco_input = 1000000U,
.max_vco_input = 24000000U,
.min_vco_output = 16000000U,
.max_vco_output = 24000000U,
.min_m = 1,
.max_m = 16,
.inc_m = 1,
.min_n = 2,
.max_n = 16,
.inc_n = 1,
.min_p = 1,
.max_p = 1,
.inc_p = 1,
},
.has_pll_i2s = false,
.has_pll_sai = false,
.has_pll_i2s_alt_input = false,
.has_alt_48MHz = 0,
.hsi_prediv = 2,
.need_48MHz = false,
},
[STM32F101 ... STM32F103] = {
.family = STM32F1,
.max_coreclock = 72000000U,
.max_apb1 = 36000000U,
.max_apb2 = 72000000U,
.hsi = 8000000U,
.pll = {
.min_vco_input = 1000000U,
.max_vco_input = 25000000U,
.min_vco_output = 1000000U,
.max_vco_output = 72000000U,
.min_m = 1,
.max_m = 16,
.inc_m = 1,
.min_n = 2,
.max_n = 16,
.inc_n = 1,
.min_p = 1,
.max_p = 1,
.inc_p = 1,
},
.has_pll_i2s = false,
.has_pll_sai = false,
.has_pll_i2s_alt_input = false,
.has_alt_48MHz = 0,
.hsi_prediv = 2,
.need_48MHz = false,
},
[STM32F205 ... STM32F217] = { [STM32F205 ... STM32F217] = {
.family = STM32F2, .family = STM32F2,
.max_coreclock = 120000000U, .max_coreclock = 120000000U,
@ -258,6 +405,34 @@ static const clk_cfg_t stm32_clk_cfg[] = {
.has_alt_48MHz = 0, .has_alt_48MHz = 0,
.need_48MHz = true, .need_48MHz = true,
}, },
[STM32F301 ... STM32F398] = {
.family = STM32F3,
.max_coreclock = 72000000U,
.max_apb1 = 36000000U,
.max_apb2 = 72000000U,
.hsi = 8000000U,
.pll = {
.min_vco_input = 1000000U,
.max_vco_input = 25000000U,
.min_vco_output = 1000000U,
.max_vco_output = 72000000U,
.min_m = 1,
.max_m = 16,
.inc_m = 1,
.min_n = 2,
.max_n = 16,
.inc_n = 1,
.min_p = 1,
.max_p = 1,
.inc_p = 1,
},
.has_pll_i2s = false,
.has_pll_sai = false,
.has_pll_i2s_alt_input = false,
.has_alt_48MHz = 0,
.hsi_prediv = 2,
.need_48MHz = false,
},
[STM32F401] = { [STM32F401] = {
.family = STM32F4, .family = STM32F4,
.max_coreclock = 84000000U, .max_coreclock = 84000000U,

20
cpu/stm32_common/doc.txt
View File

@ -8,10 +8,10 @@
* @ref cpu_stm32f1, @ref cpu_stm32f2, @ref cpu_stm32f3, @ref cpu_stm32f4, * @ref cpu_stm32f1, @ref cpu_stm32f2, @ref cpu_stm32f3, @ref cpu_stm32f4,
* @ref cpu_stm32l4, @ref cpu_stm32f7. * @ref cpu_stm32l4, @ref cpu_stm32f7.
* *
* STM32F[2|4|7] Clock configuration * STM32Fx Clock configuration
* ================================= * =================================
* *
* stm32f2, stm32f4 and stm32f7 cpus share clock configuration code and macro. * stm32fx cpus share clock configuration code and macro.
* It can be configured as described here. * It can be configured as described here.
* *
* The following macro must be defined in the board's periph_conf.h: * The following macro must be defined in the board's periph_conf.h:
@ -22,16 +22,26 @@
* - CLOCK_AHB_DIV, CLOCK_AHB: AHB prescaler in register value and AHB frequecny in Hz * - CLOCK_AHB_DIV, CLOCK_AHB: AHB prescaler in register value and AHB frequecny in Hz
* - CLOCK_APB1_DIV, CLOCK_APB1: APB1 prescaler in register value and APB1 frequecny in Hz * - CLOCK_APB1_DIV, CLOCK_APB1: APB1 prescaler in register value and APB1 frequecny in Hz
* - CLOCK_APB2_DIV, CLOCK_APB2: APB2 prescaler in register value and APB2 frequecny in Hz * - CLOCK_APB2_DIV, CLOCK_APB2: APB2 prescaler in register value and APB2 frequecny in Hz
* - CLOCK_PLL_M, CLOCK_PLL_N, CLOCK_PLL_P, CLOCK_PLL_Q: Main PLL factors * (CLOCK_APB2_DIV is not needed for stm32f0)
*
* The following macro must be defined for stm32f[2|4|7]:
* - CLOCK_PLL_M, CLOCK_PLL_N, CLOCK_PLL_P, CLOCK_PLL_Q, (CLOCK_PLL_R, optional):
* Main PLL factors
*
* The following macro must be defined for stm32f[0|1|3]:
* - PLL_MUL, PLL_PREDIV: PLL factors. These values are used as is. A PREDIV of 2
* can be assumed when HSI is selected as PLL input. Some model support any value
* as PREDIV even with HSI though. The `clk_conf` tool will assume PREDIV must be
* to with HSI and will set it accordingly.
* *
* The following macro are optional and can be defined depending on board config * The following macro are optional and can be defined depending on board config
* and application needs: * and application needs:
* - CLOCK_ENABLE_PLL_I2S: if a second PLL (PLL I2S) is available on the cpu, it * - CLOCK_ENABLE_PLL_I2S: if a second PLL (PLL I2S) is available on the cpu, it
* can be activated with this macro, then CLOCK_PLL_I2S_M, CLOCK_PLL_I2S_N, * can be activated with this macro, then CLOCK_PLL_I2S_M, CLOCK_PLL_I2S_N,
* CLOCK_PLL_I2S_P and CLOCK_PLL_I2S_Q need to be defined * CLOCK_PLL_I2S_P and CLOCK_PLL_I2S_Q need to be defined, CLOCK_PLL_I2S_R is optional.
* - CLOCK_ENABLE_PLL_SAI: if a second PLL (PLL SAI) is available on the cpu, it * - CLOCK_ENABLE_PLL_SAI: if a second PLL (PLL SAI) is available on the cpu, it
* can be activated with this macro, then CLOCK_PLL_SAI_M, CLOCK_PLL_SAI_N, * can be activated with this macro, then CLOCK_PLL_SAI_M, CLOCK_PLL_SAI_N,
* CLOCK_PLL_SAI_P and CLOCK_PLL_SAI_Q need to be defined * CLOCK_PLL_SAI_P and CLOCK_PLL_SAI_Q need to be defined, CLOCK_PLL_SAI_R is optional.
* - CLOCK_USE_ALT_48MHZ: if the 48MHz clock should be generated by the alternate * - CLOCK_USE_ALT_48MHZ: if the 48MHz clock should be generated by the alternate
* source (PLL I2S or PLL SAI, depending on cpu) * source (PLL I2S or PLL SAI, depending on cpu)
* *

55
cpu/stm32_common/stmclk.c
View File

@ -19,7 +19,8 @@
* @} * @}
*/ */
#if defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7) #if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) \
|| defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7)
#include "cpu.h" #include "cpu.h"
#include "stmclk.h" #include "stmclk.h"
@ -40,6 +41,7 @@
* @name PLL configuration * @name PLL configuration
* @{ * @{
*/ */
#if defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7)
/* figure out which input to use */ /* figure out which input to use */
#if (CLOCK_HSE) #if (CLOCK_HSE)
#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSE #define PLL_SRC RCC_PLLCFGR_PLLSRC_HSE
@ -89,19 +91,54 @@
#define PLL_M (CLOCK_PLL_M << RCC_PLLCFGR_PLLM_Pos) #define PLL_M (CLOCK_PLL_M << RCC_PLLCFGR_PLLM_Pos)
#define PLL_N (CLOCK_PLL_N << RCC_PLLCFGR_PLLN_Pos) #define PLL_N (CLOCK_PLL_N << RCC_PLLCFGR_PLLN_Pos)
#define PLL_Q (CLOCK_PLL_Q << RCC_PLLCFGR_PLLQ_Pos) #define PLL_Q (CLOCK_PLL_Q << RCC_PLLCFGR_PLLQ_Pos)
#elif defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3)
#if (CLOCK_HSE)
#define PLL_SRC (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1)
#else
#define PLL_SRC (RCC_CFGR_PLLSRC_HSI_DIV2)
#endif
#define PLL_MUL ((CLOCK_PLL_MUL - 2) << 18)
#define PLL_PREDIV (CLOCK_PLL_PREDIV - 1)
#if defined(CPU_FAM_STM32F0)
#define CLOCK_APB2_DIV (0)
#endif
#elif defined(CPU_FAM_STM32F1)
#if CLOCK_HSE
#define PLL_SRC (RCC_CFGR_PLLSRC) /* HSE */
#else
#define PLL_SRC (0) /* HSI / 2 */
#endif
#define PLL_MUL ((CLOCK_PLL_MUL - 2) << 18)
#define PLL_PREDIV (CLOCK_PLL_PREDIV - 1)
#define RCC_CR_HSITRIM_4 (1 << 7)
#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMULL
#endif
/** @} */ /** @} */
/** /**
* @name Deduct the needed flash wait states from the core clock frequency * @name Deduct the needed flash wait states from the core clock frequency
* @{ * @{
*/ */
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || defined(STM32F3)
#define FLASH_WAITSTATES ((CLOCK_CORECLOCK - 1) / 24000000U)
#else
#define FLASH_WAITSTATES (CLOCK_CORECLOCK / 30000000U) #define FLASH_WAITSTATES (CLOCK_CORECLOCK / 30000000U)
#endif
/* we enable I+D cashes, pre-fetch, and we set the actual number of /* we enable I+D cashes, pre-fetch, and we set the actual number of
* needed flash wait states */ * needed flash wait states */
#if defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) #if defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4)
#define FLASH_ACR_CONFIG (FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN | FLASH_WAITSTATES) #define FLASH_ACR_CONFIG (FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN | FLASH_WAITSTATES)
#elif defined(CPU_FAM_STM32F7) #elif defined(CPU_FAM_STM32F7)
#define FLASH_ACR_CONFIG (FLASH_ACR_ARTEN | FLASH_ACR_PRFTEN | FLASH_WAITSTATES) #define FLASH_ACR_CONFIG (FLASH_ACR_ARTEN | FLASH_ACR_PRFTEN | FLASH_WAITSTATES)
#elif defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F3)
#define FLASH_ACR_CONFIG (FLASH_ACR_PRFTBE | FLASH_WAITSTATES)
#endif #endif
/** @} */ /** @} */
@ -150,7 +187,19 @@ void stmclk_init_sysclk(void)
RCC->DCKCFGR2 |= RCC_DCKCFGR2_CK48MSEL; RCC->DCKCFGR2 |= RCC_DCKCFGR2_CK48MSEL;
#endif #endif
/* now we can safely configure and start the PLL */ /* now we can safely configure and start the PLL */
#if defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7)
RCC->PLLCFGR = (PLL_SRC | PLL_M | PLL_N | PLL_P | PLL_Q); RCC->PLLCFGR = (PLL_SRC | PLL_M | PLL_N | PLL_P | PLL_Q);
#elif defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F3)
/* reset PLL configuration bits */
RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL);
/* set PLL configuration */
RCC->CFGR |= PLL_SRC | PLL_MUL;
#if CLOCK_PLL_PREDIV == 2
RCC->CFGR |= RCC_CFGR_PLLXTPRE; /* PREDIV == 2 */
#elif CLOCK_PLL_PREDIV > 2
RCC->CFGR2 = PLL_PREDIV; /* PREDIV > 2 */
#endif
#endif
RCC->CR |= (RCC_CR_PLLON); RCC->CR |= (RCC_CR_PLLON);
while (!(RCC->CR & RCC_CR_PLLRDY)) {} while (!(RCC->CR & RCC_CR_PLLRDY)) {}
@ -176,4 +225,6 @@ void stmclk_init_sysclk(void)
} }
#else #else
typedef int dont_be_pedantic; typedef int dont_be_pedantic;
#endif /* defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7) */ #endif /* defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) ||
* defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F3) ||
* defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7) */

104
cpu/stm32f0/cpu.c
View File

@ -18,34 +18,9 @@
*/ */
#include "cpu.h" #include "cpu.h"
#include "periph_conf.h" #include "stmclk.h"
#include "periph/init.h" #include "periph/init.h"
/* Check the source to be used for the PLL */
#if defined(CLOCK_HSI) && defined(CLOCK_HSE)
#error "Only provide one of two CLOCK_HSI/CLOCK_HSE"
#elif CLOCK_HSI
#define CLOCK_CR_SOURCE RCC_CR_HSION
#define CLOCK_CR_SOURCE_RDY RCC_CR_HSIRDY
#define CLOCK_PLL_SOURCE (RCC_CFGR_PLLSRC_HSI_DIV2)
#define CLOCK_PLL_MUL_MUL 2
#define CLOCK_DISABLE_HSI 0
#if (RCC_PLL_MUL * RCC_PLL_MUL_MUL) > 6
#error PLL with HSI as clock source cant extend 6 times multiplier
#endif
#elif CLOCK_HSE
#define CLOCK_CR_SOURCE RCC_CR_HSEON
#define CLOCK_CR_SOURCE_RDY RCC_CR_HSERDY
#define CLOCK_PLL_SOURCE (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1)
#define CLOCK_PLL_MUL_MUL 1
#define CLOCK_DISABLE_HSI 1
#else
#error "Please provide CLOCK_HSI or CLOCK_HSE in boards/NAME/includes/perhip_cpu.h"
#endif
static void clock_init(void);
/** /**
* @brief Initialize the CPU, set IRQ priorities * @brief Initialize the CPU, set IRQ priorities
*/ */
@ -54,82 +29,7 @@ void cpu_init(void)
/* initialize the Cortex-M core */ /* initialize the Cortex-M core */
cortexm_init(); cortexm_init();
/* initialize the clock system */ /* initialize the clock system */
clock_init(); stmclk_init_sysclk();
/* trigger static peripheral initialization */ /* trigger static peripheral initialization */
periph_init(); periph_init();
} }
/**
* @brief Configure the controllers clock system
*
* The clock initialization make the following assumptions:
* - the external HSE clock from an external oscillator is used as base clock
* - the internal PLL circuit is used for clock refinement
*
* Use the following formulas to calculate the needed values:
*
* SYSCLK = ((HSE_VALUE / CLOCK_PLL_M) * CLOCK_PLL_N) / CLOCK_PLL_P
* USB, SDIO and RNG Clock = ((HSE_VALUE / CLOCK_PLL_M) * CLOCK_PLL_N) / CLOCK_PLL_Q
*
* The actual used values are specified in the board's `periph_conf.h` file.
*
* NOTE: currently there is not timeout for initialization of PLL and other locks
* -> when wrong values are chosen, the initialization could stall
*/
static void clock_init(void)
{
/* reset clock configuration register */
RCC->CFGR = 0;
RCC->CFGR2 = 0;
/* disable HSE, CSS and PLL */
RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON | RCC_CR_PLLON);
/* disable all clock interrupts */
RCC->CIR = 0;
/* enable the high speed clock source */
RCC->CR |= CLOCK_CR_SOURCE;
/* wait for the high speed clock to be ready */
while (!(RCC->CR & CLOCK_CR_SOURCE_RDY)) {}
/* setup the peripheral bus prescalers */
/* set HCLK = SYSCLK, so no clock division here */
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
/* set PCLK = HCLK, so its not divided */
RCC->CFGR |= RCC_CFGR_PPRE_DIV1;
/* configure the PLL */
/* reset PLL configuration bits */
RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL);
/* set PLL configuration */
RCC->CFGR |= CLOCK_PLL_SOURCE | ((((CLOCK_PLL_MUL * CLOCK_PLL_MUL_MUL) - 2) & 0xf) << 18);
/* enable PLL again */
RCC->CR |= RCC_CR_PLLON;
/* wait until PLL is stable */
while(!(RCC->CR & RCC_CR_PLLRDY)) {}
/* configure flash latency */
/* enable pre-fetch buffer and set flash latency to 1 cycle*/
FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
/* configure the sysclock and the peripheral clocks */
/* set sysclock to be driven by the PLL clock */
RCC->CFGR &= ~RCC_CFGR_SW;
RCC->CFGR |= RCC_CFGR_SW_PLL;
/* wait for sysclock to be stable */
while (!(RCC->CFGR & RCC_CFGR_SWS_PLL)) {}
#if CLOCK_DISABLE_HSI
/* disable the HSI if we use the HSE */
RCC->CR &= ~(RCC_CR_HSION);
while (RCC->CR & RCC_CR_HSIRDY) {}
#endif
}

156
cpu/stm32f1/stmclk.c
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@ -1,156 +0,0 @@
/*
* Copyright (C) 2017 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_stm32f1
* @{
*
* @file
* @brief Implementation of STM32F1 clock configuration
*
* @author Stefan Pfeiffer <stefan.pfeiffer@fu-berlin.de>
* @author Alaeddine Weslati <alaeddine.weslati@inria.fr>
* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Nick van IJzendoorn <nijzendoorn@engineering-spirit.nl>
* @author Víctor Ariño <victor.arino@zii.aero>
*
* @}
*/
#include "irq.h"
#include "cpu.h"
#include "stmclk.h"
#include "periph_conf.h"
/* make sure we have all needed information about the clock configuration */
#ifndef CLOCK_HSE
#error "Please provide CLOCK_HSE in your board's perhip_conf.h"
#endif
#ifndef CLOCK_LSE
#error "Please provide CLOCK_LSE in your board's periph_conf.h"
#endif
#ifndef CLOCK_CORECLOCK
#error "Please provide CLOCK_CORECLOCK in your board's periph_conf.h"
#endif
#if !defined(CLOCK_PLL_MUL) || !defined(CLOCK_PLL_DIV)
#error "Please provide a valid PLL configuration in your board's periph_conf.h"
#endif
#if !defined(CLOCK_AHB_DIV) || !defined(CLOCK_AHB) || \
!defined(CLOCK_APB1_DIV) || !defined(CLOCK_APB1) || \
!defined(CLOCK_APB2_DIV) || !defined(CLOCK_APB2)
#error "Please provide a AHB and APBx configuration in your board configuration"
#endif
/* make sure the selected system clock is valid */
#if (CLOCK_CORECLOCK > 72000000)
#error "clock config: the selected system clock exceeds 72MHz"
#endif
/* figure out which base block to use */
#if CLOCK_HSE
#if (CLOCK_HSE < 4000000) || (CLOCK_HSE > 16000000)
#error "clock config: HSE value is out of valid range"
#endif
#define BASECLK (CLOCK_HSE)
#else
#define BASECLK (8000000) /* HSI is alway 8MHz */
#endif
/* if PLL is configured, verify its parameters */
#if (CLOCK_PLL_DIV && CLOCK_PLL_MUL)
#define USEPLL
/* check clock config */
#if (CLOCK_CORECLOCK != ((BASECLK / CLOCK_PLL_DIV) * CLOCK_PLL_MUL))
#error "clock config: PLL configuration does not yield expected system clock"
#endif
/* make sure PLL_MUL is in range */
#if (CLOCK_PLL_MUL < 2) || (CLOCK_PLL_MUL > 17)
#error "clock config: CLOCK_PLL_MUL is out of range"
#endif
/* make sure PLL_DIV is 2 when using HSI as input */
#if (!CLOCK_HSE) && (CLOCK_PLL_DIV != 2)
#error "clock config: CLOCK_PLL_DIV must be 2 when using HSI oscillator"
#endif
/* and produce the actual PLL configuration */
#if CLOCK_HSE
#define PLLSRC (RCC_CFGR_PLLSRC)
#if (CLOCK_PLL_DIV == 2)
#define PLLDIV (RCC_CFGR_PLLXTPRE)
#else
#define PLLDIV (0)
#endif
#else
#define PLLSRC (0)
#define PLLDIV (0)
#endif
#define PLLMUL ((CLOCK_PLL_MUL - 2) << 18)
/* and join it for writing the the CFGR register */
#define PLLCFG (PLLMUL | PLLDIV | PLLSRC)
#else
#define PLLCFG (0)
#endif
/* now we need to select the system clock source configuration */
#ifdef USEPLL
#define SYSCLK_SRC RCC_CFGR_SW_PLL
#define SYSCLK_BSY RCC_CFGR_SWS_PLL
#elif CLK_HSE
#define SYSCLK_SRC RCC_CFGR_SW_HSE
#define SYSCLK_BSY RCC_CFGR_SWS_HSE
#else
#define SYSCLK_SRC RCC_CFGR_SW_HSI
#define SYSCLK_BSY RCC_CFGR_SWS_HSI
#endif
/* Configuration of flash access cycles */
#define FLASH_WAITSTATES ((CLOCK_CORECLOCK - 1) / 24000000U)
/* define some bitfields */
#define HSITRIM (1 << 7)
#define SWSHSI (0)
void stmclk_init_sysclk(void)
{
/* disable any IRQs */
unsigned is = irq_disable();
RCC->CIR = 0;
/* enable HSI and use it as system clock */
stmclk_enable_hsi();
RCC->CFGR &= ~(RCC_CFGR_SW);
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) {}
/* its safe now to program the flash wait states */
FLASH->ACR = (FLASH_ACR_PRFTBE | FLASH_WAITSTATES);
/* now we are in a defined state and can stop all other clocks */
RCC->CR = (HSITRIM | RCC_CR_HSION);
/* next we put in the desired PLL and peripheral bus configuration */
RCC->CFGR = (CLOCK_AHB_DIV | CLOCK_APB1_DIV | CLOCK_APB2_DIV | PLLCFG);
/* now we need to (re-)enable the used clocks */
#if CLOCK_HSE
RCC->CR |= RCC_CR_HSEON;
while (!(RCC->CR & RCC_CR_HSERDY)) {}
#endif
#ifdef USEPLL
RCC->CR |= RCC_CR_PLLON;
while (!(RCC->CR & RCC_CR_PLLRDY)) {}
#endif
/* leaves switching the system clock */
RCC->CFGR |= SYSCLK_SRC;
while ((RCC->CFGR & RCC_CFGR_SWS) != SYSCLK_BSY) {}
/* disable HSI (if not used) */
stmclk_disable_hsi();
/* re-enable IRQs */
irq_restore(is);
}

122
cpu/stm32f3/cpu.c
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@ -18,36 +18,9 @@
* @} * @}
*/ */
#include <stdint.h>
#include "cpu.h" #include "cpu.h"
#include "periph_conf.h"
#include "periph/init.h" #include "periph/init.h"
#include "stmclk.h"
/* Check the source to be used for the PLL */
#if defined(CLOCK_HSI) && defined(CLOCK_HSE)
#error "Only provide one of two CLOCK_HSI/CLOCK_HSE"
#elif CLOCK_HSI
#define CLOCK_CR_SOURCE RCC_CR_HSION
#define CLOCK_CR_SOURCE_RDY RCC_CR_HSIRDY
#ifdef RCC_CFGR_PLLSRC_HSI_DIV2
#define CLOCK_PLL_SOURCE (RCC_CFGR_PLLSRC_HSI_DIV2)
#define CLOCK_PLL_MUL_MULTIPLIER 2
#else
#define CLOCK_PLL_SOURCE (RCC_CFGR_PLLSRC_HSI_PREDIV)
#define CLOCK_PLL_MUL_MULTIPLIER 1
#endif
#define CLOCK_DISABLE_HSI 0
#elif CLOCK_HSE
#define CLOCK_CR_SOURCE RCC_CR_HSEON
#define CLOCK_CR_SOURCE_RDY RCC_CR_HSERDY
#define CLOCK_PLL_SOURCE (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1)
#define CLOCK_PLL_MUL_MULTIPLIER 1
#define CLOCK_DISABLE_HSI 1
#else
#error "Please provide CLOCK_HSI or CLOCK_HSE in boards/NAME/includes/perhip_cpu.h"
#endif
static void cpu_clock_init(void);
/** /**
* @brief Initialize the CPU, set IRQ priorities * @brief Initialize the CPU, set IRQ priorities
@ -57,98 +30,7 @@ void cpu_init(void)
/* initialize the Cortex-M core */ /* initialize the Cortex-M core */
cortexm_init(); cortexm_init();
/* initialize the clock system */ /* initialize the clock system */
cpu_clock_init(); stmclk_init_sysclk();
/* trigger static peripheral initialization */ /* trigger static peripheral initialization */
periph_init(); periph_init();
} }
/**
* @brief Configure the controllers clock system
*
* The clock initialization make the following assumptions:
* - the HSI and HSE selection is based on the CLOCK_HSI or CLOCK_HSE define in the periph_conf.h
* - the internal PLL circuit is used for clock refinement
*
* The actual used values are specified in the board's `periph_conf.h` file.
*
* NOTE: currently there is not timeout for initialization of PLL and other locks
* -> when wrong values are chosen, the initialization could stall
*/
static void cpu_clock_init(void)
{
/* configure the high speed clock */
/* reset clock configuration register */
RCC->CFGR = 0;
/* disable HSE, CSS and PLL */
RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON | RCC_CR_PLLON);
/* disable all clock interrupts */
RCC->CIR = 0;
/* enable the high speed clock */
RCC->CR |= CLOCK_CR_SOURCE;
/* wait for high speed clock to be ready */
while (!(RCC->CR & CLOCK_CR_SOURCE_RDY)) {}
/* setup the peripheral bus prescalers */
/* set the AHB clock divider */
RCC->CFGR &= ~RCC_CFGR_HPRE;
RCC->CFGR |= CLOCK_AHB_DIV;
/* set the APB2 (high speed) bus clock divider */
RCC->CFGR &= ~RCC_CFGR_PPRE2;
RCC->CFGR |= CLOCK_APB2_DIV;
/* set the APB1 (low speed) bus clock divider */
RCC->CFGR &= ~RCC_CFGR_PPRE1;
RCC->CFGR |= CLOCK_APB1_DIV;
/* configure the PLL */
/* reset PLL configuration */
RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL);
/* set PLL to use high speed clock with prescaler 1 as input */
RCC->CFGR |= CLOCK_PLL_SOURCE | ((((CLOCK_PLL_MUL * CLOCK_PLL_MUL_MULTIPLIER) - 2) & 0xf) << 18);
/* enable PLL again */
RCC->CR |= RCC_CR_PLLON;
/* wait until PLL is stable */
while(!(RCC->CR & RCC_CR_PLLRDY)) {}
/* configure flash latency */
/* reset flash access control register */
FLASH->ACR = 0;
/* enable pre-fetch buffer */
FLASH->ACR |= FLASH_ACR_PRFTBE;
/* set flash latency */
FLASH->ACR &= ~FLASH_ACR_LATENCY;
FLASH->ACR |= CLOCK_FLASH_LATENCY;
/* configure the sysclock and the peripheral clocks */
/* set sysclock to be driven by the PLL clock */
RCC->CFGR &= ~RCC_CFGR_SW;
RCC->CFGR |= RCC_CFGR_SW_PLL;
/* wait for sysclock to be stable */
while (!(RCC->CFGR & RCC_CFGR_SWS_PLL)) {}
#if CLOCK_DISABLE_HSI
/* disable the HSI if we use the HSE */
RCC->CR &= ~(RCC_CR_HSION);
while (RCC->CR & RCC_CR_HSIRDY) {}
/* swith I2Cx clock source to SYSCLK */
RCC->CFGR3 &= ~(RCC_CFGR3_I2CSW);
RCC->CFGR3 |= RCC_CFGR3_I2C1SW_SYSCLK;
#ifdef RCC_CFGR3_I2C2SW_SYSCLK
RCC->CFGR3 |= RCC_CFGR3_I2C2SW_SYSCLK;
#endif
#ifdef RCC_CFGR3_I2C3SW_SYSCLK
RCC->CFGR3 |= RCC_CFGR3_I2C3SW_SYSCLK;
#endif
#endif
}