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Merge pull request #11689 from benpicco/sam0_32k-gclk

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cpu/sam0_common: RTC & RTT cleanup
This commit is contained in:
Dylan Laduranty 2019-06-18 13:50:04 +02:00 committed by GitHub
commit fc9577030e
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GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 124 additions and 94 deletions
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61
cpu/sam0_common/periph/rtc.c
View File

@ -65,71 +65,34 @@ static inline void _rtc_set_enabled(bool on)
#ifdef CPU_SAMD21 #ifdef CPU_SAMD21
static void _rtc_clock_setup(void) static void _rtc_clock_setup(void)
{ {
/* RTC uses External 32,768KHz Oscillator (OSC32K isn't accurate enough p1075/1138)*/
SYSCTRL->XOSC32K.reg = SYSCTRL_XOSC32K_ONDEMAND |
SYSCTRL_XOSC32K_EN32K |
SYSCTRL_XOSC32K_XTALEN |
SYSCTRL_XOSC32K_STARTUP(6) |
SYSCTRL_XOSC32K_ENABLE;
/* Setup clock GCLK2 with OSC32K divided by 32 */ /* Setup clock GCLK2 with OSC32K divided by 32 */
GCLK->GENDIV.reg = GCLK_GENDIV_ID(2)|GCLK_GENDIV_DIV(4); GCLK->GENDIV.reg = GCLK_GENDIV_ID(2) | GCLK_GENDIV_DIV(4);
GCLK->GENCTRL.reg = (GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_XOSC32K | GCLK_GENCTRL_ID(2) | GCLK_GENCTRL_DIVSEL ); GCLK->GENCTRL.bit.DIVSEL = 1;
GCLK->CLKCTRL.reg = (uint32_t)((GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK2 | (RTC_GCLK_ID << GCLK_CLKCTRL_ID_Pos))); GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(2) | GCLK_CLKCTRL_ID_RTC;
while (GCLK->STATUS.bit.SYNCBUSY) {} while (GCLK->STATUS.bit.SYNCBUSY) {}
} }
#else #else
static void _rtc_clock_setup(void) static void _rtc_clock_setup(void)
{ {
MCLK->APBAMASK.reg |= MCLK_APBAMASK_OSC32KCTRL;
#if EXTERNAL_OSC32_SOURCE
/* RTC uses External 32,768KHz Oscillator */
OSC32KCTRL->XOSC32K.reg = OSC32KCTRL_XOSC32K_XTALEN
| OSC32KCTRL_XOSC32K_EN1K
| OSC32KCTRL_XOSC32K_RUNSTDBY
| OSC32KCTRL_XOSC32K_ENABLE;
/* Wait XOSC32K Ready */
while (OSC32KCTRL->STATUS.bit.XOSC32KRDY==0) {}
/* RTC source clock is external oscillator at 1kHz */ /* RTC source clock is external oscillator at 1kHz */
#if EXTERNAL_OSC32_SOURCE
OSC32KCTRL->XOSC32K.bit.EN1K = 1;
OSC32KCTRL->RTCCTRL.reg = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K; OSC32KCTRL->RTCCTRL.reg = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K;
#endif /* EXTERNAL_OSC32_SOURCE */
#if INTERNAL_OSC32_SOURCE
uint32_t * pCalibrationArea;
uint32_t osc32kcal;
/* Read OSC32KCAL, calibration data for OSC32 !!! */
pCalibrationArea = (uint32_t*) NVMCTRL_OTP5;
osc32kcal = ( (*pCalibrationArea) & 0x1FC0 ) >> 6;
/* RTC use Low Power Internal Oscillator at 1kHz */
OSC32KCTRL->OSC32K.reg = OSC32KCTRL_OSC32K_RUNSTDBY
| OSC32KCTRL_OSC32K_EN1K
| OSC32KCTRL_OSC32K_CALIB(osc32kcal)
| OSC32KCTRL_OSC32K_ENABLE;
/* Wait OSC32K Ready */
while (OSC32KCTRL->STATUS.bit.OSC32KRDY==0) {}
/* RTC uses internal 32,768KHz Oscillator */ /* RTC uses internal 32,768KHz Oscillator */
#elif INTERNAL_OSC32_SOURCE
OSC32KCTRL->OSC32K.bit.EN1K = 1;
OSC32KCTRL->RTCCTRL.reg = OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K; OSC32KCTRL->RTCCTRL.reg = OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K;
#endif /* INTERNAL_OSC32_SOURCE */
#if ULTRA_LOW_POWER_INTERNAL_OSC_SOURCE
/* RTC uses Ultra Low Power internal 32,768KHz Oscillator */ /* RTC uses Ultra Low Power internal 32,768KHz Oscillator */
#elif ULTRA_LOW_POWER_INTERNAL_OSC_SOURCE
OSC32KCTRL->RTCCTRL.reg = OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K; OSC32KCTRL->RTCCTRL.reg = OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K;
#endif /* ULTRA_LOW_POWER_INTERNAL_OSC_SOURCE */ #else
#error "No clock source for RTC selected. "
#endif
} }
#endif /* CPU_SAMD21 - Clock Setup */ #endif /* !CPU_SAMD21 - Clock Setup */
void rtc_init(void) void rtc_init(void)
{ {

53
cpu/sam0_common/periph/rtt.c
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@ -22,7 +22,7 @@
#include <stdint.h> #include <stdint.h>
#include "periph/rtt.h" #include "periph/rtt.h"
#include "board.h" #include "periph_conf.h"
#define ENABLE_DEBUG 0 #define ENABLE_DEBUG 0
#include "debug.h" #include "debug.h"
@ -56,48 +56,31 @@ static inline void _rtt_reset(void)
#ifdef CPU_SAMD21 #ifdef CPU_SAMD21
static void _rtt_clock_setup(void) static void _rtt_clock_setup(void)
{ {
/* RTC uses External 32,768KHz Oscillator because OSC32K isn't accurate /* Setup clock GCLK2 with OSC32K */
* enough (p1075/1138). Also keep running in standby. */ GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(2) | GCLK_CLKCTRL_ID_RTC;
SYSCTRL->XOSC32K.reg = SYSCTRL_XOSC32K_ONDEMAND |
SYSCTRL_XOSC32K_EN32K |
SYSCTRL_XOSC32K_XTALEN |
SYSCTRL_XOSC32K_STARTUP(6) |
#if RTT_RUNSTDBY
SYSCTRL_XOSC32K_RUNSTDBY |
#endif
SYSCTRL_XOSC32K_ENABLE;
/* Setup clock GCLK2 with divider 1 */
GCLK->GENDIV.reg = GCLK_GENDIV_ID(2) | GCLK_GENDIV_DIV(1);
while (GCLK->STATUS.bit.SYNCBUSY) {}
/* Enable GCLK2 with XOSC32K as source. Use divider without modification
* and keep running in standby. */
GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(2) |
GCLK_GENCTRL_GENEN |
#if RTT_RUNSTDBY
GCLK_GENCTRL_RUNSTDBY |
#endif
GCLK_GENCTRL_SRC_XOSC32K;
while (GCLK->STATUS.bit.SYNCBUSY) {}
/* Connect GCLK2 to RTC */
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_GEN_GCLK2 |
GCLK_CLKCTRL_CLKEN |
GCLK_CLKCTRL_ID(RTC_GCLK_ID);
while (GCLK->STATUS.bit.SYNCBUSY) {} while (GCLK->STATUS.bit.SYNCBUSY) {}
} }
/* !CPU_SAMD21 */
#else #else
static void _rtt_clock_setup(void) static void _rtt_clock_setup(void)
{ {
/* Turn on power manager for RTC */ /* RTC source clock is external oscillator at 32kHz */
MCLK->APBAMASK.reg |= MCLK_APBAMASK_OSC32KCTRL; #if EXTERNAL_OSC32_SOURCE
OSC32KCTRL->XOSC32K.bit.EN32K = 1;
OSC32KCTRL->RTCCTRL.reg = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K;
/* set clock source */ /* RTC uses internal 32,768KHz Oscillator */
#elif INTERNAL_OSC32_SOURCE
OSC32KCTRL->RTCCTRL.reg = OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K;
/* RTC uses Ultra Low Power internal 32,768KHz Oscillator */
#elif ULTRA_LOW_POWER_INTERNAL_OSC_SOURCE
OSC32KCTRL->RTCCTRL.reg = OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K; OSC32KCTRL->RTCCTRL.reg = OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K;
}
#else
#error "No clock source for RTT selected. "
#endif #endif
}
#endif /* !CPU_SAMD21 - Clock Setup */
void rtt_init(void) void rtt_init(void)
{ {

16
cpu/samd21/cpu.c
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@ -187,14 +187,20 @@ static void clk_init(void)
/* make sure we synchronize clock generator 0 before we go on */ /* make sure we synchronize clock generator 0 before we go on */
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {} while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
#if GEN2_ULP32K
/* Setup Clock generator 2 with divider 1 (32.768kHz) */ /* Setup Clock generator 2 with divider 1 (32.768kHz) */
GCLK->GENDIV.reg = (GCLK_GENDIV_ID(2) | GCLK_GENDIV_DIV(0)); GCLK->GENDIV.reg = (GCLK_GENDIV_ID(2) | GCLK_GENDIV_DIV(0));
GCLK->GENCTRL.reg = (GCLK_GENCTRL_ID(2) | GCLK_GENCTRL_GENEN | GCLK->GENCTRL.reg = (GCLK_GENCTRL_ID(2) | GCLK_GENCTRL_GENEN
GCLK_GENCTRL_RUNSTDBY | | GCLK_GENCTRL_RUNSTDBY
GCLK_GENCTRL_SRC_OSCULP32K); #if GEN2_ULP32K
| GCLK_GENCTRL_SRC_OSCULP32K);
#else
| GCLK_GENCTRL_SRC_XOSC32K);
while (GCLK->STATUS.bit.SYNCBUSY) {} SYSCTRL->XOSC32K.reg = SYSCTRL_XOSC32K_ONDEMAND
| SYSCTRL_XOSC32K_EN32K
| SYSCTRL_XOSC32K_XTALEN
| SYSCTRL_XOSC32K_STARTUP(6)
| SYSCTRL_XOSC32K_ENABLE;
#endif #endif
/* redirect all peripherals to a disabled clock generator (7) by default */ /* redirect all peripherals to a disabled clock generator (7) by default */

42
cpu/saml1x/cpu.c
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@ -20,6 +20,7 @@
#include "cpu.h" #include "cpu.h"
#include "periph/init.h" #include "periph/init.h"
#include "periph_conf.h"
#include "board.h" #include "board.h"
#ifdef CPU_FAM_SAML11 #ifdef CPU_FAM_SAML11
@ -34,6 +35,41 @@ static void _gclk_setup(int gclk, uint32_t reg)
while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(gclk)) {} while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(gclk)) {}
} }
static void _osc32k_setup(void)
{
#if INTERNAL_OSC32_SOURCE
uint32_t * pCalibrationArea;
uint32_t osc32kcal;
/* Read OSC32KCAL, calibration data for OSC32 !!! */
pCalibrationArea = (uint32_t*) NVMCTRL_OTP5;
osc32kcal = ( (*pCalibrationArea) & 0x1FC0 ) >> 6;
/* RTC use Low Power Internal Oscillator at 32kHz */
OSC32KCTRL->OSC32K.reg = OSC32KCTRL_OSC32K_RUNSTDBY
| OSC32KCTRL_OSC32K_EN32K
| OSC32KCTRL_OSC32K_CALIB(osc32kcal)
| OSC32KCTRL_OSC32K_ENABLE;
/* Wait OSC32K Ready */
while (!OSC32KCTRL->STATUS.bit.OSC32KRDY) {}
#endif /* INTERNAL_OSC32_SOURCE */
}
static void _xosc32k_setup(void)
{
#if EXTERNAL_OSC32_SOURCE
/* RTC uses External 32,768KHz Oscillator */
OSC32KCTRL->XOSC32K.reg = OSC32KCTRL_XOSC32K_XTALEN
| OSC32KCTRL_XOSC32K_RUNSTDBY
| OSC32KCTRL_XOSC32K_EN32K
| OSC32KCTRL_XOSC32K_ENABLE;
/* Wait XOSC32K Ready */
while (!OSC32KCTRL->STATUS.bit.XOSC32KRDY) {}
#endif
}
/** /**
* @brief Initialize the CPU, set IRQ priorities, clocks * @brief Initialize the CPU, set IRQ priorities, clocks
*/ */
@ -45,6 +81,7 @@ void cpu_init(void)
/* turn on only needed APB peripherals */ /* turn on only needed APB peripherals */
MCLK->APBAMASK.reg = MCLK_APBAMASK_MCLK MCLK->APBAMASK.reg = MCLK_APBAMASK_MCLK
| MCLK_APBAMASK_OSCCTRL | MCLK_APBAMASK_OSCCTRL
| MCLK_APBAMASK_OSC32KCTRL
| MCLK_APBAMASK_GCLK | MCLK_APBAMASK_GCLK
| MCLK_APBAMASK_PM | MCLK_APBAMASK_PM
#ifdef MODULE_PERIPH_GPIO_IRQ #ifdef MODULE_PERIPH_GPIO_IRQ
@ -61,7 +98,7 @@ void cpu_init(void)
while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) {} while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) {}
PM->PLCFG.reg = PM_PLCFG_PLSEL_PL2; PM->PLCFG.reg = PM_PLCFG_PLSEL_PL2;
while (0 == PM->INTFLAG.bit.PLRDY) {} while (!PM->INTFLAG.bit.PLRDY) {}
MCLK->APBBMASK.reg |= MCLK_APBBMASK_NVMCTRL; MCLK->APBBMASK.reg |= MCLK_APBBMASK_NVMCTRL;
_NVMCTRL->CTRLB.reg |= NVMCTRL_CTRLB_RWS(1); _NVMCTRL->CTRLB.reg |= NVMCTRL_CTRLB_RWS(1);
@ -72,6 +109,9 @@ void cpu_init(void)
OSCCTRL->OSC16MCTRL.bit.ONDEMAND = 0; OSCCTRL->OSC16MCTRL.bit.ONDEMAND = 0;
OSCCTRL->OSC16MCTRL.bit.RUNSTDBY = 0; OSCCTRL->OSC16MCTRL.bit.RUNSTDBY = 0;
_osc32k_setup();
_xosc32k_setup();
/* Setup GCLK generators */ /* Setup GCLK generators */
_gclk_setup(0, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSC16M); _gclk_setup(0, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSC16M);

46
cpu/saml21/cpu.c
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@ -20,11 +20,47 @@
#include "cpu.h" #include "cpu.h"
#include "periph/init.h" #include "periph/init.h"
#include "periph_conf.h"
static void _gclk_setup(int gclk, uint32_t reg) static void _gclk_setup(int gclk, uint32_t reg)
{ {
while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(gclk)) {}
GCLK->GENCTRL[gclk].reg = reg; GCLK->GENCTRL[gclk].reg = reg;
while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(gclk)) {}
}
static void _osc32k_setup(void)
{
#if INTERNAL_OSC32_SOURCE
uint32_t * pCalibrationArea;
uint32_t osc32kcal;
/* Read OSC32KCAL, calibration data for OSC32 !!! */
pCalibrationArea = (uint32_t*) NVMCTRL_OTP5;
osc32kcal = ( (*pCalibrationArea) & 0x1FC0 ) >> 6;
/* RTC use Low Power Internal Oscillator at 32kHz */
OSC32KCTRL->OSC32K.reg = OSC32KCTRL_OSC32K_RUNSTDBY
| OSC32KCTRL_OSC32K_EN32K
| OSC32KCTRL_OSC32K_CALIB(osc32kcal)
| OSC32KCTRL_OSC32K_ENABLE;
/* Wait OSC32K Ready */
while (!OSC32KCTRL->STATUS.bit.OSC32KRDY) {}
#endif /* INTERNAL_OSC32_SOURCE */
}
static void _xosc32k_setup(void)
{
#if EXTERNAL_OSC32_SOURCE
/* RTC uses External 32,768KHz Oscillator */
OSC32KCTRL->XOSC32K.reg = OSC32KCTRL_XOSC32K_XTALEN
| OSC32KCTRL_XOSC32K_RUNSTDBY
| OSC32KCTRL_XOSC32K_EN32K
| OSC32KCTRL_XOSC32K_ENABLE;
/* Wait XOSC32K Ready */
while (!OSC32KCTRL->STATUS.bit.XOSC32KRDY) {}
#endif
} }
/** /**
@ -59,17 +95,19 @@ void cpu_init(void)
while (GCLK->CTRLA.reg & GCLK_CTRLA_SWRST) {} while (GCLK->CTRLA.reg & GCLK_CTRLA_SWRST) {}
while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) {} while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) {}
PM->PLCFG.reg = PM_PLCFG_PLSEL_PL2;
while (!PM->INTFLAG.bit.PLRDY) {}
/* set OSC16M to 16MHz */ /* set OSC16M to 16MHz */
OSCCTRL->OSC16MCTRL.bit.FSEL = 3; OSCCTRL->OSC16MCTRL.bit.FSEL = 3;
OSCCTRL->OSC16MCTRL.bit.ONDEMAND = 0; OSCCTRL->OSC16MCTRL.bit.ONDEMAND = 0;
OSCCTRL->OSC16MCTRL.bit.RUNSTDBY = 0; OSCCTRL->OSC16MCTRL.bit.RUNSTDBY = 0;
PM->PLCFG.reg = PM_PLCFG_PLSEL_PL2; _osc32k_setup();
while (!PM->INTFLAG.bit.PLRDY) {} _xosc32k_setup();
/* Setup GCLK generators */ /* Setup GCLK generators */
_gclk_setup(0, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSC16M); _gclk_setup(0, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSC16M);
_gclk_setup(1, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSCULP32K);
#ifdef MODULE_PERIPH_PM #ifdef MODULE_PERIPH_PM
PM->CTRLA.reg = PM_CTRLA_MASK & (~PM_CTRLA_IORET); PM->CTRLA.reg = PM_CTRLA_MASK & (~PM_CTRLA_IORET);