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boards: adapt stm32f[2|4|7] boards clock config

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This commit is contained in:
Vincent Dupont 2017-08-16 16:17:31 +02:00
parent 33e8a419be
commit fc9fc57aa6
16 changed files with 290 additions and 106 deletions
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19
boards/f4vi1/include/periph_conf.h
View File

@ -28,25 +28,34 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 168MHz */
#define CLOCK_CORECLOCK (168000000U)
/* 0: no external high speed crystal available /* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */ * else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (16000000U) #define CLOCK_HSE (16000000U)
/* 0: no external low speed crystal available, /* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */ * 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (0) #define CLOCK_LSE (0)
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 168MHz */
#define CLOCK_CORECLOCK (168000000U)
/* peripheral clock setup */ /* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */ #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1) #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 42MHz */ #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 42MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4) #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 84MHz */ #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 84MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2) #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (8)
#define CLOCK_PLL_N (168)
#define CLOCK_PLL_P (2)
#define CLOCK_PLL_Q (7)
/** @} */ /** @} */
/** /**

19
boards/msbiot/include/periph_conf.h
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@ -26,25 +26,34 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 168MHz */
#define CLOCK_CORECLOCK (168000000U)
/* 0: no external high speed crystal available /* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */ * else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (16000000U) #define CLOCK_HSE (16000000U)
/* 0: no external low speed crystal available, /* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */ * 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (0) #define CLOCK_LSE (0)
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 168MHz */
#define CLOCK_CORECLOCK (168000000U)
/* peripheral clock setup */ /* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */ #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1) #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 42MHz */ #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 42MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4) #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 84MHz */ #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 84MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2) #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (8)
#define CLOCK_PLL_N (168)
#define CLOCK_PLL_P (2)
#define CLOCK_PLL_Q (7)
/** @} */ /** @} */
/** /**

21
boards/nucleo-f401/include/periph_conf.h
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@ -26,27 +26,34 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 84MHz */
#define CLOCK_CORECLOCK (84000000U)
/* 0: no external high speed crystal available /* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */ * else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U) #define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available, /* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */ * 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1) #define CLOCK_LSE (1)
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 84MHz */
#define CLOCK_CORECLOCK (84000000U)
/* PLL Output divisor */
#define P (4U)
/* peripheral clock setup */ /* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */ #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1) #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 42MHz */ #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 42MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 84MHz */ #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 84MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* Main PLL factors */
#define CLOCK_PLL_M (4)
#define CLOCK_PLL_N (168)
#define CLOCK_PLL_P (4)
#define CLOCK_PLL_Q (7)
/** @} */ /** @} */
/** /**

43
boards/nucleo-f410/include/periph_conf.h
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@ -26,25 +26,34 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 100MHz */
#define CLOCK_CORECLOCK (96000000U)
/* 0: no external high speed crystal available /* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */ * else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U) #define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available, /* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */ * 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1) #define CLOCK_LSE (1)
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 100MHz */
#define CLOCK_CORECLOCK (96000000U)
/* peripheral clock setup */ /* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */ #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1) #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */ #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */ #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* Main PLL factors */
#define CLOCK_PLL_M (4)
#define CLOCK_PLL_N (192)
#define CLOCK_PLL_P (4)
#define CLOCK_PLL_Q (8)
/** @} */ /** @} */
/** /**
@ -119,19 +128,19 @@ static const uart_conf_t uart_config[] = {
* @{ * @{
*/ */
static const uint8_t spi_divtable[2][5] = { static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 50000000Hz */ { /* for APB1 @ 48000000Hz */
7, /* -> 195312Hz */ 7, /* -> 187500Hz */
6, /* -> 390625Hz */ 6, /* -> 375000Hz */
5, /* -> 781250Hz */ 5, /* -> 750000Hz */
2, /* -> 6250000Hz */ 2, /* -> 6000000Hz */
1 /* -> 12500000Hz */ 1 /* -> 12000000Hz */
}, },
{ /* for APB2 @ 100000000Hz */ { /* for APB2 @ 96000000Hz */
7, /* -> 390625Hz */ 7, /* -> 375000Hz */
7, /* -> 390625Hz */ 7, /* -> 375000Hz */
6, /* -> 781250Hz */ 6, /* -> 750000Hz */
3, /* -> 6250000Hz */ 3, /* -> 6000000Hz */
2 /* -> 12500000Hz */ 2 /* -> 12000000Hz */
} }
}; };

43
boards/nucleo-f411/include/periph_conf.h
View File

@ -26,25 +26,34 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 100MHz */
#define CLOCK_CORECLOCK (96000000U)
/* 0: no external high speed crystal available /* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */ * else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U) #define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available, /* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */ * 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1) #define CLOCK_LSE (1)
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 100MHz */
#define CLOCK_CORECLOCK (96000000U)
/* peripheral clock setup */ /* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */ #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1) #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */ #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */ #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* Main PLL factors */
#define CLOCK_PLL_M (4)
#define CLOCK_PLL_N (192)
#define CLOCK_PLL_P (4)
#define CLOCK_PLL_Q (8)
/** @} */ /** @} */
/** /**
@ -165,19 +174,19 @@ static const pwm_conf_t pwm_config[] = {
* @{ * @{
*/ */
static const uint8_t spi_divtable[2][5] = { static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 50000000Hz */ { /* for APB1 @ 48000000Hz */
7, /* -> 195312Hz */ 7, /* -> 187500Hz */
6, /* -> 390625Hz */ 6, /* -> 375000Hz */
5, /* -> 781250Hz */ 5, /* -> 750000Hz */
2, /* -> 6250000Hz */ 2, /* -> 6000000Hz */
1 /* -> 12500000Hz */ 1 /* -> 12000000Hz */
}, },
{ /* for APB2 @ 100000000Hz */ { /* for APB2 @ 96000000Hz */
7, /* -> 390625Hz */ 7, /* -> 375000Hz */
7, /* -> 390625Hz */ 7, /* -> 375000Hz */
6, /* -> 781250Hz */ 6, /* -> 750000Hz */
3, /* -> 6250000Hz */ 3, /* -> 6000000Hz */
2 /* -> 12500000Hz */ 2 /* -> 12000000Hz */
} }
}; };

29
boards/nucleo-f446/include/periph_conf.h
View File

@ -26,25 +26,44 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 180MHz */
#define CLOCK_CORECLOCK (180000000U)
/* 0: no external high speed crystal available /* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */ * else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U) #define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available, /* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */ * 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1) #define CLOCK_LSE (1)
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 180MHz */
#define CLOCK_CORECLOCK (168000000U)
/* peripheral clock setup */ /* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */ #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1) #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 45MHz */ #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 45MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4) #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 90MHz */ #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 90MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2) #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (4)
#define CLOCK_PLL_N (180)
#define CLOCK_PLL_P (2)
#define CLOCK_PLL_Q (0)
/* PLL SAI configuration */
#define CLOCK_ENABLE_PLL_SAI (1)
#define CLOCK_PLL_SAI_M (4)
#define CLOCK_PLL_SAI_N (192)
#define CLOCK_PLL_SAI_P (8)
#define CLOCK_PLL_SAI_Q (0)
/* Use alternative source for 48MHz clock */
#define CLOCK_USE_ALT_48MHZ (1)
/** @} */ /** @} */
/** /**

19
boards/nucleo144-f207/include/periph_conf.h
View File

@ -28,25 +28,34 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 120MHz */
#define CLOCK_CORECLOCK (120000000U)
/* 0: no external high speed crystal available /* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */ * else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U) #define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available, /* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */ * 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1) #define CLOCK_LSE (1)
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 120MHz */
#define CLOCK_CORECLOCK (120000000U)
/* peripheral clock setup */ /* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */ #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1) #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 30MHz */ #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 30MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4) #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 60MHz */ #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 60MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2) #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (4)
#define CLOCK_PLL_N (120)
#define CLOCK_PLL_P (2)
#define CLOCK_PLL_Q (5)
/** @} */ /** @} */
/** /**

30
boards/nucleo144-f412/include/periph_conf.h
View File

@ -28,25 +28,45 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 100MHz */
#define CLOCK_CORECLOCK (100000000U)
/* 0: no external high speed crystal available /* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */ * else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U) #define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available, /* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */ * 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1) #define CLOCK_LSE (1)
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 100MHz */
#define CLOCK_CORECLOCK (96000000U)
/* peripheral clock setup */ /* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */ #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1) #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */ #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */ #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* Main PLL factors */
#define CLOCK_PLL_M (4)
#define CLOCK_PLL_N (200)
#define CLOCK_PLL_P (4)
#define CLOCK_PLL_Q (0)
/* PLL I2S configuration */
#define CLOCK_ENABLE_PLL_I2S (1)
#define CLOCK_PLL_I2S_SRC (0)
#define CLOCK_PLL_I2S_M (4)
#define CLOCK_PLL_I2S_N (216)
#define CLOCK_PLL_I2S_P (0)
#define CLOCK_PLL_I2S_Q (9)
/* Use alternative source for 48MHz clock */
#define CLOCK_USE_ALT_48MHZ (1)
/** @} */ /** @} */
/** /**

30
boards/nucleo144-f413/include/periph_conf.h
View File

@ -28,25 +28,45 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 100MHz */
#define CLOCK_CORECLOCK (100000000U)
/* 0: no external high speed crystal available /* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */ * else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U) #define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available, /* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */ * 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1) #define CLOCK_LSE (1)
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 100MHz */
#define CLOCK_CORECLOCK (96000000U)
/* peripheral clock setup */ /* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */ #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1) #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */ #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */ #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* Main PLL factors */
#define CLOCK_PLL_M (4)
#define CLOCK_PLL_N (200)
#define CLOCK_PLL_P (4)
#define CLOCK_PLL_Q (0)
/* PLL I2S configuration */
#define CLOCK_ENABLE_PLL_I2S (1)
#define CLOCK_PLL_I2S_SRC (0)
#define CLOCK_PLL_I2S_M (4)
#define CLOCK_PLL_I2S_N (216)
#define CLOCK_PLL_I2S_P (0)
#define CLOCK_PLL_I2S_Q (9)
/* Use alternative source for 48MHz clock */
#define CLOCK_USE_ALT_48MHZ (1)
/** @} */ /** @} */
/** /**

19
boards/nucleo144-f429/include/periph_conf.h
View File

@ -26,25 +26,34 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 180MHz */
#define CLOCK_CORECLOCK (168000000U)
/* 0: no external high speed crystal available /* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */ * else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U) #define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available, /* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */ * 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1) #define CLOCK_LSE (1)
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 180MHz */
#define CLOCK_CORECLOCK (168000000U)
/* peripheral clock setup */ /* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */ #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1) #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 45MHz */ #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 45MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4) #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 90MHz */ #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 90MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2) #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (4)
#define CLOCK_PLL_N (168)
#define CLOCK_PLL_P (2)
#define CLOCK_PLL_Q (7)
/** @} */ /** @} */
/** /**

29
boards/nucleo144-f446/include/periph_conf.h
View File

@ -26,25 +26,44 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 180MHz */
#define CLOCK_CORECLOCK (180000000U)
/* 0: no external high speed crystal available /* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */ * else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U) #define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available, /* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */ * 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1) #define CLOCK_LSE (1)
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 100MHz */
#define CLOCK_CORECLOCK (168000000U)
/* peripheral clock setup */ /* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */ #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1) #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 45MHz */ #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 45MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4) #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 90MHz */ #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 90MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2) #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (4)
#define CLOCK_PLL_N (180)
#define CLOCK_PLL_P (2)
#define CLOCK_PLL_Q (0)
/* PLL SAI configuration */
#define CLOCK_ENABLE_PLL_SAI (1)
#define CLOCK_PLL_SAI_M (4)
#define CLOCK_PLL_SAI_N (192)
#define CLOCK_PLL_SAI_P (8)
#define CLOCK_PLL_SAI_Q (0)
/* Use alternative source for 48MHz clock */
#define CLOCK_USE_ALT_48MHZ (1)
/** @} */ /** @} */
/** /**

19
boards/nucleo144-f722/include/periph_conf.h
View File

@ -26,25 +26,34 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 216MHz */
#define CLOCK_CORECLOCK (216000000U)
/* 0: no external high speed crystal available /* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */ * else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U) #define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available, /* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */ * 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1) #define CLOCK_LSE (1)
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 216MHz, min: 96MHz, must be multiple of 24MHz */
#define CLOCK_CORECLOCK (216000000U)
/* peripheral clock setup */ /* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */ #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1) #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 54MHz */ #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 54MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4) #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 108MHz */ #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 108MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2) #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (4)
#define CLOCK_PLL_N (216)
#define CLOCK_PLL_P (2)
#define CLOCK_PLL_Q (9)
/** @} */ /** @} */
/** /**

19
boards/nucleo144-f746/include/periph_conf.h
View File

@ -26,25 +26,34 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 216MHz */
#define CLOCK_CORECLOCK (216000000U)
/* 0: no external high speed crystal available /* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */ * else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U) #define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available, /* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */ * 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1) #define CLOCK_LSE (1)
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 216MHz, min: 96MHz, must be multiple of 24MHz */
#define CLOCK_CORECLOCK (216000000U)
/* peripheral clock setup */ /* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */ #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1) #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 54MHz */ #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 54MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4) #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 108MHz */ #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 108MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2) #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (4)
#define CLOCK_PLL_N (216)
#define CLOCK_PLL_P (2)
#define CLOCK_PLL_Q (9)
/** @} */ /** @} */
/** /**

19
boards/nucleo144-f767/include/periph_conf.h
View File

@ -26,25 +26,34 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 216MHz */
#define CLOCK_CORECLOCK (216000000U)
/* 0: no external high speed crystal available /* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */ * else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U) #define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available, /* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */ * 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1) #define CLOCK_LSE (1)
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 216MHz, min: 96MHz, must be multiple of 24MHz */
#define CLOCK_CORECLOCK (216000000U)
/* peripheral clock setup */ /* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */ #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1) #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 54MHz */ #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 54MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4) #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 108MHz */ #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 108MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2) #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (4)
#define CLOCK_PLL_N (216)
#define CLOCK_PLL_P (2)
#define CLOCK_PLL_Q (9)
/** @} */ /** @} */
/** /**

19
boards/stm32f4discovery/include/periph_conf.h
View File

@ -27,25 +27,34 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 168MHz */
#define CLOCK_CORECLOCK (168000000U)
/* 0: no external high speed crystal available /* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */ * else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U) #define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available, /* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */ * 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1) #define CLOCK_LSE (1)
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 168MHz */
#define CLOCK_CORECLOCK (168000000U)
/* peripheral clock setup */ /* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */ #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1) #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 42MHz */ #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 42MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4) #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 84MHz */ #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 84MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2) #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (4)
#define CLOCK_PLL_N (168)
#define CLOCK_PLL_P (2)
#define CLOCK_PLL_Q (7)
/** @} */ /** @} */
/** /**

19
boards/stm32f7discovery/include/periph_conf.h
View File

@ -26,25 +26,34 @@ extern "C" {
#endif #endif
/** /**
* @name Clock system configuration * @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{ * @{
*/ */
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 216MHz */
#define CLOCK_CORECLOCK (216000000U)
/* 0: no external high speed crystal available /* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */ * else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (25000000U) #define CLOCK_HSE (25000000U)
/* 0: no external low speed crystal available, /* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */ * 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1) #define CLOCK_LSE (1)
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 216MHz, min: 96MHz, must be multiple of 48MHz */
#define CLOCK_CORECLOCK (216000000U)
/* peripheral clock setup */ /* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */ #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1) #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 54MHz */ #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 54MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4) #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 108MHz */ #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 108MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2) #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (25)
#define CLOCK_PLL_N (432)
#define CLOCK_PLL_P (2)
#define CLOCK_PLL_Q (9)
/** @} */ /** @} */
/** /**