3 Commits

Author	SHA1	Message	Date
Benjamin Valentin	38b6ee56f3	cpu/sam0: use defines for GCLK IDs ... Give the clocks explicit names to better identify their meaning.	2020-02-04 21:16:54 +01:00
Benjamin Valentin	736e5e5a35	cpu/samd5x: allow more flexible selection of CLOCK_CORECLOCK ... There are some constraints to the oscillators on the samd5x. - DFLL is fixed to run at 48 MHz - DPLL can run at 96 to 200 MHz Always use DFLL for frequencies <= 48 MHz. For frequencies >= 96 MHz, use DPLL directly. For frequencies < 96 MHz, clock DPLL at twice the desired frequency and use a divider.	2019-09-27 10:49:43 +02:00
Benjamin Valentin	f375b00ff3	cpu/samd5x: add support for samd5x/same5x MCUs ... This adds supoprt for the Atmel SAMD51 & SAME54 SoC. The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.	2019-06-06 16:47:11 +02:00