The buffer[EHTHERNET_MAX_LEN] used in _esp_wifi_send to convert the iolist of the given packet to a plain buffer for the WiFi interface should not be on the stack to prevent the sending thread's stack from overflowing.
- Using a enum instead of _COUNTER is easier to read
- _COUNTER is also a reserved name; so better not use it to avoid issues
- Split out the pcint code into a static inline function for increased
readability
The bank index and the pin number are not necessarily identical. For all
PCINT banks except for bank 3 bank_idx was used therefore. It was likely
just forgotten to update that for bank 3 as well.
Some ESP8266/ESP8285 modules only work with DOUT SPI flash mode and a SPI flash frequency of 26 MHz. Therefore, these parameters have to be used by default. Otherwise some modules will no boot.
For better compatibility copy most of cortexm_base.ld
and use the same section names.
Only interrupt stacks and the two additional (currently unused)
heap sections are different between the two now.
Both architectures are variants of the ARM architecture and use the same
toolchain.
There is no reason to have such wildly different defaults.
This results in some tests passing that would crash before:
- [x] `tests/pkg_libcose`
- [x] `tests/pkg_qdsa`
- [x] `tests/pkg_relic`
- [x] `tests/pkg_tweetnacl`
- [x] `tests/pthread_tls`
`THREAD_EXTRA_STACKSIZE_PRINTF_FLOAT` is not used anywhere in RIOT
anymore, so just drop it.
Startup information, including board configuration, is only printed when module esp_log_startup is used. This reduces the amount of information that is printed by default to the console during the startup. The user can enable module esp_log_startup to get the additional startup information.
To avoid that murdock times out before tests/pkg_spiffs and tests/pkg_littlefs time out, the configured test timeouts for these tests is reduced to 200 seconds which should be enough. An ESP32 needs an average of 60 seconds for these tests, while an ESP8266 needs in average 100 seconds.
ESP32 nodes can crash during SPI Flash write operations if required parts of the code are not in the IRAM but in the cached SPI Flash memory, which is disabled during the SPI Flash write operations. Therefore, the code of the SPIFFS package and the VFS module are now stored in the IRAM.
Building e.g. gnrc_border_router example on FreeBSD fails due to
missing defines related to sockets. This adds the missing header
<sys/socket.h> to fix compiling.
Now that CPU and CPU_MODEL are defined in the board's Makefile.features
it can be used to determine the available features provided by the
specific model.
Setting up the .data and .bss section happens in arm7_init.c now.
The code was commented out anyway, so just remove it.
Also remove leftover variable declarations that were only used in
the dead code.
To reduce the information that are printed at the console during the startup, special bootloaders are required that suppress the outputs which are only informational. The according bootloader has to be selected during the make process.
Startup information, including board configuration, is only printed when module esp_log_startup is used. This reduces the amount of information that is printed by default to the console during the startup. The user can enable module esp_log_startup to get the additional startup information.
lpc23xx has 2k of battery RAM that is retained in Deep Power Down mode.
To not overwrite that data it must only be initialized on Power On Reset.
However, RSIR looks the same when waking up from Deep Power Down as it does
on the power-on case.
So use 4 bytes of the backup RAM to keep a signature that is only valid if
memory was retained (no power-on Reset).
A small change to the linker script is required so two sections can be
placed into flash.
The UART peripheral clock seems to be sporadically set to wrong value when the CPU clock is changed. In this case, the UART clock is not set to 115.200 kbps but to 96 kbps, so that the output in the console seems like garbage. This can also cause automatic tests to fail. Therefore, the CPU clock is only changed if CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ defines a different default CPU clock than the one already used at boot time.
The common ADC API dictates that a sample call must return -1 on an
incorrect resolution. The sam0 ADC implementation instead threw an
assertion failure.
