7 Commits

Author SHA1 Message Date
Koen Zandberg
48aa533639
cpu/riscv_common: Add CLIC peripheral driver
The CLIC is a next generation interrupt controller for the RISC-V
architecture.

Co-authored-by:
2021-08-24 10:30:18 +02:00
Koen Zandberg
9239c2fe14
cpu/riscv_common: Add bit set and clear functions 2021-08-24 10:30:15 +02:00
Koen Zandberg
c1d81cfb56
cpu/riscv_common: Jump to rom start on boot
With this the riscv start code jumps to the ROM start on boot when the
ROM area doesn't start at address 0x0.
2021-08-24 10:30:12 +02:00
Sören Tempel
5b15dc8932 fe310: Fix debug format strings
read_csr() returns an unsigned long, not a uint32_t. This causes a
-Wformat warning to be emitted when compiling with clang. This commit
fixes the warning by changing the format string.
2020-10-07 19:07:23 +00:00
Sören Tempel
125e4b54c1 fe310: Support the LLVM toolchain (i.e. compilation with clang)
This requires -nostartfiles to be only passed to the linker, not the
compiler, as it is a linker flag and passing it to the compiler causes a
clang warning to be emitted.

Additionally, clang does not seem to support `-mcmodel=medlow` and
`-msmall-data-limit=8` but these options do not seem strictly necessary
to me anyhow thus they are deactivated conditionally when using clang.
2020-10-07 07:37:52 +00:00
Koen Zandberg
0b2810a856
riscv_common: make thread_yield_higher IRQ compatible 2021-02-08 11:04:18 +01:00
Koen Zandberg
2692957c0e
riscv_common: Refactor common fe310 code to riscv_common 2021-02-05 09:32:19 +01:00