2 Commits

Author	SHA1	Message	Date
Sebastian Meiling	ea0b5ff0dd	cpu: add missing arch features to fe310 ... Adds arch_32bit and arch_riscv to cpu/fe310 to allow for feature requirements and blacklisting.	2019-10-14 17:40:23 +02:00
kenrabold	7d1d5e77d8	cpu/fe310: add RISC-V cpu FE310 ... New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools	2018-05-29 15:21:45 -07:00