2 Commits

Author	SHA1	Message	Date
Alexandre Abadie	42a544bc6a	cpu/stm32l4/wb: ensure LPTIM clock source is correctly reset	2020-03-27 10:57:49 +01:00
Francisco Molina	c6e0e7adcb	cpu/stm32_common: add common L4 and WB stmclk	2020-03-25 09:29:57 +01:00