Alexandre Abadie
0aadf367cc
cpu/stm32: rework common clock source selection header
2021-01-25 11:46:34 +01:00
Alexandre Abadie
2f2622c76f
cpu/stm32: move stm32l5 default PLL N to cpu
2020-11-10 09:34:07 +01:00
Alexandre Abadie
36d33d38f7
cpu/stm32: move stm32l4+ default PLL N to cpu
2020-11-10 09:34:07 +01:00
Alexandre Abadie
934028c114
cpu/stm32: fix l4l5wb clock configuration
...
Default values were wrong for WB when using HSE 32MHz as PLL input source
Default PLL input source was wrong when not using HSE and the board
provides an HSE
2020-11-10 09:34:07 +01:00
Alexandre Abadie
ec5b47fc61
cpu/stm32l4+/wb: centralize max core clock define, adapt related boards
2020-10-27 08:44:55 +01:00
