This commit reworks the trap entry to only save the callee-saved
registers when a context switch is required. the caller-saved registers
are always stored and restored to adhere to the RISC-V ABI. This saves
considerable cycles on interrupts.
The RISC-V timer should only be touched by periph/timer and must not be
initialized and enabled by the IRQ code. The current code can cause an
unhandled interrupt when the timer is not used and the mtime register
hits UINT64_MAX.
