10875890e0
- Before, HSI was enabled as the default case when it is only used for stm32f0 and stm32f1. It is now implemented explicitly for those platforms, and only those.
226 lines
6.5 KiB
C
226 lines
6.5 KiB
C
/*
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* Copyright (C) 2016 Freie Universität Berlin
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* 2018 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32_common
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* @ingroup drivers_periph_flashpage
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* @{
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*
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* @file
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* @brief Low-level flash page driver implementation
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Francisco Acosta <francisco.acosta@inria.fr>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*
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* @}
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*/
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#include "cpu.h"
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#include "stmclk.h"
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#include "assert.h"
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#define ENABLE_DEBUG (0)
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#include "debug.h"
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#include "periph/flashpage.h"
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#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
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/* Program memory unlock keys */
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#define FLASH_PRGKEY1 ((uint32_t)0x8C9DAEBF)
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#define FLASH_PRGKEY2 ((uint32_t)0x13141516)
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#define CNTRL_REG (FLASH->PECR)
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#define CNTRL_REG_LOCK (FLASH_PECR_PELOCK)
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#define FLASH_CR_PER (FLASH_PECR_ERASE | FLASH_PECR_PROG)
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#define FLASH_CR_PG (FLASH_PECR_FPRG | FLASH_PECR_PROG)
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#define FLASHPAGE_DIV (4U) /* write 4 bytes in one go */
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#else
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#if defined(CPU_FAM_STM32L4)
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#define FLASHPAGE_DIV (8U)
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#else
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#define FLASHPAGE_DIV (2U)
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#endif
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#define CNTRL_REG (FLASH->CR)
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#define CNTRL_REG_LOCK (FLASH_CR_LOCK)
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#endif
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extern void _lock(void);
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extern void _unlock(void);
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extern void _wait_for_pending_operations(void);
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static void _unlock_flash(void)
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{
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_unlock();
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#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
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DEBUG("[flashpage] unlocking the flash program memory\n");
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if (!(CNTRL_REG & CNTRL_REG_LOCK)) {
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if (CNTRL_REG & FLASH_PECR_PRGLOCK) {
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DEBUG("[flashpage] setting the program memory unlock keys\n");
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FLASH->PRGKEYR = FLASH_PRGKEY1;
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FLASH->PRGKEYR = FLASH_PRGKEY2;
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}
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}
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#endif
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}
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static void _erase_page(void *page_addr)
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{
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#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1) || \
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defined(CPU_FAM_STM32L4)
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uint32_t *dst = page_addr;
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#else
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uint16_t *dst = page_addr;
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#endif
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#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1)
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uint32_t hsi_state = (RCC->CR & RCC_CR_HSION);
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/* the internal RC oscillator (HSI) must be enabled */
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stmclk_enable_hsi();
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#endif
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/* unlock the flash module */
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_unlock_flash();
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/* make sure no flash operation is ongoing */
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_wait_for_pending_operations();
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/* set page erase bit and program page address */
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DEBUG("[flashpage] erase: setting the erase bit\n");
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CNTRL_REG |= FLASH_CR_PER;
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DEBUG("address to erase: %p\n", page_addr);
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#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
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DEBUG("[flashpage] erase: trigger the page erase\n");
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*dst = (uint32_t)0;
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#elif defined(CPU_FAM_STM32L4)
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DEBUG("[flashpage] erase: setting the page address\n");
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CNTRL_REG |= FLASH_CR_PER;
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uint8_t pn;
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#if FLASHPAGE_NUMOF <= 256
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pn = (uint8_t)flashpage_page(dst);
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#else
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uint16_t page = flashpage_page(dst);
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if (page > 255) {
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CNTRL_REG |= FLASH_CR_BKER;
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}
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else {
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CNTRL_REG &= ~FLASH_CR_BKER;
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}
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pn = (uint8_t)page;
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#endif
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CNTRL_REG |= (uint32_t)(pn << FLASH_CR_PNB_Pos);
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CNTRL_REG |= FLASH_CR_STRT;
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#else /* CPU_FAM_STM32F0 || CPU_FAM_STM32F1 */
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DEBUG("[flashpage] erase: setting the page address\n");
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FLASH->AR = (uint32_t)dst;
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/* trigger the page erase and wait for it to be finished */
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DEBUG("[flashpage] erase: trigger the page erase\n");
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CNTRL_REG |= FLASH_CR_STRT;
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#endif
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/* wait as long as device is busy */
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_wait_for_pending_operations();
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/* reset PER bit */
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DEBUG("[flashpage] erase: resetting the page erase bit\n");
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CNTRL_REG &= ~(FLASH_CR_PER);
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/* lock the flash module again */
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_lock();
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#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1)
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/* restore the HSI state */
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if (!hsi_state) {
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stmclk_disable_hsi();
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}
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#endif
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}
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void flashpage_write_raw(void *target_addr, const void *data, size_t len)
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{
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/* assert multiples of FLASHPAGE_RAW_BLOCKSIZE are written and no less of
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that length. */
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assert(!(len % FLASHPAGE_RAW_BLOCKSIZE));
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/* ensure writes are aligned */
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assert(!(((unsigned)target_addr % FLASHPAGE_RAW_ALIGNMENT) ||
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((unsigned)data % FLASHPAGE_RAW_ALIGNMENT)));
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/* ensure the length doesn't exceed the actual flash size */
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assert(((unsigned)target_addr + len) <
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(CPU_FLASH_BASE + (FLASHPAGE_SIZE * FLASHPAGE_NUMOF)) + 1);
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#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
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uint32_t *dst = target_addr;
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const uint32_t *data_addr = data;
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#elif defined(CPU_FAM_STM32L4)
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uint64_t *dst = target_addr;
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const uint64_t *data_addr = data;
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#else
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uint16_t *dst = (uint16_t *)target_addr;
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const uint16_t *data_addr = data;
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#endif
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#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1)
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uint32_t hsi_state = (RCC->CR & RCC_CR_HSION);
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/* the internal RC oscillator (HSI) must be enabled */
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stmclk_enable_hsi();
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#endif
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/* unlock the flash module */
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_unlock_flash();
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DEBUG("[flashpage_raw] write: now writing the data\n");
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#if !(defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1))
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/* set PG bit and program page to flash */
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CNTRL_REG |= FLASH_CR_PG;
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#endif
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for (size_t i = 0; i < (len / FLASHPAGE_DIV); i++) {
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DEBUG("[flashpage_raw] writing %c to %p\n", (char)data_addr[i], dst);
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*dst++ = data_addr[i];
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/* wait as long as device is busy */
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_wait_for_pending_operations();
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}
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/* clear program bit again */
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CNTRL_REG &= ~(FLASH_CR_PG);
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DEBUG("[flashpage_raw] write: done writing data\n");
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/* lock the flash module again */
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_lock();
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#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1)
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/* restore the HSI state */
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if (!hsi_state) {
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stmclk_disable_hsi();
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}
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#endif
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}
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void flashpage_write(int page, const void *data)
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{
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assert(page < (int)FLASHPAGE_NUMOF);
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#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
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/* STM32L0/L1 only supports word sizes */
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uint32_t *page_addr = flashpage_addr(page);
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#elif defined(CPU_FAM_STM32L4)
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uint64_t *page_addr = flashpage_addr(page);
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#else
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/* Default is to support half-word sizes */
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uint16_t *page_addr = flashpage_addr(page);
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#endif
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/* ERASE sequence */
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_erase_page(page_addr);
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/* WRITE sequence */
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if (data != NULL) {
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flashpage_write_raw(page_addr, data, FLASHPAGE_SIZE);
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}
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}
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