139 lines
3.5 KiB
Plaintext
139 lines
3.5 KiB
Plaintext
/*
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* Copyright (C) 2014-2016 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32f1
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* @{
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*
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* @file
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* @brief Low-level SPI driver implementation
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*
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* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
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* @author Fabian Nack <nack@inf.fu-berlin.de>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
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*
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* @}
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*/
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#include "cpu.h"
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#include "mutex.h"
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#include "assert.h"
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#include "periph/spi.h"
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#define ENABLE_DEBUG (0)
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#include "debug.h"
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/* Remove this ugly guard once we selectively build the periph drivers */
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#ifdef SPI_NUMOF
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/**
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* @brief Number of bits to shift the BR value in the CR1 register
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*/
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#define BR_SHIFT (3U)
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/**
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* @brief Array holding one pre-initialized mutex for each SPI device
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*/
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static mutex_t locks[SPI_NUMOF];
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static inline SPI_TypeDef *dev(spi_t bus)
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{
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return spi_config[bus].dev;
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}
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void spi_init(spi_t bus)
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{
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/* make sure given bus is valid */
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assert(bus <= SPI_NUMOF);
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/* initialize the bus lock */
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mutex_init(&locks[bus]);
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/* trigger pin configuration */
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spi_init_pins(bus);
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}
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void spi_init_pins(spi_t bus)
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{
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gpio_init_af(spi_config[bus].pin_clk, GPIO_AF_OUT_PP);
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gpio_init_af(spi_config[bus].pin_mosi, GPIO_AF_OUT_PP);
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gpio_init(spi_config[bus].pin_miso, GPIO_IN);
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}
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int spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t clk)
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{
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assert((clk >= SPI_CLK_100KHZ) && (clk <= SPI_CLK_10MHZ));
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/* get exclusive bus access */
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mutex_lock(&locks[bus]);
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/* power on the peripheral */
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periph_clk_en(spi_config[bus].apbbus, spi_config[bus].rccmask);
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/* configure mode and bus clock */
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uint8_t br = spi_divtable[spi_config[bus].apbbus][clk];
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dev(bus)->CR1 = (SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_MSTR |
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(mode & 0x3) | (br << BR_SHIFT));
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/* enable the SPI device */
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dev(bus)->CR1 |= SPI_CR1_SPE;
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return SPI_OK;
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}
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void spi_release(spi_t bus)
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{
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/* disable, power off, and release the bus */
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dev(bus)->CR1 = 0;
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periph_clk_dis(spi_config[bus].apbbus, spi_config[bus].rccmask);
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mutex_unlock(&locks[bus]);
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}
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void spi_transfer_bytes(spi_t bus, spi_cs_t cs, bool cont,
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const void *out, void *in, size_t len)
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{
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uint8_t *out_buf = (uint8_t *)out;
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uint8_t *in_buf = (uint8_t *)in;
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assert(in || out);
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/* take care of the chip select */
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if (cs != SPI_CS_UNDEF) {
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gpio_clear((gpio_t)cs);
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}
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if (!in_buf) {
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for (size_t i = 0; i < len; i++) {
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while (!(dev(bus)->SR & SPI_SR_TXE)) {}
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dev(bus)->DR = out_buf[i];
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}
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while ((dev(bus)->SR & SPI_SR_BSY)) {}
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dev(bus)->DR;
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}
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else if (!out_buf) {
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for (size_t i = 0; i < len; i++) {
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dev(bus)->DR = 0;
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while (!dev(bus)->SR & SPI_SR_RXNE) {}
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in_buf[i] = (uint8_t)dev(bus)->DR;
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}
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}
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else {
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for (size_t i = 0; i < len; i++) {
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while (!(dev(bus)->SR & SPI_SR_TXE)) {}
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dev(bus)->DR = out_buf[i];
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while (!(dev(bus)->SR & SPI_SR_RXNE)) {}
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in_buf[i] = (uint8_t)dev(bus)->DR;
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}
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}
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/* finally release chip select line if requested */
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if ((cs != SPI_CS_UNDEF) && (!cont)) {
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gpio_set((gpio_t)cs);
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}
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}
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#endif /* SPI_NUMOF */
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