347 lines
9.3 KiB
C
347 lines
9.3 KiB
C
/*
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* Copyright (C) 2015 Freie Universität Berlin
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* 2015 FreshTemp, LLC.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup driver_periph
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* @{
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*
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* @file
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* @brief Low-level UART driver implementation
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*
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* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
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* @author Troels Hoffmeyer <troels.d.hoffmeyer@gmail.com>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Dylan Laduranty <dylanladuranty@gmail.com>
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*
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* @}
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*/
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#include "cpu.h"
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#include "periph/uart.h"
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#include "periph/gpio.h"
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#define ENABLE_DEBUG (0)
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#include "debug.h"
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/**
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* @brief Allocate memory to store the callback functions
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*/
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static uart_isr_ctx_t uart_ctx[UART_NUMOF];
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/**
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* @brief Get the pointer to the base register of the given UART device
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*
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* @param[in] dev UART device identifier
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*
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* @return base register address
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*/
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static inline SercomUsart *_uart(uart_t dev)
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{
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return uart_config[dev].dev;
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}
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#ifdef CPU_FAM_SAML21
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static uint64_t _long_division(uint64_t n, uint64_t d);
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/**
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* @brief Get the sercom gclk id of the given UART device
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*
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* @param[in] dev UART device identifier
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*
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* @return sercom gclk id
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*/
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static int _get_sercom_gclk_id(SercomUsart *dev)
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{
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int id;
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switch(sercom_id(dev)) {
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case 0:
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id = SERCOM0_GCLK_ID_CORE;
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break;
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case 1:
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id = SERCOM1_GCLK_ID_CORE;
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break;
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case 2:
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id = SERCOM2_GCLK_ID_CORE;
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break;
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case 3:
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id = SERCOM3_GCLK_ID_CORE;
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break;
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case 4:
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id = SERCOM4_GCLK_ID_CORE;
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break;
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case 5:
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id = SERCOM5_GCLK_ID_CORE;
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break;
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default:
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id = -1;
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DEBUG("[UART]: wrong SERCOM ID\n");
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break;
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}
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return id;
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}
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#endif
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static int init_base(uart_t uart, uint32_t baudrate);
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int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
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{
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/* initialize basic functionality */
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int res = init_base(uart, baudrate);
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if (res != UART_OK) {
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return res;
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}
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/* register callbacks */
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uart_ctx[uart].rx_cb = rx_cb;
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uart_ctx[uart].arg = arg;
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/* configure interrupts and enable RX interrupt */
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NVIC_EnableIRQ(SERCOM0_IRQn + sercom_id(_uart(uart)));
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_uart(uart)->INTENSET.reg |= SERCOM_USART_INTENSET_RXC;
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return UART_OK;
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}
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static int init_base(uart_t uart, uint32_t baudrate)
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{
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SercomUsart *dev;
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if ((unsigned int)uart >= UART_NUMOF) {
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return UART_NODEV;
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}
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/* get the devices base register */
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dev = _uart(uart);
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/* configure pins */
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gpio_init(uart_config[uart].rx_pin, GPIO_IN);
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gpio_init_mux(uart_config[uart].rx_pin, uart_config[uart].mux);
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gpio_init(uart_config[uart].tx_pin, GPIO_OUT);
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gpio_init_mux(uart_config[uart].tx_pin, uart_config[uart].mux);
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#ifdef CPU_FAM_SAMD21
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/* calculate baudrate */
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uint32_t baud = ((((uint32_t)CLOCK_CORECLOCK * 10) / baudrate) / 16);
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/* enable sync and async clocks */
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uart_poweron(uart);
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/* reset the UART device */
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dev->CTRLA.reg = SERCOM_USART_CTRLA_SWRST;
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while (dev->SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_SWRST) {}
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/* set asynchronous mode w/o parity, LSB first, TX and RX pad as specified
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* by the board in the periph_conf.h, x16 sampling and use internal clock */
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dev->CTRLA.reg = (SERCOM_USART_CTRLA_DORD |
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SERCOM_USART_CTRLA_SAMPR(0x1) |
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SERCOM_USART_CTRLA_TXPO(uart_config[uart].tx_pad) |
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SERCOM_USART_CTRLA_RXPO(uart_config[uart].rx_pad) |
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SERCOM_USART_CTRLA_MODE_USART_INT_CLK |
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(uart_config[uart].runstdby ?
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SERCOM_USART_CTRLA_RUNSTDBY : 0));
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/* set baudrate */
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dev->BAUD.FRAC.FP = (baud % 10);
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dev->BAUD.FRAC.BAUD = (baud / 10);
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/* enable receiver and transmitter, use 1 stop bit */
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dev->CTRLB.reg = (SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN);
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while (dev->SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_CTRLB) {}
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#elif CPU_FAM_SAML21
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/* Calculate the BAUD value */
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uint64_t temp1 = ((16 * ((uint64_t)baudrate)) << 32);
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uint64_t ratio = _long_division(temp1 , CLOCK_CORECLOCK);
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uint64_t scale = ((uint64_t)1 << 32) - ratio;
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uint64_t baud_calculated = (65536 * scale) >> 32;
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dev->CTRLA.bit.ENABLE = 0; /* Disable to write, need to sync tho */
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while(dev->SYNCBUSY.bit.ENABLE) {}
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/* set to LSB, asynchronous mode without parity, PAD0 Tx, PAD1 Rx,
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* 16x over-sampling, internal clk */
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dev->CTRLA.reg = SERCOM_USART_CTRLA_DORD \
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| SERCOM_USART_CTRLA_FORM(0x0) \
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| SERCOM_USART_CTRLA_SAMPA(0x0) \
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| SERCOM_USART_CTRLA_TXPO(uart_config[uart].tx_pad) \
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| SERCOM_USART_CTRLA_RXPO(uart_config[uart].rx_pad) \
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| SERCOM_USART_CTRLA_SAMPR(0x0) \
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| SERCOM_USART_CTRLA_MODE(0x1) \
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| (uart_config[uart].runstdby ?
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SERCOM_USART_CTRLA_RUNSTDBY : 0);
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/* Set baud rate */
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dev->BAUD.bit.BAUD = baud_calculated;
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/* enable receiver and transmitter, one stop bit*/
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dev->CTRLB.reg = (SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN);
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while(dev->SYNCBUSY.bit.CTRLB) {}
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uart_poweron(uart);
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#endif
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return UART_OK;
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}
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void uart_write(uart_t uart, const uint8_t *data, size_t len)
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{
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for (size_t i = 0; i < len; i++) {
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while (!(_uart(uart)->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE)) {}
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_uart(uart)->DATA.reg = data[i];
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while (_uart(uart)->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) {}
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}
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}
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void uart_poweron(uart_t uart)
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{
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SercomUsart *dev;
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/* get the devices base register */
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dev = _uart(uart);
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#ifdef CPU_FAM_SAMD21
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PM->APBCMASK.reg |= (PM_APBCMASK_SERCOM0 << sercom_id(_uart(uart)));
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GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_CLKEN |
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GCLK_CLKCTRL_GEN(uart_config[uart].gclk_src) |
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(SERCOM0_GCLK_ID_CORE + sercom_id(_uart(uart))) <<
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GCLK_CLKCTRL_ID_Pos);
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while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
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#elif CPU_FAM_SAML21
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/* Enable the peripheral channel */
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GCLK->PCHCTRL[_get_sercom_gclk_id(dev)].reg |= GCLK_PCHCTRL_CHEN |
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GCLK_PCHCTRL_GEN(uart_config[uart].gclk_src);
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while (!(GCLK->PCHCTRL[_get_sercom_gclk_id(dev)].reg & GCLK_PCHCTRL_CHEN)) {}
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if(_get_sercom_gclk_id(dev) < 5) {
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MCLK->APBCMASK.reg |= MCLK_APBCMASK_SERCOM0 << sercom_id(dev);
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}
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else {
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MCLK->APBDMASK.reg |= MCLK_APBDMASK_SERCOM5;
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}
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while (dev->SYNCBUSY.reg) {}
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#endif
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/* finally, enable the device */
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dev->CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
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}
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void uart_poweroff(uart_t uart)
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{
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SercomUsart *dev;
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/* get the devices base register */
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dev = _uart(uart);
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#ifdef CPU_FAM_SAMD21
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PM->APBCMASK.reg &= ~(PM_APBCMASK_SERCOM0 << sercom_id(dev));
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GCLK->CLKCTRL.reg = ((SERCOM0_GCLK_ID_CORE + sercom_id(dev)) <<
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GCLK_CLKCTRL_ID_Pos);
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while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
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#elif CPU_FAM_SAML21
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/* Enable the peripheral channel */
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GCLK->PCHCTRL[_get_sercom_gclk_id(dev)].reg &= ~GCLK_PCHCTRL_CHEN;
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if(_get_sercom_gclk_id(dev) < 5) {
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MCLK->APBCMASK.reg &= ~(MCLK_APBCMASK_SERCOM0 << sercom_id(dev));
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}
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else {
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MCLK->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM5;
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}
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while (dev->SYNCBUSY.reg) {}
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#endif
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}
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static inline void irq_handler(uint8_t uartnum)
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{
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SercomUsart *uart = _uart(uartnum);
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#ifdef CPU_FAM_SAMD21
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if (uart->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) {
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/* interrupt flag is cleared by reading the data register */
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uart_ctx[uartnum].rx_cb(uart_ctx[uartnum].arg, (uint8_t)(uart->DATA.reg));
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}
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else if (uart->INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) {
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/* clear error flag */
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uart->INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR;
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}
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#elif CPU_FAM_SAML21
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if (uart->INTFLAG.bit.RXC) {
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/* cleared by reading DATA regiser */
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uint8_t data = (uint8_t)uart->DATA.reg;
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uart_ctx[uartnum].rx_cb(uart_ctx[uartnum].arg, data);
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}
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else if (uart->INTFLAG.bit.ERROR) {
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/* clear error flag */
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uart->INTFLAG.reg |= SERCOM_USART_INTFLAG_ERROR;
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}
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#endif
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cortexm_isr_end();
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}
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#ifdef UART_0_ISR
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void UART_0_ISR(void)
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{
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irq_handler(0);
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}
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#endif
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#ifdef UART_1_ISR
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void UART_1_ISR(void)
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{
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irq_handler(1);
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}
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#endif
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#ifdef UART_2_ISR
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void UART_2_ISR(void)
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{
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irq_handler(2);
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}
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#endif
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#ifdef UART_3_ISR
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void UART_3_ISR(void)
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{
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irq_handler(3);
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}
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#endif
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#ifdef UART_4_ISR
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void UART_4_ISR(void)
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{
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irq_handler(4);
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}
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#endif
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#ifdef UART_5_ISR
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void UART_5_ISR(void)
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{
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irq_handler(5);
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}
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#endif
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#ifdef CPU_FAM_SAML21
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static uint64_t _long_division(uint64_t n, uint64_t d)
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{
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int32_t i;
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uint64_t q = 0, r = 0, bit_shift;
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for (i = 63; i >= 0; i--) {
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bit_shift = (uint64_t)1 << i;
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r = r << 1;
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if (n & bit_shift) {
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r |= 0x01;
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}
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if (r >= d) {
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r = r - d;
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q |= bit_shift;
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}
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}
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return q;
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}
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#endif
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