266 lines
15 KiB
C
266 lines
15 KiB
C
/*
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* Copyright (C) 2015 Rakendra Thapa <rakendrathapa#gmail.com>
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_stm32f4
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* @{
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*
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* @file vectors.c
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* @brief Interrupt vector definitions
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*
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* @author Rakendra Thapa <rakendrathapa@gmail.com>
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*/
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#include <stdint.h>
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#include "vectors_cortexm.h"
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/* get the start of the ISR stack as defined in the linkerscript */
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extern uint32_t _estack;
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/* define a local dummy handler as it needs to be in the same compilation unit
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* as the alias definition */
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void dummy_handler(void) {
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dummy_handler_default();
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}
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/* Cortex-M common interrupt vectors */
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WEAK_DEFAULT void isr_svc(void);
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WEAK_DEFAULT void isr_pendsv(void);
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WEAK_DEFAULT void isr_systick(void);
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/* LM4F120 specific interrupt vectors */
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WEAK_DEFAULT void isr_gpio_porta(void);
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WEAK_DEFAULT void isr_gpio_portb(void);
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WEAK_DEFAULT void isr_gpio_portc(void);
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WEAK_DEFAULT void isr_gpio_portd(void);
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WEAK_DEFAULT void isr_gpio_porte(void);
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WEAK_DEFAULT void isr_uart0(void);
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WEAK_DEFAULT void isr_uart1(void);
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WEAK_DEFAULT void isr_ssi0(void);
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WEAK_DEFAULT void isr_i2c0(void);
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WEAK_DEFAULT void isr_adc0_seq0(void);
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WEAK_DEFAULT void isr_adc0_seq1(void);
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WEAK_DEFAULT void isr_adc0_seq2(void);
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WEAK_DEFAULT void isr_adc0_seq3(void);
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WEAK_DEFAULT void isr_wdt(void);
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WEAK_DEFAULT void isr_timer0a(void);
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WEAK_DEFAULT void isr_timer0b(void);
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WEAK_DEFAULT void isr_timer1a(void);
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WEAK_DEFAULT void isr_timer1b(void);
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WEAK_DEFAULT void isr_timer2a(void);
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WEAK_DEFAULT void isr_timer2b(void);
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WEAK_DEFAULT void isr_comp0(void);
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WEAK_DEFAULT void isr_comp1(void);
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WEAK_DEFAULT void isr_sysctl(void);
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WEAK_DEFAULT void isr_flashctl(void);
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WEAK_DEFAULT void isr_gpio_portf(void);
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WEAK_DEFAULT void isr_uart2(void);
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WEAK_DEFAULT void isr_ssi1(void);
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WEAK_DEFAULT void isr_timer3a(void);
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WEAK_DEFAULT void isr_timer3b(void);
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WEAK_DEFAULT void isr_i2c1(void);
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WEAK_DEFAULT void isr_can0(void);
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WEAK_DEFAULT void isr_hibernate(void);
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WEAK_DEFAULT void isr_usb(void);
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WEAK_DEFAULT void isr_udma_sw(void);
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WEAK_DEFAULT void isr_udma_error(void);
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WEAK_DEFAULT void isr_adc1_seq0(void);
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WEAK_DEFAULT void isr_adc1_seq1(void);
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WEAK_DEFAULT void isr_adc1_seq2(void);
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WEAK_DEFAULT void isr_adc1_seq3(void);
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WEAK_DEFAULT void isr_ssi2(void);
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WEAK_DEFAULT void isr_ssi3(void);
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WEAK_DEFAULT void isr_uart3(void);
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WEAK_DEFAULT void isr_uart4(void);
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WEAK_DEFAULT void isr_uart5(void);
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WEAK_DEFAULT void isr_uart6(void);
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WEAK_DEFAULT void isr_uart7(void);
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WEAK_DEFAULT void isr_i2c2(void);
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WEAK_DEFAULT void isr_i2c4(void);
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WEAK_DEFAULT void isr_timer4a(void);
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WEAK_DEFAULT void isr_timer4b(void);
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WEAK_DEFAULT void isr_timer5a(void);
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WEAK_DEFAULT void isr_timer5b(void);
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WEAK_DEFAULT void isr_wtimer0a(void);
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WEAK_DEFAULT void isr_wtimer0b(void);
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WEAK_DEFAULT void isr_wtimer1a(void);
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WEAK_DEFAULT void isr_wtimer1b(void);
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WEAK_DEFAULT void isr_wtimer2a(void);
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WEAK_DEFAULT void isr_wtimer2b(void);
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WEAK_DEFAULT void isr_wtimer3a(void);
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WEAK_DEFAULT void isr_wtimer3b(void);
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WEAK_DEFAULT void isr_wtimer4a(void);
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WEAK_DEFAULT void isr_wtimer4b(void);
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WEAK_DEFAULT void isr_wtimer5a(void);
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WEAK_DEFAULT void isr_wtimer5b(void);
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WEAK_DEFAULT void isr_sysex(void);
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/* interrupt vector table */
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ISR_VECTORS const void *interrupt_vector[] = {
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/* Exception stack pointer */
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(void*) (&_estack), /* pointer to the top of the stack */
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/* Cortex-M4 handlers */
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(void*) reset_handler_default, /* entry point of the program */
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(void*) nmi_default, /* non maskable interrupt handler */
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(void*) hard_fault_default, /* hard fault exception */
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(void*) mem_manage_default, /* memory manage exception */
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(void*) bus_fault_default, /* bus fault exception */
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(void*) usage_fault_default, /* usage fault exception */
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(void*) (0UL), /* Reserved */
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(void*) (0UL), /* Reserved */
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(void*) (0UL), /* Reserved */
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(void*) (0UL), /* Reserved */
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(void*) isr_svc, /* system call interrupt, in RIOT used for
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* switching into thread context on boot */
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(void*) debug_mon_default, /* debug monitor exception */
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(void*) (0UL), /* Reserved */
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(void*) isr_pendsv, /* pendSV interrupt, in RIOT the actual
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* context switching is happening here */
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(void*) isr_systick, /* SysTick interrupt, not used in RIOT */
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/* Peripherial interrupts start here.*/
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(void *) isr_gpio_porta, // GPIO Port A 16
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(void *) isr_gpio_portb, // GPIO Port B 17
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(void *) isr_gpio_portc, // GPIO Port C 18
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(void *) isr_gpio_portd, // GPIO Port D 19
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(void *) isr_gpio_porte, // GPIO Port E 20
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(void *) isr_uart0, // UART 0 21
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(void *) isr_uart1, // UART 1 22
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(void *) isr_ssi0, // SSI 0 23
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(void *) isr_i2c0, // I2C 0 24
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(void *) (0UL), // Reserved 25
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(void *) (0UL), // Reserved 26
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(void *) (0UL), // Reserved 27
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(void *) (0UL), // Reserved 28
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(void *) (0UL), // Reserved 29
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(void *) isr_adc0_seq0, // ADC 0 Seq 0 30
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(void *) isr_adc0_seq1, // ADC 0 Seq 1 31
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(void *) isr_adc0_seq2, // ADC 0 Seq 2 32
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(void *) isr_adc0_seq3, // ADC 0 Seq 3 33
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(void *) isr_wdt, // WDT 0 and 1 34
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(void *) isr_timer0a, // 16/32 bit timer 0 A 35
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(void *) isr_timer0b, // 16/32 bit timer 0 B 36
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(void *) isr_timer1a, // 16/32 bit timer 1 A 37
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(void *) isr_timer1b, // 16/32 bit timer 1 B 38
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(void *) isr_timer2a, // 16/32 bit timer 2 A 39
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(void *) isr_timer2b, // 16/32 bit timer 2 B 40
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(void *) isr_comp0, // Analog comparator 0 41
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(void *) isr_comp1, // Analog comparator 1 42
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(void *) (0UL), // Reserved 43
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(void *) isr_sysctl, // System control 44
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(void *) isr_flashctl, // Flash + EEPROM control 45
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(void *) isr_gpio_portf, // GPIO Port F 46
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(void *) (0UL), // Reserved 47
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(void *) (0UL), // Reserved 48
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(void *) isr_uart2, // UART 2 49
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(void *) isr_ssi2, // SSI 1 50
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(void *) isr_timer3a, // 16/32 bit timer 3 A 51
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(void *) isr_timer3b, // 16/32 bit timer 3 B 52
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(void *) isr_i2c1, // I2C 1 53
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(void *) (0UL), // Reserved 54
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(void *) isr_can0, // CAN 0 55
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(void *) (0UL), // Reserved 56
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(void *) (0UL), // Reserved 57
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(void *) (0UL), // Reserved 58
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(void *) isr_hibernate, // Hibernation module 59
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(void *) isr_usb, // USB 60
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(void *) (0UL), // Reserved 61
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(void *) isr_udma_sw, // UDMA SW 62
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(void *) isr_udma_error, // UDMA Error 63
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(void *) isr_adc1_seq0, // ADC 1 Seq 0 64
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(void *) isr_adc1_seq1, // ADC 1 Seq 1 65
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(void *) isr_adc1_seq2, // ADC 1 Seq 2 66
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(void *) isr_adc1_seq3, // ADC 1 Seq 3 67
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(void *) (0UL), // Reserved 68
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(void *) (0UL), // Reserved 69
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(void *) (0UL), // Reserved 70
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(void *) (0UL), // Reserved 71
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(void *) (0UL), // Reserved 72
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(void *) isr_ssi2, // SSI 2 73
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(void *) isr_ssi3, // SSI 3 74
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(void *) isr_uart3, // UART 3 75
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(void *) isr_uart4, // UART 4 76
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(void *) isr_uart5, // UART 5 77
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(void *) isr_uart6, // UART 6 78
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(void *) isr_uart7, // UART 7 79
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(void *) (0UL), // Reserved 80
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(void *) (0UL), // Reserved 81
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(void *) (0UL), // Reserved 82
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(void *) (0UL), // Reserved 83
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(void *) isr_i2c2, // I2C 2 84
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(void *) isr_i2c4, // I2C 4 85
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(void *) isr_timer4a, // 16/32 bit timer 4 A 86
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(void *) isr_timer4b, // 16/32 bit timer 4 B 87
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(void *) (0UL), // Reserved 88
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(void *) (0UL), // Reserved 89
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(void *) (0UL), // Reserved 90
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(void *) (0UL), // Reserved 91
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(void *) (0UL), // Reserved 92
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(void *) (0UL), // Reserved 93
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(void *) (0UL), // Reserved 94
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(void *) (0UL), // Reserved 95
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(void *) (0UL), // Reserved 96
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(void *) (0UL), // Reserved 97
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(void *) (0UL), // Reserved 98
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(void *) (0UL), // Reserved 99
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(void *) (0UL), // Reserved 100
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(void *) (0UL), // Reserved 101
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(void *) (0UL), // Reserved 102
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(void *) (0UL), // Reserved 103
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(void *) (0UL), // Reserved 104
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(void *) (0UL), // Reserved 105
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(void *) (0UL), // Reserved 106
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(void *) (0UL), // Reserved 107
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(void *) isr_timer5a, // 16/32 bit timer 5 A 108
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(void *) isr_timer5b, // 16/32 bit timer 5 B 109
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(void *) isr_wtimer0a, // 32/64 bit timer 0 A 110
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(void *) isr_wtimer0b, // 32/64 bit timer 0 B 111
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(void *) isr_wtimer1a, // 32/64 bit timer 1 A 112
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(void *) isr_wtimer1b, // 32/64 bit timer 1 B 113
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(void *) isr_wtimer2a, // 32/64 bit timer 2 A 114
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(void *) isr_wtimer2b, // 32/64 bit timer 2 B 115
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(void *) isr_wtimer3a, // 32/64 bit timer 3 A 116
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(void *) isr_wtimer3b, // 32/64 bit timer 3 B 117
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(void *) isr_wtimer4a, // 32/64 bit timer 4 A 118
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(void *) isr_wtimer4b, // 32/64 bit timer 4 B 119
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(void *) isr_wtimer5a, // 32/64 bit timer 5 A 120
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(void *) isr_wtimer5b, // 32/64 bit timer 5 B 121
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(void *) isr_sysex, // System Exception 122
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(void *) (0UL), // Reserved 123
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(void *) (0UL), // Reserved 124
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(void *) (0UL), // Reserved 125
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(void *) (0UL), // Reserved 126
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(void *) (0UL), // Reserved 127
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(void *) (0UL), // Reserved 128
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(void *) (0UL), // Reserved 129
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(void *) (0UL), // Reserved 130
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(void *) (0UL), // Reserved 131
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(void *) (0UL), // Reserved 132
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(void *) (0UL), // Reserved 133
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(void *) (0UL), // Reserved 134
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(void *) (0UL), // Reserved 135
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(void *) (0UL), // Reserved 136
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(void *) (0UL), // Reserved 137
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(void *) (0UL), // Reserved 138
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(void *) (0UL), // Reserved 139
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(void *) (0UL), // Reserved 140
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(void *) (0UL), // Reserved 141
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(void *) (0UL), // Reserved 142
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(void *) (0UL), // Reserved 143
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(void *) (0UL), // Reserved 144
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(void *) (0UL), // Reserved 145
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(void *) (0UL), // Reserved 146
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(void *) (0UL), // Reserved 147
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(void *) (0UL), // Reserved 148
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(void *) (0UL), // Reserved 149
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(void *) (0UL), // Reserved 150
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(void *) (0UL), // Reserved 151
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(void *) (0UL), // Reserved 152
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(void *) (0UL), // Reserved 153
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(void *) (0UL) // Reserved 154
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};
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/** @} */
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