ae95137f95
This driver is compliant with the candev interface. It has been tested with STM32F0 and STM32F2 and STM32F413 ONLY at this time but should be compliant with other STM32Fx devices
139 lines
3.2 KiB
C
139 lines
3.2 KiB
C
/*
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* Copyright (C) 2016 OTA keys S.A.
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup candev_stm32
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* @{
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*
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* @file
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* @brief STM32 CAN controller driver (bxCAN) default parameters
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*
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* @author Vincent Dupont <vincent@otakeys.com>
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* @}
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*/
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#ifndef CANDEV_STM32_PARAMS_H
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#define CANDEV_STM32_PARAMS_H
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#include "can/device.h"
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#include "periph/can.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Default STM32 CAN devices config */
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static const can_conf_t candev_conf[] = {
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{
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#if defined(CPU_FAM_STM32F0)
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.can = CAN,
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.rcc_mask = RCC_APB1ENR_CANEN,
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.rx_pin = GPIO_PIN(PORT_A, 11),
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.tx_pin = GPIO_PIN(PORT_A, 12),
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.af = GPIO_AF4,
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.irqn = CEC_CAN_IRQn,
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#else
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.can = CAN1,
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.rcc_mask = RCC_APB1ENR_CAN1EN,
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.can_master = CAN1,
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.master_rcc_mask = RCC_APB1ENR_CAN1EN,
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.first_filter = 0,
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.nb_filters = 14,
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#ifndef CPU_FAM_STM32F1
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.rx_pin = GPIO_PIN(PORT_D, 0),
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.tx_pin = GPIO_PIN(PORT_D, 1),
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.af = GPIO_AF9,
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#else
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.rx_pin = GPIO_PIN(PORT_A, 11),
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.tx_pin = GPIO_PIN(PORT_A, 12),
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#endif
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.tx_irqn = CAN1_TX_IRQn,
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.rx0_irqn = CAN1_RX0_IRQn,
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.rx1_irqn = CAN1_RX1_IRQn,
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.sce_irqn = CAN1_SCE_IRQn,
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#endif
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.ttcm = 0,
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.abom = 1,
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.awum = 1,
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.nart = 0,
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.rflm = 0,
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.txfp = 0,
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},
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#if (CANDEV_STM32_CHAN_NUMOF >= 2) && (CAN_DLL_NUMOF >= 2)
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{
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.can = CAN2,
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.rcc_mask = RCC_APB1ENR_CAN2EN,
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.can_master = CAN1,
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.master_rcc_mask = RCC_APB1ENR_CAN1EN,
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.first_filter = 14,
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.nb_filters = 14,
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.rx_pin = GPIO_PIN(PORT_B, 5),
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.tx_pin = GPIO_PIN(PORT_B, 6),
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#ifndef CPU_FAM_STM32F1
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.af = GPIO_AF9,
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#endif
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.tx_irqn = CAN2_TX_IRQn,
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.rx0_irqn = CAN2_RX0_IRQn,
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.rx1_irqn = CAN2_RX1_IRQn,
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.sce_irqn = CAN2_SCE_IRQn,
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.ttcm = 0,
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.abom = 1,
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.awum = 1,
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.nart = 0,
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.rflm = 0,
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.txfp = 0,
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},
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#endif
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#if (CANDEV_STM32_CHAN_NUMOF >= 3) && (CAN_DLL_NUMOF >= 3)
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{
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.can = CAN3,
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.rcc_mask = RCC_APB1ENR_CAN3EN,
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.can_master = CAN3,
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.master_rcc_mask = RCC_APB1ENR_CAN3EN,
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.first_filter = 0,
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.nb_filters = 14,
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.rx_pin = GPIO_PIN(PORT_B, 3),
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.tx_pin = GPIO_PIN(PORT_B, 4),
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.af = GPIO_AF11,
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.tx_irqn = CAN3_TX_IRQn,
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.rx0_irqn = CAN3_RX0_IRQn,
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.rx1_irqn = CAN3_RX1_IRQn,
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.sce_irqn = CAN3_SCE_IRQn,
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.ttcm = 0,
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.abom = 1,
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.awum = 1,
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.nart = 0,
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.rflm = 0,
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.txfp = 0,
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},
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#endif
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};
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/** Default STM32 CAN devices parameters */
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static const candev_params_t candev_params[] = {
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{
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.name = "can_stm32_0",
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},
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#if (CANDEV_STM32_CHAN_NUMOF >= 2) && (CAN_DLL_NUMOF >= 2)
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{
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.name = "can_stm32_1",
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},
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#endif
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#if (CANDEV_STM32_CHAN_NUMOF >= 3) && (CAN_DLL_NUMOF >= 3)
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{
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.name = "can_stm32_2",
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},
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#endif
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* CANDEV_STM32_PARAMS_H */
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