10 lines
242 B
Plaintext
10 lines
242 B
Plaintext
/**
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* @defgroup cpu_fe310 SiFive fe310
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* @ingroup cpu
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* @brief SiFive fe310 RISC-V MCU specific implementation.
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*
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* This module contains SiFive fe310 specific code and definition.
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*
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* @see cpu_riscv_common
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*/
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