e206087d65
drivers/eth-phy: add generic Ethernet PHY iface cpu/stm32f4: implement eth driver peripheral This implements the ethernet (MAC) peripheral of the stm32f4 as a netdev driver. boards/stm32f4discovery: add eth configuration boards/stm32f4discovery: add feature stm32_eth tests/stm32_eth_lwip: add test application
135 lines
4.6 KiB
C
135 lines
4.6 KiB
C
/*
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* Copyright (C) 2016 TriaGnoSys GmbH
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for
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* more details.
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*/
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/**
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* @defgroup ethernet_phy Ethernet PHY
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* @brief Provides a Ethernet PHY abstraction
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* @{
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*
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* @file
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* @brief Definitions for Ethernet PHY devices
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*
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* @author Víctor Ariño <victor.arino@triagnosys.com>
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*/
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#ifndef ETH_PHY_H
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#define ETH_PHY_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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/* Ethernet PHY Common Registers */
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#define PHY_BMCR (0x00)
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#define PHY_BSMR (0x01)
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#define PHY_PHYIDR1 (0x02)
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#define PHY_PHYIDR2 (0x03)
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#define PHY_ANAR (0x04)
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#define PHY_ANLPAR (0x05)
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#define PHY_ANER (0x06)
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#define PHY_ANNPTR (0x07)
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/* Ethernet PHY BMCR Fields */
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#define BMCR_RESET (0x8000)
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#define BMCR_LOOPBACK (0x4000)
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#define BMCR_SPEED_SELECT (0x2000)
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#define BMCR_AN (0x1000)
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#define BMCR_POWER_DOWN (0x0800)
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#define BMCR_ISOLATE (0x0400)
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#define BMCR_RESTART_AN (0x0200)
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#define BMCR_DUPLEX_MODE (0x0100)
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#define BMCR_COLLISION_TEST (0x0080)
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/* Ethernet PHY BSMR Fields */
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#define BSMR_100BASE_T4 (0x8000)
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#define BSMR_100BASE_TX_FDUPLEX (0x4000)
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#define BSMR_100BASE_TX_HDUPLEX (0x2000)
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#define BSMR_10BASE_T_FDUPLEX (0x1000)
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#define BSMR_10BASE_T_HDUPLEX (0x0800)
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#define BSMR_NO_PREAMBLE (0x0040)
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#define BSMR_AN_COMPLETE (0x0020)
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#define BSMR_REMOTE_FAULT (0x0010)
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#define BSMR_AN_ABILITY (0x0008)
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#define BSMR_LINK_STATUS (0x0004)
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#define BSMR_JABBER_DETECT (0x0002)
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#define BSMR_EXTENDED_CAP (0x0001)
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/* Ethernet PHY PHYIDR1 Fields */
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#define PHYIDR1_OUI (0xffff)
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/* Ethernet PHY PHYIDR2 Fields */
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#define PHYIDR2_OUI (0xfe00)
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#define PHYIDR2_MODEL (0x01f0)
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#define PHYIDR2_REV (0x0007)
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/* Ethernet PHY ANAR Fields */
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#define ANAR_NEXT_PAGE (0x8000)
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#define ANAR_REMOTE_FAULT (0x2000)
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#define ANAR_PAUSE (0x0600)
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#define ANAR_100BASE_T4 (0x0200)
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#define ANAR_100BASE_TX_FDUPLEX (0x0100)
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#define ANAR_100BASE_TX_HDUPLEX (0x0080)
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#define ANAR_10BASE_T_FDUPLEX (0x0040)
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#define ANAR_10BASE_T_HDUPLEX (0x0020)
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#define ANAR_SELECTOR (0x000f)
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/* Ethernet PHY ANLPAR Fields */
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#define ANLPAR_NEXT_PAGE (0x8000)
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#define ANLPAR_ACK (0x4000)
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#define ANLPAR_REMOTE_FAULT (0x2000)
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#define ANLPAR_PAUSE (0x0600)
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#define ANLPAR_100BASE_T4 (0x0200)
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#define ANLPAR_100BASE_TX_FDUPLEX (0x0100)
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#define ANLPAR_100BASE_TX_HDUPLEX (0x0080)
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#define ANLPAR_10BASE_T_FDUPLEX (0x0040)
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#define ANLPAR_10BASE_T_HDUPLEX (0x0020)
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#define ANLPAR_SELECTOR (0x000f)
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/* Ethernet PHY ANNPTR Fields */
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#define ANNPTR_NEXT_PAGE (0x8000)
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#define ANNPTR_MSG_PAGE (0x2000)
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#define ANNPTR_ACK2 (0x1000)
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#define ANNPTR_TOGGLE_TX (0x0800)
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#define ANNPTR_CODE (0x03ff)
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/* Ethernet PHY ANER Fields */
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#define ANER_PDF (0x0010)
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#define ANER_LP_NEXT_PAGE_ABLE (0x0008)
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#define ANER_NEXT_PAGE_ABLE (0x0004)
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#define ANER_PAGE_RX (0x0002)
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#define ANER_LP_AN_ABLE (0x0001)
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/**
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* @brief Read a PHY register
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*
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* @param[in] addr address of the PHY to read
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* @param[in] reg register to be read
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*
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* @return value in the register, or <=0 on error
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*/
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int32_t eth_phy_read(uint16_t addr, uint8_t reg);
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/**
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* @brief Write a PHY register
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*
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* @param[in] addr address of the PHY to write
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* @param[in] reg register to be written
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* @param[in] value value to write into the register
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*
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* @return 0 in case of success or <=0 on error
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*/
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int32_t eth_phy_write(uint16_t addr, uint8_t reg, uint16_t value);
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#ifdef __cplusplus
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}
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#endif
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/** @} */
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#endif /* ETH_PHY_H */
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