28c6481266
When waiting for transmission (to CC2420) to be done, we were wrongly waiting for UCBUSY bit to be set, while one should actually wait for that bit to be cleared.
273 lines
7.1 KiB
C
273 lines
7.1 KiB
C
/*
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* driver_cc2420.c - Implementation of the board dependent cc2420 functions
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* for Zolertia Z1.
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* Copyright (C) 2005, 2006, 2007, 2008 by Thomas Hillebrandt and Heiko Will
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* Copyright (C) 2013 Oliver Hahm <oliver.hahm@inria.fr>
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* Copyright (C) 2014 Kévin Roussel <Kevin.Roussel@inria.fr>
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup board_z1
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* @{
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*
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* @file driver_cc2420.c
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* @brief Board specific CC2420 driver HAL for the Zolertia Z1
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*
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* @author Kévin Roussel <Kevin.Roussel@inria.fr>
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*
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* @}
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*/
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#include <stdio.h>
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#include "board.h"
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#include "cpu.h"
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#include "irq.h"
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#include "hwtimer.h"
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#include "crash.h"
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#include "cc2420.h"
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#include "cc2420_arch.h"
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#include "cc2420_spi.h"
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#define ENABLE_DEBUG (1)
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#include "debug.h"
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#define CC2420_RESETn_PIN 0x40 /* RADIO_RESET <-> P4.6 */
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#define CC2420_VREGEN_PIN 0x20 /* RADIO_VREG_EN <-> P4.5 */
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#define CC2420_FIFOP_PIN 0x04
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#define CC2420_GIO0_PIN 0x08
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#define CC2420_GIO1_PIN 0x10
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#define CC2420_SFD_PIN 0x02
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#define CC2420_FIFOP (P1IN & CC2420_FIFOP_PIN) /* FIFOP <-> packet interrupt (P1.2) */
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#define CC2420_GIO0 (P1IN & CC2420_GIO0_PIN) /* FIFO <-> GIO0 - RX data available (P1.3) */
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#define CC2420_GIO1 (P1IN & CC2420_GIO1_PIN) /* CCA <-> GIO1 - clear channel (P1.4) */
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#define CC2420_SFD (P4IN & CC2420_SFD_PIN) /* SFD <-> TBL - start frame delimiter (P4.1) */
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#define CC2420_CS_LOW (P3OUT &= ~0x01) /* RADIO_CS <-> P3.0 */
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#define CC2420_CS_HIGH (P3OUT |= 0x01)
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volatile int abort_count;
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volatile int retry_count = 0;
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void cc2420_reset(void)
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{
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P4OUT |= CC2420_VREGEN_PIN;
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P4OUT &= ~CC2420_RESETn_PIN;
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hwtimer_wait(500);
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P4OUT |= CC2420_RESETn_PIN;
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}
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void cc2420_gio0_enable(void)
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{
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P1IFG &= ~CC2420_GIO0_PIN; /* Clear IFG for GIO0 */
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P1IE |= CC2420_GIO0_PIN; /* Enable interrupt for GIO0 */
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}
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void cc2420_gio0_disable(void)
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{
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P1IE &= ~CC2420_GIO0_PIN; /* Disable interrupt for GIO0 */
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P1IFG &= ~CC2420_GIO0_PIN; /* Clear IFG for GIO0 */
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}
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void cc2420_gio1_enable(void)
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{
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P1IFG &= ~CC2420_GIO1_PIN; /* Clear IFG for GIO1 */
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P1IE |= CC2420_GIO1_PIN; /* Enable interrupt for GIO1 */
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}
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void cc2420_gio1_disable(void)
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{
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P1IE &= ~CC2420_GIO1_PIN; /* Disable interrupt for GIO1 */
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P1IFG &= ~CC2420_GIO1_PIN; /* Clear IFG for GIO1 */
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}
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void cc2420_before_send(void)
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{
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/* Disable SFD interrupt before sending packet */
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/* However there is no interrupt on MSP430F2617 port 4 */
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}
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void cc2420_after_send(void)
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{
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/* Enable SFD interrupt after sending packet */
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/* However there is no interrupt on MSP430F2617 port 4 */
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}
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int cc2420_get_gio0(void)
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{
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return CC2420_GIO0;
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}
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int cc2420_get_gio1(void)
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{
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return CC2420_GIO1;
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}
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uint8_t cc2420_get_fifop(void)
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{
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return CC2420_FIFOP;
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}
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uint8_t cc2420_get_sfd(void)
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{
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return CC2420_SFD;
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}
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#define MAX_RSSI_WAIT 1000
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uint8_t cc2420_get_cca(void)
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{
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uint8_t status;
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long count = 0;
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do {
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unsigned int sr = disableIRQ();
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cc2420_spi_select();
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status = cc2420_txrx(NOBYTE);
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cc2420_spi_unselect();
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restoreIRQ(sr);
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count++;
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if (count >= MAX_RSSI_WAIT) {
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core_panic(0x2420, "cc2420_get_cca(): RSSI never valid!");
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}
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} while (!(status & CC2420_STATUS_RSSI_VALID));
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return CC2420_GIO1;
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}
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void cc2420_spi_cs(void)
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{
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CC2420_CS_LOW; /* Chip Select line is active-low */
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}
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#define MAX_SPI_WAIT 1000
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uint8_t cc2420_txrx(uint8_t data)
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{
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/* Wait for SPI to be ready for transmission */
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long count = 0;
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do {
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count++;
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if (count >= MAX_SPI_WAIT) {
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core_panic(0x2420, "cc2420_txrx(): SPI never ready for TX!");
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}
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} while (!(IFG2 & UCB0TXIFG));
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/* Transmit data byte to CC2420, and wait for end of transmission */
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IFG2 &= ~UCB0RXIFG;
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UCB0TXBUF = data;
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count = 0;
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do {
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count++;
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if (count >= MAX_SPI_WAIT) {
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core_panic(0x2420, "cc2420_txrx(): couldn't send byte!");
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}
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} while (UCB0STAT & UCBUSY);
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/* Read the byte that CC2420 has (normally, during TX) returned */
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count = 0;
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do {
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count++;
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if (count >= MAX_SPI_WAIT) {
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core_panic(0x2420, "cc2420_txrx(): couldn't receive byte!");
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}
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} while (!(IFG2 & UCB0RXIFG));
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/* Return received byte */
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return UCB0RXBUF;
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}
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void cc2420_spi_select(void)
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{
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CC2420_CS_LOW;
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}
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void cc2420_spi_unselect(void) {
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CC2420_CS_HIGH;
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}
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void cc2420_init_interrupts(void)
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{
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unsigned int state = disableIRQ(); /* Disable all interrupts */
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/* done in board.c : function z1_ports_init()
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P1SEL &= ~CC2420_FIFOP_PIN; // must be <> 1 to use interrupts
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P1SEL &= ~CC2420_GIO0_PIN; // must be <> 1 to use interrupts
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*/
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/* FIFO <-> GIO0 interrupt */
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P1IES |= CC2420_GIO0_PIN; /* Enable external interrupt on falling edge for GIO0/FIFO */
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P1IE |= CC2420_GIO0_PIN;
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P1IFG &= ~CC2420_GIO0_PIN; /* Clear the interrupt flag */
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/* FIFOP <-> Packet interrupt */
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P1IES &= ~CC2420_FIFOP_PIN; /* Enable external interrupt on rising edge for FIFOP */
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P1IE |= CC2420_FIFOP_PIN;
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P1IFG &= ~CC2420_FIFOP_PIN; /* Clear IFG for FIFOP */
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restoreIRQ(state); /* Enable all interrupts */
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}
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void cc2420_spi_init(void)
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{
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/*
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* NOTES :
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* - we will use SPI mode using block B of the USCI0,
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* so as to avoid disturbing UART0 which is managed by USCI0 block A
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* - MCU pin (GPIO port) initialisation is done in board.c,
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* function z1_ports_init().
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*/
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/* Keep peripheral in reset state during configuration */
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UCB0CTL1 = UCSWRST;
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/* 8-bit SPI Master 3-pin mode, MSB first,
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with SMCLK as clock source */
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UCB0CTL0 = UCSYNC + UCMST + UCMODE_0 + UCMSB;
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UCB0CTL1 |= UCSSEL_3;
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UCB0CTL0 |= UCCKPH; /* Data captured on rising edge, changed on falling */
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UCB0CTL0 &= ~UCCKPL; /* SPI data lines are active-high/inactive-low */
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/* Ignore clockrate argument for now, just use clock source/2 */
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UCB0BR0 = 0x02; /* Ensure baud rate <= SMCLK/2 */
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UCB0BR1 = 0x00;
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/* Release for operation */
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UCB0CTL1 &= ~UCSWRST;
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}
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/*
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* CC2420 receive interrupt
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*/
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interrupt (PORT1_VECTOR) __attribute__ ((naked)) cc2420_isr(void)
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{
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__enter_isr();
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/* Check if FIFOP signal is raising => RX interrupt */
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if ((P1IFG & CC2420_FIFOP_PIN) != 0) {
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P1IFG &= ~CC2420_FIFOP_PIN;
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cc2420_rx_irq();
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DEBUG("rx interrupt");
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}
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/* GIO0 is falling => check if FIFOP is high, indicating an RXFIFO overflow */
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else if ((P1IFG & CC2420_GIO0_PIN) != 0) {
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P1IFG &= ~CC2420_GIO0_PIN;
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if (cc2420_get_fifop()) {
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cc2420_rxoverflow_irq();
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DEBUG("[CC2420] rxfifo overflow");
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}
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}
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else {
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puts("cc2420_isr(): unexpected IFG!");
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/* Should not occur - only FIFOP and GIO0 interrupts are enabled */
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}
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__exit_isr();
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}
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