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treewide/stm32: Make CLOCK_HS* configurable

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This commit is contained in:
MrKevinWeiss 2022-10-26 11:43:40 +02:00
parent e802203b19
commit 17cce015d4
No known key found for this signature in database
GPG Key ID: 4B69974722CBEEAE
50 changed files with 217 additions and 117 deletions
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4
boards/common/iotlab/Kconfig
View File

@ -27,6 +27,10 @@ config BOARD_COMMON_IOTLAB
select HAVE_L3G4200D
select HAVE_LSM303DLHC
choice CHOICE_CLOCK_HSE
default CLOCK_HSE_16MHZ
endchoice
config MODULE_BOARDS_COMMON_IOTLAB
bool
depends on TEST_KCONFIG

5
boards/common/iotlab/include/periph_conf_common.h
View File

@ -29,7 +29,10 @@
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
#define CLOCK_HSE MHZ(16)
#ifndef CONFIG_CLOCK_HSE
#define CONFIG_CLOCK_HSE MHZ(16)
#endif
#include "periph_cpu.h"
#include "clk_conf.h"

4
boards/common/weact-f4x1cx/Kconfig
View File

@ -28,6 +28,10 @@ config BOARD_COMMON_WEACT_F4X1CX
select HAVE_SAUL_GPIO
select HAVE_MTD_SPI_NOR
choice CHOICE_CLOCK_HSE
default CLOCK_HSE_25MHZ
endchoice
config MODULE_BOARDS_COMMON_WEACT-F4X1CX
bool
depends on TEST_KCONFIG

4
boards/common/weact-f4x1cx/include/periph_conf.h
View File

@ -33,7 +33,9 @@
#endif
/* The HSE provides a 25MHz clock */
#define CLOCK_HSE MHZ(25)
#ifndef CONFIG_CLOCK_HSE
#define CONFIG_CLOCK_HSE MHZ(25)
#endif
#include "clk_conf.h"
#include "cfg_i2c1_pb8_pb9.h"

4
boards/f4vi1/Kconfig
View File

@ -21,6 +21,10 @@ config BOARD_F4VI1
select BOARD_HAS_HSE
select BOARD_HAS_LSE
choice CHOICE_CLOCK_HSE
default CLOCK_HSE_16MHZ
endchoice
config CLOCK_PLL_M
default 16

4
boards/f4vi1/include/periph_conf.h
View File

@ -27,7 +27,9 @@
#endif
/* The HSE provides a 16MHz clock */
#define CLOCK_HSE MHZ(16)
#ifndef CONFIG_CLOCK_HSE
#define CONFIG_CLOCK_HSE MHZ(16)
#endif
#include "periph_cpu.h"
#include "clk_conf.h"

5
boards/im880b/Kconfig
View File

@ -22,6 +22,11 @@ config BOARD_IM880B
select HAS_PERIPH_UART
# Clock configuration
select BOARD_HAS_HSE
select BOARD_HAS_LSE
choice CHOICE_CLOCK_HSE
default CLOCK_HSE_16MHZ
endchoice
source "$(RIOTBOARD)/common/stm32/Kconfig"

4
boards/im880b/include/periph_conf.h
View File

@ -36,7 +36,9 @@
/**
* @brief Speed of the HSE clock in Hz
*/
#define CLOCK_HSE MHZ(16)
#ifndef CONFIG_CLOCK_HSE
#define CONFIG_CLOCK_HSE MHZ(16)
#endif
#include "periph_cpu.h"
#include "clk_conf.h"

4
boards/lora-e5-dev/Kconfig
View File

@ -33,6 +33,10 @@ config BOARD_LORA_E5_DEV
select HAVE_SAUL_GPIO
select HAVE_LM75A
choice CHOICE_CLOCK_HSE
default CLOCK_HSE_32MHZ
endchoice
config LORA_E5_DEV_ENABLE_3P3V
bool "LoRa-E5 Development Kit - Enable 3.3V output"
default y

4
boards/lora-e5-dev/include/periph_conf.h
View File

@ -30,7 +30,9 @@
#define CONFIG_BOARD_HAS_HSE 1
#endif
#define CLOCK_HSE MHZ(32)
#ifndef CONFIG_CLOCK_HSE
#define CONFIG_CLOCK_HSE MHZ(32)
#endif
#include "periph_cpu.h"
#include "clk_conf.h"

4
boards/msbiot/Kconfig
View File

@ -30,6 +30,10 @@ config BOARD_MSBIOT
select HAVE_MPU9150
select HAVE_SAUL_GPIO
choice CHOICE_CLOCK_HSE
default CLOCK_HSE_16MHZ
endchoice
config CLOCK_PLL_M
default 16

4
boards/msbiot/include/periph_conf.h
View File

@ -25,7 +25,9 @@
#endif
/* The HSE provides a 16MHz clock */
#define CLOCK_HSE MHZ(16)
#ifndef CONFIG_CLOCK_HSE
#define CONFIG_CLOCK_HSE MHZ(16)
#endif
#include "periph_cpu.h"
#include "clk_conf.h"

4
boards/nucleo-wl55jc/Kconfig
View File

@ -28,4 +28,8 @@ config BOARD_NUCLEO_WL55JC
select MODULE_PERIPH_LPUART if MODULE_STDIO_UART && HAS_PERIPH_LPUART
choice CHOICE_CLOCK_HSE
default CLOCK_HSE_32MHZ
endchoice
source "$(RIOTBOARD)/common/nucleo64/Kconfig"

4
boards/nucleo-wl55jc/include/periph_conf.h
View File

@ -31,7 +31,9 @@
#define CONFIG_BOARD_HAS_HSE 1
#endif
#define CLOCK_HSE MHZ(32)
#ifndef CONFIG_CLOCK_HSE
#define CONFIG_CLOCK_HSE MHZ(32)
#endif
#include "periph_cpu.h"
#include "clk_conf.h"

4
boards/p-nucleo-wb55/Kconfig
View File

@ -33,4 +33,8 @@ config BOARD_P_NUCLEO_WB55
select BOARD_HAS_HSE
select BOARD_HAS_LSE
choice CHOICE_CLOCK_HSE
default CLOCK_HSE_32MHZ
endchoice
source "$(RIOTBOARD)/common/nucleo/Kconfig"

4
boards/p-nucleo-wb55/include/periph_conf.h
View File

@ -28,7 +28,9 @@
#define CONFIG_BOARD_HAS_HSE 1
#endif
#define CLOCK_HSE MHZ(32)
#ifndef CONFIG_CLOCK_HSE
#define CONFIG_CLOCK_HSE MHZ(32)
#endif
/* EXTAHB (HCLK2) max freq 32 Mhz*/
#define CLOCK_EXTAHB_DIV RCC_EXTCFGR_C2HPRE_3

4
boards/pyboard/Kconfig
View File

@ -31,6 +31,10 @@ config BOARD_PYBOARD
select HAVE_SAUL_GPIO
choice CHOICE_CLOCK_HSE
default CLOCK_HSE_12MHZ
endchoice
config CLOCK_PLL_M
default 12

4
boards/pyboard/include/periph_conf.h
View File

@ -32,7 +32,9 @@
#endif
/* The HSE provides a 12MHz clock */
#define CLOCK_HSE MHZ(12)
#ifndef CONFIG_CLOCK_HSE
#define CONFIG_CLOCK_HSE MHZ(12)
#endif
#include "periph_cpu.h"
#include "clk_conf.h"

4
boards/stm32f469i-disco/Kconfig
View File

@ -27,4 +27,8 @@ config BOARD_STM32F469I_DISCO
select HAVE_SAUL_GPIO
choice CHOICE_CLOCK_HSE
default CLOCK_HSE_8MHZ
endchoice
source "$(RIOTBOARD)/common/stm32/Kconfig"

4
boards/stm32f469i-disco/include/periph_conf.h
View File

@ -28,7 +28,9 @@
#endif
/* The HSE provides a 8MHz clock */
#define CLOCK_HSE MHZ(8)
#ifndef CONFIG_CLOCK_HSE
#define CONFIG_CLOCK_HSE MHZ(8)
#endif
#include "periph_cpu.h"
#include "clk_conf.h"

4
boards/stm32f723e-disco/Kconfig
View File

@ -37,6 +37,10 @@ config BOARD_STM32F723E_DISCO
# Workaround due to stdout only working with stdin enabled
select MODULE_STDIN if TEST_KCONFIG
choice CHOICE_CLOCK_HSE
default CLOCK_HSE_25MHZ
endchoice
config MODULE_PERIPH_INIT_LED0
default n if MODULE_PERIPH_SPI

4
boards/stm32f723e-disco/include/periph_conf.h
View File

@ -30,7 +30,9 @@
#endif
/* The HSE provides a 25MHz clock */
#define CLOCK_HSE MHZ(25)
#ifndef CONFIG_CLOCK_HSE
#define CONFIG_CLOCK_HSE MHZ(25)
#endif
#include "periph_cpu.h"
#include "clk_conf.h"

6
boards/stm32f746g-disco/Kconfig
View File

@ -34,4 +34,10 @@ config BOARD_STM32F746G_DISCO
select HAVE_STM32_ETH
select HAVE_FT5X06
choice CHOICE_CLOCK_HSE
default CLOCK_HSE_25MHZ
endchoice
source "$(RIOTBOARD)/common/stm32/Kconfig"

4
boards/stm32f746g-disco/include/periph_conf.h
View File

@ -30,7 +30,9 @@
#endif
/* The HSE provides a 25MHz clock */
#define CLOCK_HSE MHZ(25)
#ifndef CONFIG_CLOCK_HSE
#define CONFIG_CLOCK_HSE MHZ(25)
#endif
#include <stdint.h>

4
boards/stm32f7508-dk/Kconfig
View File

@ -33,4 +33,8 @@ config BOARD_STM32F7508_DK
select HAVE_SAUL_GPIO
select HAVE_FT5X06
choice CHOICE_CLOCK_HSE
default CLOCK_HSE_25MHZ
endchoice
source "$(RIOTBOARD)/common/stm32/Kconfig"

6
boards/stm32f769i-disco/Kconfig
View File

@ -29,4 +29,10 @@ config BOARD_STM32F769I_DISCO
select HAVE_SAUL_GPIO
choice CHOICE_CLOCK_HSE
default CLOCK_HSE_25MHZ
endchoice
source "$(RIOTBOARD)/common/stm32/Kconfig"

4
boards/stm32f769i-disco/include/periph_conf.h
View File

@ -30,7 +30,9 @@
#endif
/* The HSE provides a 25MHz clock */
#define CLOCK_HSE MHZ(25)
#ifndef CONFIG_CLOCK_HSE
#define CONFIG_CLOCK_HSE MHZ(25)
#endif
#include "periph_cpu.h"
#include "clk_conf.h"

4
boards/ublox-c030-u201/Kconfig
View File

@ -30,4 +30,8 @@ config BOARD_UBLOX_C030_U201
select HAVE_SAUL_GPIO
select MODULE_PERIPH_UART_HW_FC if TEST_KCONFIG && HAS_PERIPH_UART_HW_FC
choice CHOICE_CLOCK_HSE
default CLOCK_HSE_12MHZ
endchoice
source "$(RIOTBOARD)/common/stm32/Kconfig"

4
boards/ublox-c030-u201/include/periph_conf.h
View File

@ -30,7 +30,9 @@
#endif
/* The HSE provides a 12MHz clock */
#define CLOCK_HSE MHZ(12)
#ifndef CONFIG_CLOCK_HSE
#define CONFIG_CLOCK_HSE MHZ(12)
#endif
#include "periph_cpu.h"
#include "clk_conf.h"

4
cpu/stm32/dist/clk_conf/clk_conf.c vendored
View File

@ -454,7 +454,9 @@ int main(int argc, char **argv)
printf("#define CLOCK_CORECLOCK (%uU)\n", coreclock);
printf("/* 0: no external high speed crystal available\n"
" * else: actual crystal frequency [in Hz] */\n"
"#define CLOCK_HSE (%uU)\n", pll_src ? pll_in : 0);
"#ifndef CONFIG_CLOCK_HSE\n"
"#define CONFIG_CLOCK_HSE (%uU)\n", pll_src ? pll_in : 0);
printf("#endif\n");
printf("/* 0: no external low speed crystal available,\n"
" * 1: external crystal available (always 32.768kHz) */\n"
"#define CLOCK_LSE (%uU)\n", is_lse);

2
cpu/stm32/doc.txt
View File

@ -21,7 +21,7 @@ system clock (but only one can be used at a time):
- HSE (High Speed External): HSE depends on the board configuration and its
presence is specified by the `CONFIG_BOARD_HAS_HSE` constant at board level.
The `CLOCK_HSE` constant specifies the frequency of the external oscillator
The `CONFIG_CLOCK_HSE` constant specifies the frequency of the external oscillator
in Hz.
To use HSE as system clock (SYSCLK), set `CONFIG_USE_CLOCK_HSE` constant to 1;

14
cpu/stm32/include/clk/cfg_clock_common_fx_gx_mp1.h
View File

@ -55,22 +55,24 @@ extern "C" {
#error "Cannot use HSI as clock source with other clock configurations"
#endif
#ifndef CLOCK_HSE
#ifndef CONFIG_CLOCK_HSE
#if defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32G4) || \
defined(CPU_FAM_STM32MP1)
#define CLOCK_HSE MHZ(24)
#define CONFIG_CLOCK_HSE MHZ(24)
#else
#define CLOCK_HSE MHZ(8)
#define CONFIG_CLOCK_HSE MHZ(8)
#endif
#endif
#ifndef CONFIG_CLOCK_HSI
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
defined(CPU_FAM_STM32F3)
#define CLOCK_HSI MHZ(8)
#define CONFIG_CLOCK_HSI MHZ(8)
#elif defined(CPU_FAM_STM32MP1)
#define CLOCK_HSI MHZ(64)
#define CONFIG_CLOCK_HSI MHZ(64)
#else
#define CLOCK_HSI MHZ(16)
#define CONFIG_CLOCK_HSI MHZ(16)
#endif
#endif
/** @} */

10
cpu/stm32/include/clk/cfg_clock_common_lx_u5_wx.h
View File

@ -66,15 +66,17 @@ extern "C" {
#error "Cannot use HSI as clock source with other clock configurations"
#endif
#ifndef CLOCK_HSE
#ifndef CONFIG_CLOCK_HSE
#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
#define CLOCK_HSE MHZ(24)
#define CONFIG_CLOCK_HSE MHZ(24)
#else
#define CLOCK_HSE MHZ(8)
#define CONFIG_CLOCK_HSE MHZ(8)
#endif
#endif
#define CLOCK_HSI MHZ(16)
#ifndef CONFIG_CLOCK_HSI
#define CONFIG_CLOCK_HSI MHZ(16)
#endif
#ifndef CONFIG_CLOCK_MSI
#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)

14
cpu/stm32/include/clk/f0f1f3/cfg_clock_default.h
View File

@ -34,7 +34,7 @@ extern "C" {
* @name F0/F1/F3 clock settings
* @{
*/
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(32))
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE < MHZ(4) || CONFIG_CLOCK_HSE > MHZ(32))
#error "HSE clock frequency must be between 4MHz and 32MHz"
#endif
@ -50,7 +50,7 @@ extern "C" {
PLL_MUL to 16, so system clock = (HSI8 / 2) * 16 = 64MHz
*/
#ifndef CONFIG_CLOCK_PLL_PREDIV
#if (IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(16))) || \
#if (IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(16))) || \
defined(CPU_LINE_STM32F303x6) || defined(CPU_LINE_STM32F303x8) || \
defined(CPU_LINE_STM32F303xB) || defined(CPU_LINE_STM32F303xC) || \
defined(CPU_LINE_STM32F328x8) || defined(CPU_LINE_STM32F358xC) || \
@ -77,19 +77,19 @@ extern "C" {
#endif /* CONFIG_CLOCK_PLL_MUL */
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
#define CLOCK_CORECLOCK (CLOCK_HSI)
#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSI)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
#if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#error "The board doesn't provide an HSE oscillator"
#endif
#define CLOCK_CORECLOCK (CLOCK_HSE)
#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSE)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#define CLOCK_PLL_SRC (CLOCK_HSE)
#else /* CLOCK_HSI */
#define CLOCK_PLL_SRC (CLOCK_HSI)
#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSE)
#else /* CONFIG_CLOCK_HSI */
#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSI)
#endif
/* PLL configuration: make sure your values are legit!
*

10
cpu/stm32/include/clk/f2f4f7/cfg_clock_default.h
View File

@ -51,19 +51,19 @@
* @{
*/
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#define CLOCK_PLL_SRC (CLOCK_HSE)
#else /* CLOCK_HSI */
#define CLOCK_PLL_SRC (CLOCK_HSI)
#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSE)
#else /* CONFIG_CLOCK_HSI */
#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSI)
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
#define CLOCK_CORECLOCK (CLOCK_HSI)
#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSI)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
#if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#error "The board doesn't provide an HSE oscillator"
#endif
#define CLOCK_CORECLOCK (CLOCK_HSE)
#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSE)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
#define CLOCK_CORECLOCK (((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_P)

10
cpu/stm32/include/clk/f2f4f7/cfg_clock_default_100.h
View File

@ -37,7 +37,7 @@ extern "C" {
decreased to 96MHZ so the PLLQ can output 48MHz.
*/
#ifndef CONFIG_CLOCK_PLL_M
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25))
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(25))
#define CONFIG_CLOCK_PLL_M (25)
#else
#define CONFIG_CLOCK_PLL_M (4)
@ -45,17 +45,17 @@ extern "C" {
#endif
#ifndef CONFIG_CLOCK_PLL_N
#if IS_USED(MODULE_PERIPH_USBDEV_CLK) && defined(CPU_LINE_STM32F411xE)
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(8))
#define CONFIG_CLOCK_PLL_N (96)
#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25))
#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(25))
#define CONFIG_CLOCK_PLL_N (192)
#else
#define CONFIG_CLOCK_PLL_N (48)
#endif
#else
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(8))
#define CONFIG_CLOCK_PLL_N (100)
#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25))
#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(25))
#define CONFIG_CLOCK_PLL_N (200)
#else
#define CONFIG_CLOCK_PLL_N (50)

2
cpu/stm32/include/clk/f2f4f7/cfg_clock_default_120.h
View File

@ -37,7 +37,7 @@ extern "C" {
#define CONFIG_CLOCK_PLL_M (4)
#endif
#ifndef CONFIG_CLOCK_PLL_N
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(8))
#define CONFIG_CLOCK_PLL_N (120)
#else
#define CONFIG_CLOCK_PLL_N (60)

16
cpu/stm32/include/clk/f2f4f7/cfg_clock_default_180.h
View File

@ -37,9 +37,9 @@ extern "C" {
decreased to 168MHZ so the PLLQ can output 48MHz.
*/
#ifndef CONFIG_CLOCK_PLL_M
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(12))
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(12))
#define CONFIG_CLOCK_PLL_M (12)
#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(16))
#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(16))
#define CONFIG_CLOCK_PLL_M (16)
#else
#define CONFIG_CLOCK_PLL_M (4)
@ -51,19 +51,19 @@ extern "C" {
defined(CPU_LINE_STM32F415xx) || defined(CPU_LINE_STM32F417xx) || \
defined(CPU_LINE_STM32F427xx) || defined(CPU_LINE_STM32F429xx) || \
defined(CPU_LINE_STM32F437xx) || defined(CPU_LINE_STM32F439xx))
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(8))
#define CONFIG_CLOCK_PLL_N (168)
#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(12) || \
(CLOCK_HSE == MHZ(16)))
#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(12) || \
(CONFIG_CLOCK_HSE == MHZ(16)))
#define CONFIG_CLOCK_PLL_N (336)
#else
#define CONFIG_CLOCK_PLL_N (84)
#endif
#else
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(8))
#define CONFIG_CLOCK_PLL_N (180)
#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(12) || \
(CLOCK_HSE == MHZ(16)))
#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(12) || \
(CONFIG_CLOCK_HSE == MHZ(16)))
#define CONFIG_CLOCK_PLL_N (360)
#else
#define CONFIG_CLOCK_PLL_N (90)

6
cpu/stm32/include/clk/f2f4f7/cfg_clock_default_216.h
View File

@ -34,16 +34,16 @@ extern "C" {
/* The following parameters configure a 216MHz system clock with HSE (8MHz,
16MHz or 25MHz) or HSI (16MHz) as PLL input clock */
#ifndef CONFIG_CLOCK_PLL_M
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25))
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(25))
#define CONFIG_CLOCK_PLL_M (25)
#else
#define CONFIG_CLOCK_PLL_M (4)
#endif
#endif
#ifndef CONFIG_CLOCK_PLL_N
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25))
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(25))
#define CONFIG_CLOCK_PLL_N (432)
#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(8))
#define CONFIG_CLOCK_PLL_N (216)
#else
#define CONFIG_CLOCK_PLL_N (108)

6
cpu/stm32/include/clk/f2f4f7/cfg_clock_default_84.h
View File

@ -34,16 +34,16 @@ extern "C" {
/* The following parameters configure a 84MHz system clock with HSE (8MHz, 16MHz
or 25MHz) or HSI (16MHz) as PLL input clock */
#ifndef CONFIG_CLOCK_PLL_M
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25))
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(25))
#define CONFIG_CLOCK_PLL_M (25)
#else
#define CONFIG_CLOCK_PLL_M (4)
#endif
#endif
#ifndef CONFIG_CLOCK_PLL_N
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(8))
#define CONFIG_CLOCK_PLL_N (168)
#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25))
#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(25))
#define CONFIG_CLOCK_PLL_N (336)
#else
#define CONFIG_CLOCK_PLL_N (84)

14
cpu/stm32/include/clk/g0g4/cfg_clock_default.h
View File

@ -32,7 +32,7 @@ extern "C" {
*
* @{
*/
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(48))
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE < MHZ(4) || CONFIG_CLOCK_HSE > MHZ(48))
#error "HSE clock frequency must be between 4MHz and 48MHz"
#endif
@ -43,9 +43,9 @@ extern "C" {
#endif
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#define CLOCK_PLL_SRC (CLOCK_HSE)
#else /* CLOCK_HSI */
#define CLOCK_PLL_SRC (CLOCK_HSI)
#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSE)
#else /* CONFIG_CLOCK_HSI */
#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSI)
#endif
/* The following parameters configure a 64MHz system clock with HSI as input clock */
@ -73,16 +73,16 @@ extern "C" {
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
#ifdef CPU_FAM_STM32G0
#define CLOCK_CORECLOCK (CLOCK_HSI / CONFIG_CLOCK_HSISYS_DIV)
#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSI / CONFIG_CLOCK_HSISYS_DIV)
#else
#define CLOCK_CORECLOCK (CLOCK_HSI)
#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSI)
#endif
#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
#if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#error "The board doesn't provide an HSE oscillator"
#endif
#define CLOCK_CORECLOCK (CLOCK_HSE)
#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSE)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
#define CLOCK_CORECLOCK \

14
cpu/stm32/include/clk/l0l1/cfg_clock_default.h
View File

@ -29,7 +29,7 @@ extern "C" {
* @name L0/L1 clock system configuration
* @{
*/
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE < MHZ(1) || CLOCK_HSE > MHZ(24))
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE < MHZ(1) || CONFIG_CLOCK_HSE > MHZ(24))
#error "HSE clock frequency must be between 1MHz and 24MHz"
#endif
@ -42,25 +42,25 @@ extern "C" {
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
#define CLOCK_CORECLOCK (CLOCK_HSI)
#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSI)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
#if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#error "The board doesn't provide an HSE oscillator"
#endif
#define CLOCK_CORECLOCK (CLOCK_HSE)
#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSE)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_MSI)
#define CLOCK_CORECLOCK (CONFIG_CLOCK_MSI)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#if CLOCK_HSE < MHZ(2)
#if CONFIG_CLOCK_HSE < MHZ(2)
#error "HSE must be greater than 2MHz when used as PLL input clock"
#endif
#define CLOCK_PLL_SRC (CLOCK_HSE)
#else /* CLOCK_HSI */
#define CLOCK_PLL_SRC (CLOCK_HSI)
#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSE)
#else /* CONFIG_CLOCK_HSI */
#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSI)
#endif /* CONFIG_BOARD_HAS_HSE */
/* PLL configuration: make sure your values are legit!
*

18
cpu/stm32/include/clk/l4l5wx/cfg_clock_default.h
View File

@ -29,7 +29,7 @@ extern "C" {
* @name L4/L5/WB clock system configuration
* @{
*/
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(48))
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE < MHZ(4) || CONFIG_CLOCK_HSE > MHZ(48))
#error "HSE clock frequency must be between 4MHz and 48MHz"
#endif
@ -56,23 +56,23 @@ extern "C" {
#if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI)
#define CLOCK_PLL_SRC (CONFIG_CLOCK_MSI)
#elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE)
#define CLOCK_PLL_SRC (CLOCK_HSE)
#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSE)
#else /* CONFIG_CLOCK_PLL_SRC_ */
#define CLOCK_PLL_SRC (CLOCK_HSI)
#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSI)
#endif
#ifndef CONFIG_CLOCK_PLL_M
#if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI)
#define CONFIG_CLOCK_PLL_M (6) /* MSI at 48MHz */
#elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) && (CLOCK_HSE == MHZ(8))
#elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) && (CONFIG_CLOCK_HSE == MHZ(8))
#define CONFIG_CLOCK_PLL_M (1) /* HSE at 8MHz */
#elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) && (CLOCK_HSE == MHZ(32))
#elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) && (CONFIG_CLOCK_HSE == MHZ(32))
#define CONFIG_CLOCK_PLL_M (4) /* HSE at 32MHz */
#else
#define CONFIG_CLOCK_PLL_M (2) /* HSI at 16MHz */
#endif
#endif
#ifndef CONFIG_CLOCK_PLL_N
#if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) && (CLOCK_HSE == MHZ(32))
#if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) && (CONFIG_CLOCK_HSE == MHZ(32))
/* For STM32WL, VCO output frequency ((PLL input clock frequency / PLLM ) x PLLN )
must be between 96 and 344 MHz. PLLN can have values <=127 & >=6 */
#if IS_ACTIVE(CPU_FAM_STM32WL)
@ -81,7 +81,7 @@ extern "C" {
#define CONFIG_CLOCK_PLL_N (16)
#endif /* CPU_FAM_STM32WL */
#elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSI) || \
(IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) && (CLOCK_HSE == MHZ(16)))
(IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) && (CONFIG_CLOCK_HSE == MHZ(16)))
#define CONFIG_CLOCK_PLL_N (32)
#else
#if defined(CPU_LINE_STM32L4A6xx) || defined(CPU_LINE_STM32L4P5xx) || \
@ -105,10 +105,10 @@ extern "C" {
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
#define CLOCK_CORECLOCK (CLOCK_HSI)
#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSI)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
#define CLOCK_CORECLOCK (CLOCK_HSE)
#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSE)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_MSI)
#define CLOCK_CORECLOCK (CONFIG_CLOCK_MSI)

12
cpu/stm32/include/clk/mp1/cfg_clock_default.h
View File

@ -28,7 +28,7 @@
#ifndef CONFIG_CLOCK_PLL_M
#define CONFIG_CLOCK_PLL_M (2)
#endif
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(24))
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(24))
#ifndef CONFIG_CLOCK_PLL_N
#define CONFIG_CLOCK_PLL_N (52)
#endif
@ -75,19 +75,19 @@
* @{
*/
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#define CLOCK_PLL_SRC (CLOCK_HSE)
#else /* CLOCK_HSI */
#define CLOCK_PLL_SRC (CLOCK_HSI)
#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSE)
#else /* CONFIG_CLOCK_HSI */
#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSI)
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
#define CLOCK_CORECLOCK (CLOCK_HSI)
#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSI)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
#if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#error "The board doesn't provide an HSE oscillator"
#endif
#define CLOCK_CORECLOCK (CLOCK_HSE)
#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSE)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
#define CLOCK_CORECLOCK (((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) \

10
cpu/stm32/include/clk/u5/cfg_clock_default.h
View File

@ -27,7 +27,7 @@ extern "C" {
* @name U5 clock system configuration
* @{
*/
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(48))
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE < MHZ(4) || CONFIG_CLOCK_HSE > MHZ(48))
#error "HSE clock frequency must be between 4MHz and 48MHz"
#endif
@ -54,9 +54,9 @@ extern "C" {
#if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI)
#define CLOCK_PLL_SRC (CONFIG_CLOCK_MSI)
#elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE)
#define CLOCK_PLL_SRC (CLOCK_HSE)
#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSE)
#else /* CONFIG_CLOCK_PLL_SRC_ */
#define CLOCK_PLL_SRC (CLOCK_HSI)
#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSI)
#endif
#ifndef CONFIG_CLOCK_PLL_M
#if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI)
@ -76,10 +76,10 @@ extern "C" {
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
#define CLOCK_CORECLOCK (CLOCK_HSI)
#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSI)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
#define CLOCK_CORECLOCK (CLOCK_HSE)
#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSE)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_MSI)
#define CLOCK_CORECLOCK (CONFIG_CLOCK_MSI)

2
cpu/stm32/include/tinyusb_hw_defaults.h
View File

@ -117,7 +117,7 @@ extern "C" {
* If the CMSIS defines that the internal UTMI HS PHY is used, the Synopsys DWC2
* driver needs the definition of the HSE clock value.
*/
#define HSE_VALUE CLOCK_HSE
#define HSE_VALUE CONFIG_CLOCK_HSE
#endif
#ifdef __cplusplus

4
cpu/stm32/periph/uart.c
View File

@ -306,10 +306,10 @@ static inline void uart_init_usart(uart_t uart, uint32_t baudrate)
switch (uart_config[uart].clk_src) {
case RCC_UART35CKSELR_UART35SRC_2: /* HSI */
clk = CLOCK_HSI;
clk = CONFIG_CLOCK_HSI;
break;
case RCC_UART35CKSELR_UART35SRC_4: /* HSE */
clk = CLOCK_HSE;
clk = CONFIG_CLOCK_HSE;
break;
default: /* return */
return;

4
cpu/stm32/stmclk/stmclk_gx.c
View File

@ -59,10 +59,10 @@
#endif
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#define PLL_IN CLOCK_HSE
#define PLL_IN CONFIG_CLOCK_HSE
#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSE
#else
#define PLL_IN CLOCK_HSI
#define PLL_IN CONFIG_CLOCK_HSI
#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSI
#endif

38
dist/tools/doccheck/exclude_patterns vendored
View File

@ -795,7 +795,7 @@ boards/common/iotlab/include/openwsn_defs\.h:[0-9]+: warning: Member PORT_maxRxD
boards/common/iotlab/include/openwsn_defs\.h:[0-9]+: warning: Member PORT_maxTxAckPrepare \(macro definition\) of file openwsn_defs\.h is not documented\.
boards/common/iotlab/include/openwsn_defs\.h:[0-9]+: warning: Member PORT_maxTxDataPrepare \(macro definition\) of file openwsn_defs\.h is not documented\.
boards/common/iotlab/include/periph_conf_common\.h:[0-9]+: warning: Member ADC_NUMOF \(macro definition\) of file periph_conf_common\.h is not documented\.
boards/common/iotlab/include/periph_conf_common\.h:[0-9]+: warning: Member CLOCK_HSE \(macro definition\) of file periph_conf_common\.h is not documented\.
boards/common/iotlab/include/periph_conf_common\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSE \(macro definition\) of file periph_conf_common\.h is not documented\.
boards/common/iotlab/include/periph_conf_common\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_HSE \(macro definition\) of file periph_conf_common\.h is not documented\.
boards/common/iotlab/include/periph_conf_common\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_LSE \(macro definition\) of file periph_conf_common\.h is not documented\.
boards/common/iotlab/include/periph_conf_common\.h:[0-9]+: warning: Member DMA_0_ISR \(macro definition\) of file periph_conf_common\.h is not documented\.
@ -1263,7 +1263,7 @@ boards/common/weact\-f4x1cx/include/board\.h:[0-9]+: warning: Member XTIMER_BACK
boards/common/weact\-f4x1cx/include/board\.h:[0-9]+: warning: Member XTIMER_OVERHEAD \(macro definition\) of file board\.h is not documented\.
boards/common/weact\-f4x1cx/include/board\.h:[0-9]+: warning: Member mtd0 \(variable\) of file board\.h is not documented\.
boards/common/weact\-f4x1cx/include/periph_conf\.h:[0-9]+: warning: Member ADC_NUMOF \(macro definition\) of file periph_conf\.h is not documented\.
boards/common/weact\-f4x1cx/include/periph_conf\.h:[0-9]+: warning: Member CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/common/weact\-f4x1cx/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/common/weact\-f4x1cx/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/common/weact\-f4x1cx/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_LSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/common/weact\-f4x1cx/include/periph_conf\.h:[0-9]+: warning: Member PWM_NUMOF \(macro definition\) of file periph_conf\.h is not documented\.
@ -1389,7 +1389,7 @@ boards/esp32\-wrover\-kit/include/board\.h:[0-9]+: warning: Member LCD_CS \(macr
boards/esp32\-wrover\-kit/include/board\.h:[0-9]+: warning: Member LCD_DC \(macro definition\) of file board\.h is not documented\.
boards/esp32\-wrover\-kit/include/board\.h:[0-9]+: warning: Member LCD_RST \(macro definition\) of file board\.h is not documented\.
boards/f4vi1/include/board\.h:[0-9]+: warning: Member LED_PORT \(macro definition\) of file board\.h is not documented\.
boards/f4vi1/include/periph_conf\.h:[0-9]+: warning: Member CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/f4vi1/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/f4vi1/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/f4vi1/include/periph_conf\.h:[0-9]+: warning: Member TIMER_0_ISR \(macro definition\) of file periph_conf\.h is not documented\.
boards/f4vi1/include/periph_conf\.h:[0-9]+: warning: Member TIMER_1_ISR \(macro definition\) of file periph_conf\.h is not documented\.
@ -1797,7 +1797,7 @@ boards/lobaro\-lorabox/include/periph_conf\.h:[0-9]+: warning: Member uart_confi
boards/lora\-e5\-dev/include/board\.h:[0-9]+: warning: Member FE_CTRL1 \(macro definition\) of file board\.h is not documented\.
boards/lora\-e5\-dev/include/board\.h:[0-9]+: warning: Member FE_CTRL2 \(macro definition\) of file board\.h is not documented\.
boards/lora\-e5\-dev/include/board\.h:[0-9]+: warning: Member SX126X_PARAM_SPI \(macro definition\) of file board\.h is not documented\.
boards/lora\-e5\-dev/include/periph_conf\.h:[0-9]+: warning: Member CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/lora\-e5\-dev/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/lora\-e5\-dev/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/lora\-e5\-dev/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_LSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/lora\-e5\-dev/include/periph_conf\.h:[0-9]+: warning: Member I2C_1_ISR \(macro definition\) of file periph_conf\.h is not documented\.
@ -2068,7 +2068,7 @@ boards/msba2/include/periph_conf\.h:[0-9]+: warning: Member i2c_config\[\] \(var
boards/msba2/include/periph_conf\.h:[0-9]+: warning: Member spi_config\[\] \(variable\) of file periph_conf\.h is not documented\.
boards/msba2/include/periph_conf\.h:[0-9]+: warning: Member uart_config\[\] \(variable\) of file periph_conf\.h is not documented\.
boards/msbiot/include/periph_conf\.h:[0-9]+: warning: Member ADC_NUMOF \(macro definition\) of file periph_conf\.h is not documented\.
boards/msbiot/include/periph_conf\.h:[0-9]+: warning: Member CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/msbiot/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/msbiot/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/msbiot/include/periph_conf\.h:[0-9]+: warning: Member DAC_NUMOF \(macro definition\) of file periph_conf\.h is not documented\.
boards/msbiot/include/periph_conf\.h:[0-9]+: warning: Member DMA_0_ISR \(macro definition\) of file periph_conf\.h is not documented\.
@ -2887,7 +2887,7 @@ boards/nucleo\-wl55jc/include/board\.h:[0-9]+: warning: Member FE_CTRL1 \(macro
boards/nucleo\-wl55jc/include/board\.h:[0-9]+: warning: Member FE_CTRL2 \(macro definition\) of file board\.h is not documented\.
boards/nucleo\-wl55jc/include/board\.h:[0-9]+: warning: Member FE_CTRL3 \(macro definition\) of file board\.h is not documented\.
boards/nucleo\-wl55jc/include/board\.h:[0-9]+: warning: Member SX126X_PARAM_SPI \(macro definition\) of file board\.h is not documented\.
boards/nucleo\-wl55jc/include/periph_conf\.h:[0-9]+: warning: Member CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/nucleo\-wl55jc/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/nucleo\-wl55jc/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/nucleo\-wl55jc/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_LSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/nucleo\-wl55jc/include/periph_conf\.h:[0-9]+: warning: Member I2C_1_ISR \(macro definition\) of file periph_conf\.h is not documented\.
@ -3125,7 +3125,7 @@ boards/p\-nucleo\-wb55/include/arduino_pinmap\.h:[0-9]+: warning: Member ARDUINO
boards/p\-nucleo\-wb55/include/arduino_pinmap\.h:[0-9]+: warning: Member ARDUINO_PIN_A5 \(macro definition\) of file arduino_pinmap\.h is not documented\.
boards/p\-nucleo\-wb55/include/periph_conf\.h:[0-9]+: warning: Member CLOCK_EXTAHB \(macro definition\) of file periph_conf\.h is not documented\.
boards/p\-nucleo\-wb55/include/periph_conf\.h:[0-9]+: warning: Member CLOCK_EXTAHB_DIV \(macro definition\) of file periph_conf\.h is not documented\.
boards/p\-nucleo\-wb55/include/periph_conf\.h:[0-9]+: warning: Member CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/p\-nucleo\-wb55/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/p\-nucleo\-wb55/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/p\-nucleo\-wb55/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_LSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/p\-nucleo\-wb55/include/periph_conf\.h:[0-9]+: warning: Member SPI_NUMOF \(macro definition\) of file periph_conf\.h is not documented\.
@ -3253,7 +3253,7 @@ boards/pinetime/include/periph_conf\.h:[0-9]+: warning: Member I2C_NUMOF \(macro
boards/pinetime/include/periph_conf\.h:[0-9]+: warning: Member SPI_NUMOF \(macro definition\) of file periph_conf\.h is not documented\.
boards/pinetime/include/periph_conf\.h:[0-9]+: warning: Member i2c_config\[\] \(variable\) of file periph_conf\.h is not documented\.
boards/pinetime/include/periph_conf\.h:[0-9]+: warning: Member spi_config\[\] \(variable\) of file periph_conf\.h is not documented\.
boards/pyboard/include/periph_conf\.h:[0-9]+: warning: Member CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/pyboard/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/pyboard/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/pyboard/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_LSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/pyboard/include/periph_conf\.h:[0-9]+: warning: Member DMA_0_ISR \(macro definition\) of file periph_conf\.h is not documented\.
@ -4513,7 +4513,7 @@ boards/stm32f4discovery/include/periph_conf\.h:[0-9]+: warning: Member pwm_confi
boards/stm32f4discovery/include/periph_conf\.h:[0-9]+: warning: Member spi_config\[\] \(variable\) of file periph_conf\.h is not documented\.
boards/stm32f4discovery/include/periph_conf\.h:[0-9]+: warning: Member timer_config\[\] \(variable\) of file periph_conf\.h is not documented\.
boards/stm32f4discovery/include/periph_conf\.h:[0-9]+: warning: Member uart_config\[\] \(variable\) of file periph_conf\.h is not documented\.
boards/stm32f723e\-disco/include/periph_conf\.h:[0-9]+: warning: Member CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/stm32f723e\-disco/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/stm32f723e\-disco/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/stm32f723e\-disco/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_LSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/stm32f723e\-disco/include/periph_conf\.h:[0-9]+: warning: Member I2C_0_ISR \(macro definition\) of file periph_conf\.h is not documented\.
@ -4531,7 +4531,7 @@ boards/stm32f723e\-disco/include/periph_conf\.h:[0-9]+: warning: Member i2c_conf
boards/stm32f723e\-disco/include/periph_conf\.h:[0-9]+: warning: Member spi_config\[\] \(variable\) of file periph_conf\.h is not documented\.
boards/stm32f723e\-disco/include/periph_conf\.h:[0-9]+: warning: Member timer_config\[\] \(variable\) of file periph_conf\.h is not documented\.
boards/stm32f723e\-disco/include/periph_conf\.h:[0-9]+: warning: Member uart_config\[\] \(variable\) of file periph_conf\.h is not documented\.
boards/stm32f769i\-disco/include/periph_conf\.h:[0-9]+: warning: Member CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/stm32f769i\-disco/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/stm32f769i\-disco/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/stm32f769i\-disco/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_LSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/stm32f769i\-disco/include/periph_conf\.h:[0-9]+: warning: Member UART_0_DMA_ISR \(macro definition\) of file periph_conf\.h is not documented\.
@ -4678,7 +4678,7 @@ boards/ublox\-c030\-u201/include/board\.h:[0-9]+: warning: Member SI70XX_SAUL_IN
boards/ublox\-c030\-u201/include/board\.h:[0-9]+: warning: Member UB_M_RST_PIN \(macro definition\) of group boards_ublox\-c030\-u201 is not documented\.
boards/ublox\-c030\-u201/include/board\.h:[0-9]+: warning: Member UB_PWRON_PIN \(macro definition\) of group boards_ublox\-c030\-u201 is not documented\.
boards/ublox\-c030\-u201/include/periph_conf\.h:[0-9]+: warning: Member ADC_NUMOF \(macro definition\) of file periph_conf\.h is not documented\.
boards/ublox\-c030\-u201/include/periph_conf\.h:[0-9]+: warning: Member CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/ublox\-c030\-u201/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/ublox\-c030\-u201/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/ublox\-c030\-u201/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_LSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/ublox\-c030\-u201/include/periph_conf\.h:[0-9]+: warning: Member DMA_0_ISR \(macro definition\) of file periph_conf\.h is not documented\.
@ -6343,11 +6343,11 @@ cpu/stm32/include/candev_stm32\.h:[0-9]+: warning: Member ISR_CAN3_RX0 \(macro d
cpu/stm32/include/candev_stm32\.h:[0-9]+: warning: Member ISR_CAN3_RX1 \(macro definition\) of file candev_stm32\.h is not documented\.
cpu/stm32/include/candev_stm32\.h:[0-9]+: warning: Member ISR_CAN3_SCE \(macro definition\) of file candev_stm32\.h is not documented\.
cpu/stm32/include/candev_stm32\.h:[0-9]+: warning: Member ISR_CAN3_TX \(macro definition\) of file candev_stm32\.h is not documented\.
cpu/stm32/include/clk/cfg_clock_common_fx_gx_mp1\.h:[0-9]+: warning: Member CLOCK_HSE \(macro definition\) of file cfg_clock_common_fx_gx_mp1\.h is not documented\.
cpu/stm32/include/clk/cfg_clock_common_fx_gx_mp1\.h:[0-9]+: warning: Member CLOCK_HSI \(macro definition\) of file cfg_clock_common_fx_gx_mp1\.h is not documented\.
cpu/stm32/include/clk/cfg_clock_common_fx_gx_mp1\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSE \(macro definition\) of file cfg_clock_common_fx_gx_mp1\.h is not documented\.
cpu/stm32/include/clk/cfg_clock_common_fx_gx_mp1\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSI \(macro definition\) of file cfg_clock_common_fx_gx_mp1\.h is not documented\.
cpu/stm32/include/clk/cfg_clock_common_fx_gx_mp1\.h:[0-9]+: warning: Member CONFIG_USE_CLOCK_PLL \(macro definition\) of file cfg_clock_common_fx_gx_mp1\.h is not documented\.
cpu/stm32/include/clk/cfg_clock_common_lx_wx\.h:[0-9]+: warning: Member CLOCK_HSE \(macro definition\) of file cfg_clock_common_lx_wx\.h is not documented\.
cpu/stm32/include/clk/cfg_clock_common_lx_wx\.h:[0-9]+: warning: Member CLOCK_HSI \(macro definition\) of file cfg_clock_common_lx_wx\.h is not documented\.
cpu/stm32/include/clk/cfg_clock_common_lx_wx\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSE \(macro definition\) of file cfg_clock_common_lx_wx\.h is not documented\.
cpu/stm32/include/clk/cfg_clock_common_lx_wx\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSI \(macro definition\) of file cfg_clock_common_lx_wx\.h is not documented\.
cpu/stm32/include/clk/cfg_clock_common_lx_wx\.h:[0-9]+: warning: Member CONFIG_CLOCK_MSI \(macro definition\) of file cfg_clock_common_lx_wx\.h is not documented\.
cpu/stm32/include/clk/cfg_clock_common_lx_wx\.h:[0-9]+: warning: Member CONFIG_USE_CLOCK_PLL \(macro definition\) of file cfg_clock_common_lx_wx\.h is not documented\.
cpu/stm32/include/clk/f0f1f3/cfg_clock_default\.h:[0-9]+: warning: Member CLOCK_AHB \(macro definition\) of file cfg_clock_default\.h is not documented\.
@ -12530,7 +12530,7 @@ boards/nucleo\-g431rb/include/periph_conf\.h:[0-9]+: warning: Member PWM_NUMOF \
boards/nucleo\-g431rb/include/periph_conf\.h:[0-9]+: warning: Member pwm_config\[\] \(variable\) of file periph_conf\.h is not documented\.
boards/stm32f469i\-disco/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_LSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/stm32f469i\-disco/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/stm32f469i\-disco/include/periph_conf\.h:[0-9]+: warning: Member CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/stm32f469i\-disco/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/stm32f469i\-disco/include/periph_conf\.h:[0-9]+: warning: Member DMA_0_ISR \(macro definition\) of file periph_conf\.h is not documented\.
boards/stm32f469i\-disco/include/periph_conf\.h:[0-9]+: warning: Member DMA_1_ISR \(macro definition\) of file periph_conf\.h is not documented\.
boards/stm32f469i\-disco/include/periph_conf\.h:[0-9]+: warning: Member DMA_NUMOF \(macro definition\) of file periph_conf\.h is not documented\.
@ -12551,7 +12551,7 @@ boards/stm32f469i\-disco/include/periph_conf\.h:[0-9]+: warning: Member ADC_NUMO
boards/stm32f469i\-disco/include/periph_conf\.h:[0-9]+: warning: Member adc_config\[\] \(variable\) of file periph_conf\.h is not documented\.
boards/stm32f746g\-disco/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_LSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/stm32f746g\-disco/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/stm32f746g\-disco/include/periph_conf\.h:[0-9]+: warning: Member CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/stm32f746g\-disco/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\.
boards/stm32f746g\-disco/include/periph_conf\.h:[0-9]+: warning: Member DMA_0_ISR \(macro definition\) of file periph_conf\.h is not documented\.
boards/stm32f746g\-disco/include/periph_conf\.h:[0-9]+: warning: Member DMA_1_ISR \(macro definition\) of file periph_conf\.h is not documented\.
boards/stm32f746g\-disco/include/periph_conf\.h:[0-9]+: warning: Member DMA_2_ISR \(macro definition\) of file periph_conf\.h is not documented\.
@ -12617,8 +12617,8 @@ cpu/stm32/include/clk/u5/cfg_clock_default\.h:[0-9]+: warning: Member CONFIG_CLO
cpu/stm32/include/clk/u5/cfg_clock_default\.h:[0-9]+: warning: Member CLOCK_APB1 \(macro definition\) of file cfg_clock_default\.h is not documented\.
cpu/stm32/include/clk/u5/cfg_clock_default\.h:[0-9]+: warning: Member CONFIG_CLOCK_APB2_DIV \(macro definition\) of file cfg_clock_default\.h is not documented\.
cpu/stm32/include/clk/u5/cfg_clock_default\.h:[0-9]+: warning: Member CLOCK_APB2 \(macro definition\) of file cfg_clock_default\.h is not documented\.
cpu/stm32/include/clk/cfg_clock_common_lx_u5_wx\.h:[0-9]+: warning: Member CLOCK_HSE \(macro definition\) of file cfg_clock_common_lx_u5_wx\.h is not documented\.
cpu/stm32/include/clk/cfg_clock_common_lx_u5_wx\.h:[0-9]+: warning: Member CLOCK_HSI \(macro definition\) of file cfg_clock_common_lx_u5_wx\.h is not documented\.
cpu/stm32/include/clk/cfg_clock_common_lx_u5_wx\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSE \(macro definition\) of file cfg_clock_common_lx_u5_wx\.h is not documented\.
cpu/stm32/include/clk/cfg_clock_common_lx_u5_wx\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSI \(macro definition\) of file cfg_clock_common_lx_u5_wx\.h is not documented\.
cpu/stm32/include/clk/cfg_clock_common_lx_u5_wx\.h:[0-9]+: warning: Member CONFIG_CLOCK_MSI \(macro definition\) of file cfg_clock_common_lx_u5_wx\.h is not documented\.
cpu/stm32/include/clk/cfg_clock_common_lx_u5_wx\.h:[0-9]+: warning: Member CONFIG_USE_CLOCK_PLL \(macro definition\) of file cfg_clock_common_lx_u5_wx\.h is not documented\.
drivers/ft5x06/include/ft5x06_params\.h:[0-9]+: warning: Member FT5X06_PARAM_I2C_DEV \(macro definition\) of file ft5x06_params\.h is not documented\.

2
drivers/usbdev_synopsys_dwc2/usbdev_synopsys_dwc2.c
View File

@ -768,7 +768,7 @@ static void _usbdev_init(usbdev_t *dev)
_global_regs(usbdev->config)->GCCFG |= USB_OTG_GCCFG_PHYHSEN;
/* determine the PLL input clock of the USB HS PHY from HSE clock */
switch (CLOCK_HSE) {
switch (CONFIG_CLOCK_HSE) {
case 12000000:
USB_HS_PHYC->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL1_PLLSEL_12MHZ;
break;