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Merge pull request #21261 from gschorcht/cpu/esp32/migration_to_esp-idf.5.4

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cpu/esp32: Migration to ESP-IDF v5.4
This commit is contained in:
Marian Buschsieweke 2025-06-02 06:25:22 +00:00 committed by GitHub
commit 3fa8d0035c
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GPG Key ID: B5690EEEBB952194
228 changed files with 12919 additions and 6851 deletions
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19
boards/common/esp32/include/board_common_esp32.h
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@ -22,8 +22,6 @@
* @{
*/
#include "board_common.h"
/**
* @brief External clock crystal frequency (MHz)
*
@ -39,6 +37,23 @@
#define ESP32_XTAL_FREQ (40)
#endif
#if !DOXYGEN
/**
* @name ztimer Configuration valid for all ESP32 boards
* @{
*/
#if CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ <= 80
# define CONFIG_ZTIMER_USEC_ADJUST_SET (880/CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ)
# define CONFIG_ZTIMER_USEC_ADJUST_SLEEP ((CONFIG_ZTIMER_USEC_ADJUST_SET >> 2) * 5)
#else
# define CONFIG_ZTIMER_USEC_ADJUST_SET (960/CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ)
# define CONFIG_ZTIMER_USEC_ADJUST_SLEEP (CONFIG_ZTIMER_USEC_ADJUST_SET + 1)
#endif
/** @} */
#endif /* !DOXYGEN */
#ifdef __cplusplus
extern "C" {
#endif

45
boards/common/esp32c3/include/board_common_esp32c3.h Normal file
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@ -0,0 +1,45 @@
/*
* Copyright (C) 2025 Gunar Schorcht
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
#pragma once
/**
* @ingroup boards_common_esp32c3
* @brief Board definitions that are common for all ESP32-C3 boards.
*
* This file contains board configurations that are valid for all ESP32-C3.
*
* For detailed information about the configuration of ESP32-C3 boards, see
* section \ref esp32_peripherals "Common Peripherals".
*
* @author Gunar Schorcht <gunar@schorcht.net>
* @file
* @{
*/
#ifdef __cplusplus
extern "C" {
#endif
#if !DOXYGEN
/**
* @name ztimer Configuration valid for all ESP32-C3 boards
* @{
*/
#define CONFIG_ZTIMER_USEC_ADJUST_SET (640/CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ)
#define CONFIG_ZTIMER_USEC_ADJUST_SLEEP (CONFIG_ZTIMER_USEC_ADJUST_SET)
/** @} */
#endif /* !DOXYGEN */
#ifdef __cplusplus
} /* end extern "C" */
#endif
/** @} */

50
boards/common/esp32s2/include/board_common_esp32s2.h Normal file
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@ -0,0 +1,50 @@
/*
* Copyright (C) 2025 Gunar Schorcht
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
#pragma once
/**
* @ingroup boards_common_esp32s2
* @brief Board definitions that are common for all ESP32-S2 boards.
*
* This file contains board configurations that are valid for all ESP32-S2.
*
* For detailed information about the configuration of ESP32-S2 boards, see
* section \ref esp32_peripherals "Common Peripherals".
*
* @author Gunar Schorcht <gunar@schorcht.net>
* @file
* @{
*/
#ifdef __cplusplus
extern "C" {
#endif
#if !DOXYGEN
/**
* @name ztimer Configuration valid for all ESP32-S2 boards
* @{
*/
#if CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ <= 80
# define CONFIG_ZTIMER_USEC_ADJUST_SET (880/CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ)
# define CONFIG_ZTIMER_USEC_ADJUST_SLEEP ((CONFIG_ZTIMER_USEC_ADJUST_SET >> 2) * 5)
#else
# define CONFIG_ZTIMER_USEC_ADJUST_SET (960/CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ)
# define CONFIG_ZTIMER_USEC_ADJUST_SLEEP (CONFIG_ZTIMER_USEC_ADJUST_SET + 1)
#endif
/** @} */
#endif /* !DOXYGEN */
#ifdef __cplusplus
} /* end extern "C" */
#endif
/** @} */

50
boards/common/esp32s3/include/board_common_esp32s3.h Normal file
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@ -0,0 +1,50 @@
/*
* Copyright (C) 2025 Gunar Schorcht
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
#pragma once
/**
* @ingroup boards_common_esp32s3
* @brief Board definitions that are common for all ESP32-S3 boards.
*
* This file contains board configurations that are valid for all ESP32-S3.
*
* For detailed information about the configuration of ESP32-S3 boards, see
* section \ref esp32_peripherals "Common Peripherals".
*
* @author Gunar Schorcht <gunar@schorcht.net>
* @file
* @{
*/
#ifdef __cplusplus
extern "C" {
#endif
#if !DOXYGEN
/**
* @name ztimer Configuration valid for all ESP32-S3 boards
* @{
*/
#if CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ <= 80
# define CONFIG_ZTIMER_USEC_ADJUST_SET (880/CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ)
# define CONFIG_ZTIMER_USEC_ADJUST_SLEEP ((CONFIG_ZTIMER_USEC_ADJUST_SET >> 2) * 5)
#else
# define CONFIG_ZTIMER_USEC_ADJUST_SET (960/CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ)
# define CONFIG_ZTIMER_USEC_ADJUST_SLEEP (CONFIG_ZTIMER_USEC_ADJUST_SET)
#endif
/** @} */
#endif /* !DOXYGEN */
#ifdef __cplusplus
} /* end extern "C" */
#endif
/** @} */

13
boards/common/esp32x/include/board_common.h
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@ -31,8 +31,21 @@
#endif
#include "periph/gpio.h"
#include "sdkconfig.h"
#if defined(CPU_FAM_ESP32)
# include "board_common_esp32.h"
#elif defined(CPU_FAM_ESP32C3)
# include "board_common_esp32c3.h"
#elif defined(CPU_FAM_ESP32S2)
# include "board_common_esp32s2.h"
#elif defined(CPU_FAM_ESP32S3)
# include "board_common_esp32s3.h"
#else
# error "ESP32x SoC family not supported"
#endif
#ifdef __cplusplus
extern "C" {
#endif

4
boards/esp32-heltec-lora32-v2/doc.txt
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@ -216,8 +216,8 @@ purpose. However, if optional off-board hardware modules are used,
these GPIOs may also be occupied,
see section \ref esp32_heltec_lora32_v2_board_configuration for more information.
The corresponding board schematics can be found [here for SX1276 version](https://github.com/Heltec-Aaron-Lee/WiFi_Kit_series/blob/master/SchematicDiagram/WiFi_LoRa_32(V2)/WIFI_LoRa_32_V2(868-915).PDF)
and [here for SX1278 version](https://github.com/Heltec-Aaron-Lee/WiFi_Kit_series/blob/master/SchematicDiagram/WiFi_LoRa_32(V2)/WiFi_LoRa_32_V2(433%2C470-510).PDF).
The corresponding board schematics can be found [here for SX1276 version](https://resource.heltec.cn/download/WiFi_LoRa_32/V2/WIFI_LoRa_32_V2(868-915).PDF)
and [here for SX1278 version](https://resource.heltec.cn/download/WiFi_LoRa_32/V2/WiFi_LoRa_32_V2(433%2C470-510).PDF).
\anchor esp32_heltec_lora_32_v2_pinout_img
@image html "https://gitlab.com/gschorcht/RIOT.wiki-Images/raw/master/esp32/Heltec_WiFi_LoRa_32_V2_pinout_v2.png" "WiFi LoRa 32 V2 Pintout Diagram"

10
boards/esp32s2-devkit/doc.txt
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@ -155,10 +155,10 @@ I2C_DEV(0) SDA | GPIO8 | | \ref esp32_i2c_interfaces "I2C Interfaces"
PWM_DEV(0) | GPIO11, GPIO12, GPIO13, GPIO14 | - | \ref esp32_pwm_channels "PWM Channels"
PWM_DEV(1) | GPIO15, GPIO16 | if module `esp_rtc_timer_32k` is not used | \ref esp32_pwm_channels "PWM Channels"
RGB-LED | GPIO18 | supported by driver module `ws281x` | |
SPI_DEV(0) CLK | GPIO12 | SPI2_HOST (FSPI) is used | \ref esp32_spi_interfaces "SPI Interfaces"
SPI_DEV(0) MISO | GPIO13 | SPI2_HOST (FSPI) is used | \ref esp32_spi_interfaces "SPI Interfaces"
SPI_DEV(0) MOSI | GPIO11 | SPI2_HOST (FSPI) is used | \ref esp32_spi_interfaces "SPI Interfaces"
SPI_DEV(0) CS0 | GPIO10 | SPI2_HOST (FSPI) is used | \ref esp32_spi_interfaces "SPI Interfaces"
SPI_DEV(0) CLK | GPIO36 | SPI2_HOST (FSPI) is used | \ref esp32_spi_interfaces "SPI Interfaces"
SPI_DEV(0) MISO | GPIO37 | SPI2_HOST (FSPI) is used | \ref esp32_spi_interfaces "SPI Interfaces"
SPI_DEV(0) MOSI | GPIO35 | SPI2_HOST (FSPI) is used | \ref esp32_spi_interfaces "SPI Interfaces"
SPI_DEV(0) CS0 | GPIO34 | SPI2_HOST (FSPI) is used | \ref esp32_spi_interfaces "SPI Interfaces"
UART_DEV(0) TxD | GPIO43 | Console (configuration is fixed) | \ref esp32_uart_interfaces "UART interfaces"
UART_DEV(0) RxD | GPIO44 | Console (configuration is fixed) | \ref esp32_uart_interfaces "UART interfaces"
</center>
@ -175,7 +175,7 @@ The following figures show the pinouts as configured by default board
definition.
@image html "https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s2/_images/esp32-s2-devkitm-1-v1-pin-layout.png" "ESP32-S2-DevKitM-1x Pinout" width=900px
@image html "https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s2/_images/esp32-s2-devkitm-1-v1-pin-layout.png" "ESP32-S2-DevKitC-1x Pinout" width=900px
@image html "https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s2/_images/esp32-s2-devkitc-1-v1-pinout.png" "ESP32-S2-DevKitC-1x Pinout" width=900px
@image html "https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s2/_images/esp32-s2_saola1-pinout.jpg" "ESP32-S2-Saola-1x Pinout" width=900px
The corresponding board schematics can be found:

2
cpu/esp32/Kconfig.esp32c3
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@ -69,7 +69,7 @@ menu "ESP32-C3 specific configurations"
config ESP32C3_DEFAULT_CPU_FREQ_MHZ_2
bool "2 MHz"
config ESP32C3_DEFAULT_CPU_FREQ_MHZ_5
bool "50 MHz"
bool "5 MHz"
config ESP32C3_DEFAULT_CPU_FREQ_MHZ_10
bool "10 MHz"
config ESP32C3_DEFAULT_CPU_FREQ_MHZ_20

1
cpu/esp32/Makefile
View File

@ -7,7 +7,6 @@ SRC = irq_arch.c startup.c stdatomic.c syscalls.c
DIRS += $(RIOTCPU)/esp_common
DIRS += periph
DIRS += esp-idf
DIRS += esp-idf-api
ifneq (, $(filter esp_bootloader, $(USEMODULE)))
DIRS += bootloader

31
cpu/esp32/Makefile.dep
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@ -4,7 +4,6 @@ include $(RIOTCPU)/esp_common/Makefile.dep
USEPKG += esp32_sdk
USEMODULE += esp_idf_api
USEMODULE += esp_idf_common
USEMODULE += esp_idf_efuse
USEMODULE += esp_bootloader
@ -21,6 +20,8 @@ ifneq (,$(filter esp_ble,$(USEMODULE)))
# add additional modules and packages used for any BLE interface
FEATURES_REQUIRED += esp_ble
USEMODULE += esp_idf_ble
USEMODULE += esp_idf_nvs_flash
USEMODULE += esp_idf_phy
USEPKG += esp32_sdk_lib_phy
ifeq (esp32,$(CPU_FAM))
FEATURES_REQUIRED += esp_ble_esp32
@ -36,20 +37,19 @@ ifneq (,$(filter esp_eth,$(USEMODULE)))
USEMODULE += esp_idf_eth
USEMODULE += esp_idf_event
USEMODULE += esp_idf_gpio
USEMODULE += esp_idf_spi_flash
USEMODULE += netdev_eth
USEMODULE += netopt
USEMODULE += ztimer_msec
endif
ifneq (,$(filter esp_wifi_any,$(USEMODULE)))
# add additional modules and packages used for any WiFi interface
USEPKG += esp32_sdk_lib_coexist
USEPKG += esp32_sdk_lib_phy
USEPKG += esp32_sdk_lib_wifi
USEMODULE += esp_idf_event
USEMODULE += esp_idf_heap
USEMODULE += esp_idf_nvs_flash
USEMODULE += esp_idf_spi_flash
USEMODULE += esp_idf_phy
USEMODULE += esp_idf_wifi
USEMODULE += esp_idf_wpa_supplicant
USEMODULE += esp_idf_wpa_supplicant_esp_supplicant
@ -70,9 +70,12 @@ ifneq (,$(filter esp_hw_counter,$(USEMODULE)))
endif
ifneq (,$(filter esp_idf_nvs_flash,$(USEMODULE)))
# NVS flash uses MBed TLS for encryption
USEPKG += mbedtls
USEMODULE += mbedtls_contrib
# add additional modules required by esp_idf_nvs_flash
USEMODULE += esp_idf_spi_flash
USEMODULE += pthread
USEMODULE += mtd
endif
ifneq (,$(filter esp_idf_wifi,$(USEMODULE)))
@ -115,7 +118,6 @@ ifneq (,$(filter esp_spi_ram,$(USEMODULE)))
FEATURES_OPTIONAL += esp_spi_oct
USEMODULE += esp_idf_gpio
USEMODULE += esp_idf_heap
USEMODULE += esp_idf_spi_flash
USEMODULE += esp_idf_spi_ram
endif
@ -124,13 +126,12 @@ ifneq (,$(filter esp_spi_oct,$(FEATURES_USED)))
endif
ifneq (,$(filter esp_idf_heap,$(USEMODULE)))
# The ESP-IDF heap component uses the TLSF implementation that is part of
# the component. To avoid conflicts with modules and packages that use the
# RIOT package `tlsf`, this package is also used for the ESP-IDF heap instead
# of its own implementation. There does not seem to be any differences in
# the implementations of TLSF with the exception of heap poisoning, which
# is not configured.
USEPKG += tlsf
# ESP-IDF heap component uses its own and modified TLSF implementation
USEPKG += esp32_sdk_tlsf
endif
ifneq (,$(filter esp_jtag,$(USEMODULE)))
FEATURES_REQUIRED += esp_jtag
endif
ifneq (,$(filter lcd_parallel_ll_mcu,$(USEMODULE)))
@ -192,10 +193,6 @@ ifneq (,$(filter tinyusb_portable_espressif,$(USEMODULE)))
USEMODULE += esp_idf_usb
endif
ifneq (,$(filter esp_jtag,$(USEMODULE)))
FEATURES_REQUIRED += esp_jtag
endif
# enable bootloader reset over USB, requires CDC ACM to be used
ifneq (,$(filter usbus_cdc_acm tinyusb_class_cdc,$(USEMODULE)))
USEMODULE += usb_board_reset

88
cpu/esp32/Makefile.include
View File

@ -111,6 +111,7 @@ PSEUDOMODULES += esp_bootloader
PSEUDOMODULES += esp_gdbstub
PSEUDOMODULES += esp_hw_counter
PSEUDOMODULES += esp_idf_gpio_hal
PSEUDOMODULES += esp_idf_phy
PSEUDOMODULES += esp_i2c_hw
PSEUDOMODULES += esp_jtag
PSEUDOMODULES += esp_lcd_gpio
@ -126,13 +127,19 @@ INCLUDES += -I$(RIOTCPU)/$(CPU)/vendor/include
INCLUDES += -I$(ESP32_SDK_DIR)/components
INCLUDES += -I$(ESP32_SDK_DIR)/components/bootloader_support/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/driver/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/driver/deprecated
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_adc/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_adc/$(CPU_FAM)/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_common/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_driver_gpio/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_driver_uart/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_hw_support/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_hw_support/include/soc
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_hw_support/port/$(CPU_FAM)/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_rom/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_rom/include/$(CPU_FAM)
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/include/$(CPU_FAM)
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_system/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_system/port/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_timer/include
@ -144,7 +151,9 @@ INCLUDES += -I$(ESP32_SDK_DIR)/components/log/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/newlib/platform_include
INCLUDES += -I$(ESP32_SDK_DIR)/components/soc/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/soc/$(CPU_FAM)/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/soc/$(CPU_FAM)/register
INCLUDES += -I$(ESP32_SDK_DIR)/components/spi_flash/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/spi_flash/include/spi_flash
ifneq (,$(filter riscv32%,$(TARGET_ARCH)))
INCLUDES += -I$(ESP32_SDK_DIR)/components/riscv/include
@ -156,7 +165,11 @@ ifneq (,$(filter xtensa%,$(TARGET_ARCH)))
endif
ifneq (,$(filter esp_ble,$(USEMODULE)))
INCLUDES += -I$(ESP32_SDK_DIR)/components/bt/include/$(CPU_FAM)/include
ifeq (esp32,$(CPU_FAM))
INCLUDES += -I$(ESP32_SDK_DIR)/components/bt/include/$(CPU_FAM)/include
else ifneq (,$(filter esp32s3 esp32c3,$(CPU_FAM)))
INCLUDES += -I$(ESP32_SDK_DIR)/components/bt/include/esp32c3/include
endif
endif
ifneq (,$(filter esp_ble_nimble,$(USEMODULE)))
@ -164,12 +177,25 @@ ifneq (,$(filter esp_ble_nimble,$(USEMODULE)))
INCLUDES += $(NIMIBASE)/nimble/transport/common/hci_h4/include
endif
ifneq (,$(filter esp_i2c_hw,$(USEMODULE)))
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_driver_i2c/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_pm/include
endif
ifneq (,$(filter esp_spi_ram,$(USEMODULE)))
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_hw_support/include/soc/$(CPU_FAM)
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_psram/include
endif
ifneq (,$(filter esp_idf_lcd,$(USEMODULE)))
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_driver_i2c/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_driver_spi/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_lcd/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_lcd/priv_include
endif
ifneq (,$(filter esp_idf_nvs_flash,$(USEMODULE)))
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_partition/include
CFLAGS += -DMBEDTLS_CIPHER_MODE_XTS
endif
ifneq (,$(filter esp_idf_spi_flash,$(USEMODULE)))
@ -187,7 +213,6 @@ ifneq (,$(filter esp_wifi_any,$(USEMODULE)))
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_netif/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_wifi/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/nvs_flash/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/spi_flash/include
endif
ifneq (,$(filter esp_wifi_enterprise,$(USEMODULE)))
@ -202,14 +227,26 @@ ifneq (,$(filter esp_eth,$(USEMODULE)))
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_wifi/include
endif
ifneq (,$(filter periph_sdmmc,$(USEMODULE)))
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_driver_sdmmc/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/sdmmc/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_hw_support/dma/include
endif
ifneq (,$(filter ws281x_esp32_hw,$(USEMODULE)))
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_driver_rmt/include
CFLAGS += -DCONFIG_RMT_SUPPRESS_DEPRECATE_WARN
endif
CFLAGS += -DCPU_FAM_$(call uppercase_and_underscore,$(CPU_FAM))
# we use ESP32 only in single core mode
# we use ESP32x SoC only in single core mode
CFLAGS += -DCONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
CFLAGS += -DCONFIG_FREERTOS_UNICORE
# other ESP-IDF configurations
CFLAGS += -DCONFIG_IDF_TARGET_$(call uppercase_and_underscore,$(CPU_FAM))
CFLAGS += -DCONFIG_IDF_TARGET=\"$(CPU_FAM)\"
CFLAGS += -DESP_PLATFORM
CFLAGS += -DLOG_TAG_IN_BRACKETS
@ -246,7 +283,9 @@ CFLAGS += -D_CONST=const
# TODO no relaxation yet
ifneq (,$(filter riscv%,$(TARGET_ARCH)))
CFLAGS += -DCONFIG_IDF_TARGET_ARCH_RISCV
CFLAGS += -mno-relax -march=rv32imc_zicsr_zifencei -mabi=ilp32 -DRISCV_NO_RELAX
LDGENFLAGS += -DCONFIG_IDF_TARGET_ARCH_RISCV
LINKFLAGS += -mno-relax -march=rv32imc_zicsr_zifencei -mabi=ilp32
GCC_NEW_RISCV_ISA ?= $(shell echo "typedef int dont_be_pedantic;" | \
$(TARGET_ARCH)-gcc -march=rv32imac -mabi=ilp32 \
@ -258,6 +297,8 @@ ifneq (,$(filter riscv%,$(TARGET_ARCH)))
endif
ifneq (,$(filter xtensa%,$(TARGET_ARCH)))
CFLAGS += -DCONFIG_IDF_TARGET_ARCH_XTENSA
LDGENFLAGS += -DCONFIG_IDF_TARGET_ARCH_XTENSA
LINKFLAGS += -L$(ESP32_SDK_DIR)/components/xtensa/$(CPU_FAM)
ARCHIVES += -lxt_hal
endif
@ -272,13 +313,25 @@ LINKFLAGS += -T$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/ld/$(CPU_FAM).rom.
LINKFLAGS += -T$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/ld/$(CPU_FAM).rom.api.ld
LINKFLAGS += -T$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/ld/$(CPU_FAM).rom.libgcc.ld
ifeq (esp32s2,$(CPU_FAM))
LINKFLAGS += -T$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/ld/$(CPU_FAM).rom.spiflash.ld
ifeq (esp32,$(CPU_FAM))
# We don't use newlibc functions in ROM for ESP32
# LINKFLAGS += -T$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/ld/$(CPU_FAM).rom.newlib-data.ld
# LINKFLAGS += -T$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/ld/$(CPU_FAM).rom.newlib-funcs.lds
else ifeq (esp32s2,$(CPU_FAM))
# We don't use newlibc functions in ROM for ESP32-S2
# LINKFLAGS += -T$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/ld/$(CPU_FAM).rom.newlib-data.ld
# LINKFLAGS += -T$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/ld/$(CPU_FAM).rom.newlib-funcs.ld
LINKFLAGS += -T$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/ld/$(CPU_FAM).rom.spiflash_legacy.ld
else ifeq (esp32s3,$(CPU_FAM))
LINKFLAGS += -T$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/ld/$(CPU_FAM).rom.ble_cca.ld
LINKFLAGS += -T$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/ld/$(CPU_FAM).rom.bt_funcs.ld
LINKFLAGS += -T$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/ld/$(CPU_FAM).rom.newlib.ld
else ifeq (esp32c3,$(CPU_FAM))
LINKFLAGS += -T$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/ld/$(CPU_FAM).rom.ble_cca.ld
LINKFLAGS += -T$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/ld/$(CPU_FAM).rom.bt_funcs.ld
LINKFLAGS += -T$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/ld/$(CPU_FAM).rom.newlib.ld
LINKFLAGS += -T$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/ld/$(CPU_FAM).rom.eco3.ld
else ifeq (esp32s3,$(CPU_FAM))
LINKFLAGS += -T$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/ld/$(CPU_FAM).rom.newlib.ld
LINKFLAGS += -T$(ESP32_SDK_DIR)/components/riscv/ld/rom.api.ld
endif
LINKFLAGS += -nostdlib -lgcc -Wl,-gc-sections
@ -293,6 +346,7 @@ endif
ifneq (,$(filter esp_wifi_any,$(USEMODULE)))
LINKFLAGS += -L$(ESP32_SDK_LIB_WIFI_DIR)/$(CPU_FAM)
LINKFLAGS += -L$(ESP32_SDK_LIB_PHY_DIR)/$(CPU_FAM)
LINKFLAGS += -L$(ESP32_SDK_LIB_COEXIST_DIR)/$(CPU_FAM)
ARCHIVES += -lcoexist -lcore -lmesh -lnet80211 -lpp
ARCHIVES += -lphy -lstdc++
ifeq (esp32,$(CPU_FAM))
@ -342,13 +396,17 @@ ifneq (,$(filter esp_jtag,$(USEMODULE)))
endif
LD_SCRIPTS += $(BINDIR)/memory.ld $(BINDIR)/sections.ld
LDGENFLAGS += -DLD_FILE_GEN
LDGENFLAGS += -DRESERVE_RTC_MEM=0x18
LDGENFLAGS += -DESP_BOOTLOADER_RESERVE_RTC=0x18
$(BINDIR)/memory.ld: $(RIOTCPU)/$(CPU)/ld/$(CPU_FAM)/memory.ld.in \
$(BINDIR)/memory.ld: $(RIOTCPU)/$(CPU)/vendor/ld/$(CPU_FAM)/memory.ld.in \
$(BINDIR)/riotbuild/riotbuild.h pkg-prepare
$(Q)$(CC) -DLD_FILE_GEN $(INCLUDES) -include '$(BINDIR)/riotbuild/riotbuild.h' \
-I$(RIOTCPU)/$(CPU)/ld -P -x c -E $< -o $@
$(BINDIR)/sections.ld: $(RIOTCPU)/$(CPU)/ld/$(CPU_FAM)/sections.ld.in \
$(Q)$(CC) $(INCLUDES) -include '$(BINDIR)/riotbuild/riotbuild.h' \
$(LDGENFLAGS) -I$(RIOTCPU)/$(CPU)/vendor/ld -P -x c -E $< -o $@
$(BINDIR)/sections.ld: $(RIOTCPU)/$(CPU)/vendor/ld/$(CPU_FAM)/sections.ld.in \
$(BINDIR)/riotbuild/riotbuild.h pkg-prepare
$(Q)$(CC) -DLD_FILE_GEN -include '$(BINDIR)/riotbuild/riotbuild.h' -C -P -x c -E $< -o $@
$(Q)$(CC) $(INCLUDES) -include '$(BINDIR)/riotbuild/riotbuild.h' \
$(LDGENFLAGS) -I$(RIOTCPU)/$(CPU)/vendor/ld -C -P -x c -E $< -o $@
$(BOOTLOADER_BIN):

235
cpu/esp32/bootloader/Makefile
View File

@ -18,15 +18,16 @@ BOOTLOADER_BAUD ?= $(BAUD)
ESP_SDK_BOOTLOADER_SRCS = \
components/bootloader/subproject/main/bootloader_start.c \
components/bootloader/subproject/components/micro-ecc/uECC_verify_antifault.c \
components/bootloader_support/bootloader_flash/src/bootloader_flash.c \
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_$(CPU_FAM).c \
components/bootloader_support/bootloader_flash/src/flash_qio_mode.c \
components/bootloader_support/src/bootloader_clock_init.c \
components/bootloader_support/src/bootloader_clock_loader.c \
components/bootloader_support/src/bootloader_common.c \
components/bootloader_support/src/bootloader_common_loader.c \
components/bootloader_support/src/bootloader_console.c \
components/bootloader_support/src/bootloader_console_loader.c \
components/bootloader_support/src/bootloader_efuse_$(CPU_FAM).c \
components/bootloader_support/src/bootloader_flash.c \
components/bootloader_support/src/bootloader_flash_config_$(CPU_FAM).c \
components/bootloader_support/src/bootloader_efuse.c \
components/bootloader_support/src/bootloader_init.c \
components/bootloader_support/src/bootloader_mem.c \
components/bootloader_support/src/bootloader_panic.c \
@ -39,7 +40,6 @@ ESP_SDK_BOOTLOADER_SRCS = \
components/bootloader_support/src/esp_image_format.c \
components/bootloader_support/src/flash_encrypt.c \
components/bootloader_support/src/flash_partitions.c \
components/bootloader_support/src/flash_qio_mode.c \
components/bootloader_support/src/secure_boot.c \
components/efuse/$(CPU_FAM)/esp_efuse_fields.c \
components/efuse/$(CPU_FAM)/esp_efuse_table.c \
@ -47,82 +47,131 @@ ESP_SDK_BOOTLOADER_SRCS = \
components/efuse/src/esp_efuse_api.c \
components/efuse/src/esp_efuse_fields.c \
components/efuse/src/esp_efuse_utility.c \
components/esp_bootloader_format/esp_bootloader_desc.c \
components/esp_common/src/esp_err_to_name.c \
components/esp_hw_support/compare_set.c \
components/esp_hw_support/cpu_util.c \
components/esp_hw_support/cpu.c \
components/esp_hw_support/esp_memory_utils.c \
components/esp_hw_support/port/$(CPU_FAM)/chip_info.c \
components/esp_hw_support/port/$(CPU_FAM)/cpu_region_protect.c \
components/esp_hw_support/port/$(CPU_FAM)/esp_cpu_intr.c \
components/esp_hw_support/port/$(CPU_FAM)/rtc_clk.c \
components/esp_hw_support/port/$(CPU_FAM)/rtc_clk_init.c \
components/esp_hw_support/port/$(CPU_FAM)/rtc_init.c \
components/esp_hw_support/port/$(CPU_FAM)/rtc_pm.c \
components/esp_hw_support/port/$(CPU_FAM)/rtc_sleep.c \
components/esp_hw_support/port/$(CPU_FAM)/rtc_time.c \
components/esp_rom/patches/esp_rom_crc.c \
components/esp_rom/patches/esp_rom_efuse.c \
components/esp_rom/patches/esp_rom_gpio.c \
components/esp_rom/patches/esp_rom_print.c \
components/esp_rom/patches/esp_rom_spiflash.c \
components/esp_rom/patches/esp_rom_sys.c \
components/esp_rom/patches/esp_rom_tjpgd.c \
components/esp_rom/patches/esp_rom_uart.c \
components/esp_system/esp_err.c \
components/hal/cpu_hal.c \
components/hal/mpu_hal.c \
components/hal/wdt_hal_iram.c \
components/log/log_buffers.c \
components/log/log.c \
components/log/log_noos.c \
components/newlib/syscalls.c \
components/hal/efuse_hal.c \
components/hal/$(CPU_FAM)/efuse_hal.c \
components/hal/hal_utils.c \
components/hal/mmu_hal.c \
components/log/src/log_timestamp_common.c \
components/log/src/noos/log_lock.c \
components/log/src/noos/log_timestamp.c \
components/soc/dport_access_common.c \
components/soc/$(CPU_FAM)/adc_periph.c \
components/soc/$(CPU_FAM)/gpio_periph.c \
components/soc/$(CPU_FAM)/i2c_periph.c \
components/soc/$(CPU_FAM)/i2s_periph.c \
components/soc/$(CPU_FAM)/interrupts.c \
components/soc/$(CPU_FAM)/ledc_periph.c \
components/soc/$(CPU_FAM)/mpi_periph.c \
components/soc/$(CPU_FAM)/rmt_periph.c \
components/soc/$(CPU_FAM)/sigmadelta_periph.c \
components/soc/$(CPU_FAM)/sdm_periph.c \
components/soc/$(CPU_FAM)/spi_periph.c \
components/soc/$(CPU_FAM)/timer_periph.c \
components/soc/$(CPU_FAM)/twai_periph.c \
components/soc/$(CPU_FAM)/uart_periph.c \
components/soc/$(CPU_FAM)/wdt_periph.c \
components/soc/lldesc.c \
components/spi_flash/$(CPU_FAM)/spi_flash_rom_patch.c \
components/spi_flash/spi_flash_wrap.c \
#
ifneq (,$(filter xtensa%,$(TARGET_ARCH)))
ESP_SDK_BOOTLOADER_SRCS += components/esp_hw_support/port/$(CPU_FAM)/rtc_wdt.c
ESP_SDK_BOOTLOADER_SRCS += components/soc/$(CPU_FAM)/lcd_periph.c
ESP_SDK_BOOTLOADER_SRCS += components/soc/$(CPU_FAM)/pcnt_periph.c
ESP_SDK_BOOTLOADER_SRCS += components/soc/$(CPU_FAM)/rtc_io_periph.c
ESP_SDK_BOOTLOADER_SRCS += components/soc/$(CPU_FAM)/touch_sensor_periph.c
ESP_SDK_BOOTLOADER_ASMSRC = components/esp_rom/patches/esp_rom_longjmp.S
ESP_SDK_BOOTLOADER_SRCS += components/xtensa/eri.c
ESP_SDK_BOOTLOADER_SRCS += components/xtensa/xt_trax.c
else
ESP_SDK_BOOTLOADER_SRCS += components/esp_hw_support/port/$(CPU_FAM)/cpu_util_$(CPU_FAM).c
endif
ifneq (,$(filter esp32 esp32s2,$(CPU_FAM)))
ESP_SDK_BOOTLOADER_SRCS += components/soc/$(CPU_FAM)/dac_periph.c
endif
ifneq (,$(filter esp32 esp32s3,$(CPU_FAM)))
ESP_SDK_BOOTLOADER_SRCS += components/soc/$(CPU_FAM)/mcpwm_periph.c
ESP_SDK_BOOTLOADER_SRCS += components/soc/$(CPU_FAM)/sdio_slave_periph.c
ESP_SDK_BOOTLOADER_SRCS += components/soc/$(CPU_FAM)/sdmmc_periph.c
endif
ifneq (,$(filter esp32c3 esp32h2 esp32s3,$(CPU_FAM)))
ESP_SDK_BOOTLOADER_SRCS += components/efuse/$(CPU_FAM)/esp_efuse_rtc_calib.c
endif
ifneq (,$(filter esp32,$(CPU_FAM)))
ESP_SDK_BOOTLOADER_SRCS += components/efuse/src/esp_efuse_api_key_esp32.c
ESP_SDK_BOOTLOADER_ASMSRC = components/esp_rom/patches/esp_rom_longjmp.S
ESP_SDK_BOOTLOADER_SRCS += \
components/efuse/src/efuse_controller/keys/without_key_purposes/three_key_blocks/esp_efuse_api_key.c \
components/hal/$(CPU_FAM)/cache_hal_$(CPU_FAM).c \
components/hal/mpu_hal.c \
components/hal/wdt_hal_iram.c \
components/soc/$(CPU_FAM)/dac_periph.c \
components/soc/$(CPU_FAM)/dport_access.c \
components/soc/$(CPU_FAM)/emac_periph.c \
components/soc/$(CPU_FAM)/lcd_periph.c \
components/soc/$(CPU_FAM)/mcpwm_periph.c \
components/soc/$(CPU_FAM)/pcnt_periph.c \
components/soc/$(CPU_FAM)/rtc_io_periph.c \
components/soc/$(CPU_FAM)/sdio_slave_periph.c \
components/soc/$(CPU_FAM)/sdmmc_periph.c \
components/soc/$(CPU_FAM)/touch_sensor_periph.c \
#
else ifneq (,$(filter esp32s2,$(CPU_FAM)))
ESP_SDK_BOOTLOADER_SRCS += components/efuse/src/esp_efuse_api_key_esp32xx.c
ESP_SDK_BOOTLOADER_SRCS += components/esp_hw_support/port/$(CPU_FAM)/regi2c_ctrl.c
ESP_SDK_BOOTLOADER_SRCS += components/soc/$(CPU_FAM)/dedic_gpio_periph.c
ESP_SDK_BOOTLOADER_SRCS += components/soc/soc_include_legacy_warn.c
ESP_SDK_BOOTLOADER_SRCS += \
components/efuse/$(CPU_FAM)/esp_efuse_rtc_calib.c \
components/efuse/$(CPU_FAM)/esp_efuse_rtc_table.c \
components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c \
components/esp_rom/$(CPU_FAM)/usb_patches.c \
components/esp_rom/patches/esp_rom_cache_esp32s2_esp32s3.c \
components/esp_rom/patches/esp_rom_regi2c_$(CPU_FAM).c \
components/hal/cache_hal.c \
components/hal/mpu_hal.c \
components/hal/wdt_hal_iram.c \
components/esp_rom/patches/esp_rom_systimer.c \
components/soc/$(CPU_FAM)/dedic_gpio_periph.c \
components/soc/$(CPU_FAM)/lcd_periph.c \
components/soc/$(CPU_FAM)/pcnt_periph.c \
components/soc/$(CPU_FAM)/rtc_io_periph.c \
components/soc/$(CPU_FAM)/temperature_sensor_periph.c \
components/soc/$(CPU_FAM)/touch_sensor_periph.c \
components/soc/$(CPU_FAM)/usb_dwc_periph.c \
#
else ifneq (,$(filter esp32s3,$(CPU_FAM)))
ESP_SDK_BOOTLOADER_ASMSRC += \
components/esp_rom/patches/esp_rom_cache_writeback_$(CPU_FAM).S
ESP_SDK_BOOTLOADER_SRCS += \
components/efuse/$(CPU_FAM)/esp_efuse_rtc_calib.c \
components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c \
components/esp_rom/patches/esp_rom_cache_esp32s2_esp32s3.c \
components/esp_rom/patches/esp_rom_systimer.c \
components/esp_rom/patches/esp_rom_wdt.c \
components/hal/cache_hal.c \
components/hal/mpu_hal.c \
components/soc/$(CPU_FAM)/dedic_gpio_periph.c \
components/soc/$(CPU_FAM)/gdma_periph.c \
components/soc/$(CPU_FAM)/lcd_periph.c \
components/soc/$(CPU_FAM)/mcpwm_periph.c \
components/soc/$(CPU_FAM)/pcnt_periph.c \
components/soc/$(CPU_FAM)/rtc_io_periph.c \
components/soc/$(CPU_FAM)/sdmmc_periph.c \
components/soc/$(CPU_FAM)/temperature_sensor_periph.c \
components/soc/$(CPU_FAM)/touch_sensor_periph.c \
components/soc/$(CPU_FAM)/usb_dwc_periph.c \
#
else ifneq (,$(filter esp32c3,$(CPU_FAM)))
ESP_SDK_BOOTLOADER_SRCS += \
components/efuse/$(CPU_FAM)/esp_efuse_rtc_calib.c \
components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c \
components/esp_rom/patches/esp_rom_systimer.c \
components/hal/cache_hal.c \
components/hal/wdt_hal_iram.c \
components/soc/$(CPU_FAM)/dedic_gpio_periph.c \
components/soc/$(CPU_FAM)/gdma_periph.c \
components/soc/$(CPU_FAM)/temperature_sensor_periph.c \
#
else
ESP_SDK_BOOTLOADER_SRCS += components/efuse/src/esp_efuse_api_key_esp32xx.c
ESP_SDK_BOOTLOADER_SRCS += components/soc/$(CPU_FAM)/dedic_gpio_periph.c
ESP_SDK_BOOTLOADER_SRCS += components/soc/$(CPU_FAM)/gdma_periph.c
ESP_SDK_BOOTLOADER_SRCS += components/soc/soc_include_legacy_warn.c
$(error Missing make configuration for ESP32x SoC variant (family): $(CPU_FAM))
endif
# Bootloader sdkconfig.h defined in CURDIR directory.
@ -134,18 +183,25 @@ INCLUDES = \
-I$(ESP32_SDK_DIR)/components/bootloader/subproject/components/micro-ecc/micro-ecc \
-I$(ESP32_SDK_DIR)/components/bootloader_support/bootloader_flash/include \
-I$(ESP32_SDK_DIR)/components/bootloader_support/include \
-I$(ESP32_SDK_DIR)/components/bootloader_support/include_bootloader \
-I$(ESP32_SDK_DIR)/components/bootloader_support/private_include \
-I$(ESP32_SDK_DIR)/components/efuse/include \
-I$(ESP32_SDK_DIR)/components/efuse/private_include \
-I$(ESP32_SDK_DIR)/components/efuse/$(CPU_FAM)/include \
-I$(ESP32_SDK_DIR)/components/efuse/$(CPU_FAM)/private_include \
-I$(ESP32_SDK_DIR)/components/esp_app_format/include \
-I$(ESP32_SDK_DIR)/components/esp_bootloader_format/include \
-I$(ESP32_SDK_DIR)/components/esp_common/include \
-I$(ESP32_SDK_DIR)/components/esp_hw_support/include \
-I$(ESP32_SDK_DIR)/components/esp_hw_support/include/esp_private \
-I$(ESP32_SDK_DIR)/components/esp_hw_support/include/soc \
-I$(ESP32_SDK_DIR)/components/esp_hw_support/include/soc/$(CPU_FAM) \
-I$(ESP32_SDK_DIR)/components/esp_hw_support/port/include \
-I$(ESP32_SDK_DIR)/components/esp_hw_support/port/$(CPU_FAM) \
-I$(ESP32_SDK_DIR)/components/esp_hw_support/port/$(CPU_FAM)/include/ \
-I$(ESP32_SDK_DIR)/components/esp_hw_support/port/$(CPU_FAM)/private_include \
-I$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM) \
-I$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/include \
-I$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/include/$(CPU_FAM) \
-I$(ESP32_SDK_DIR)/components/esp_rom/include \
-I$(ESP32_SDK_DIR)/components/esp_rom/include/$(CPU_FAM) \
-I$(ESP32_SDK_DIR)/components/hal/$(CPU_FAM)/include \
@ -153,8 +209,9 @@ INCLUDES = \
-I$(ESP32_SDK_DIR)/components/hal/platform_port/include \
-I$(ESP32_SDK_DIR)/components/log/include \
-I$(ESP32_SDK_DIR)/components/newlib/platform_include \
-I$(ESP32_SDK_DIR)/components/soc/$(CPU_FAM)/. \
-I$(ESP32_SDK_DIR)/components/soc/$(CPU_FAM) \
-I$(ESP32_SDK_DIR)/components/soc/$(CPU_FAM)/include \
-I$(ESP32_SDK_DIR)/components/soc/$(CPU_FAM)/register \
-I$(ESP32_SDK_DIR)/components/soc/include \
-I$(ESP32_SDK_DIR)/components/spi_flash/include \
-I$(ESP32_SDK_DIR)/components/spi_flash/include/spi_flash \
@ -171,10 +228,9 @@ CFLAGS += -Wno-format
ifneq (,$(filter riscv32%,$(TARGET_ARCH)))
INCLUDES += -I$(ESP32_SDK_DIR)/components/riscv/include
CFLAGS += -DCONFIG_IDF_TARGET_ARCH_RISCV
CFLAGS += -march=rv32imc
CFLAGS += -march=rv32imc_zicsr_zifencei
CFLAGS += -Wno-error=format=
CFLAGS += -nostartfiles
CFLAGS += -Wno-format
GCC_NEW_RISCV_ISA ?= $(shell echo "typedef int dont_be_pedantic;" | \
$(TARGET_ARCH)-gcc -march=rv32imac -mabi=ilp32 \
-misa-spec=2.2 -E - > /dev/null 2>&1 && \
@ -187,53 +243,88 @@ endif
ifneq (,$(filter xtensa%,$(TARGET_ARCH)))
INCLUDES += -I$(ESP32_SDK_DIR)/components/xtensa/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/xtensa/$(CPU_FAM)/include
CFLAGS += -mlongcalls -mtext-section-literals
CFLAGS += -DCONFIG_IDF_TARGET_ARCH_XTENSA
CFLAGS += -mlongcalls
CFLAGS += -mtext-section-literals
CFLAGS += -fno-builtin-memcpy
CFLAGS += -fno-builtin-memset
CFLAGS += -fno-builtin-bzero
CFLAGS += -fno-builtin-stpcpy
CFLAGS += -fno-builtin-strncpy
endif
ifneq (,$(filter esp32,$(CPU_FAM)))
CFLAGS += -Wno-frame-address
endif
# BOOTLOADER_BUILD=1 signals to the SDK that's a bootloader build.
CFLAGS += \
-Wno-frame-address \
-ffunction-sections \
-fdata-sections \
-Wall \
-Wextra \
-Werror=all \
-Wno-error=deprecated-declarations \
-Wno-error=unused-but-set-variable \
-Wno-error=unused-function \
-Wno-error=unused-variable \
-Wno-error=deprecated-declarations \
-Wextra \
-Wno-unused-parameter \
-Wno-old-style-declaration \
-Wno-sign-compare \
-ggdb \
-Os \
-freorder-blocks \
-fstrict-volatile-bitfields \
-Wno-error=unused-but-set-variable \
-Wno-unused-parameter \
-fdata-sections \
-ffunction-sections \
-fdiagnostics-color=always \
-fno-jump-tables \
-fno-tree-switch-conversion \
-fno-stack-protector \
-freorder-blocks \
-fstrict-volatile-bitfields \
-ggdb \
-Os \
-std=gnu99 \
-Wno-old-style-declaration \
-D_GNU_SOURCE \
-DESP_PLATFORM \
-DBOOTLOADER_BUILD=1 \
-DNON_OS_BUILD=1 \
-DSOC_MMU_PAGE_SIZE=CONFIG_MMU_PAGE_SIZE \
-DSOC_XTAL_FREQ_MHZ=CONFIG_XTAL_FREQ \
-D_GLIBCXX_HAVE_POSIX_SEMAPHORE \
-D_GLIBCXX_USE_POSIX_SEMAPHORE \
-DRIOT_BOOTLOADER_BAUD=$(BOOTLOADER_BAUD) \
-DRIOT_FLASH_SIZE=$(FLASH_SIZE) \
-DWITH_POSIX \
-DHAVE_CONFIG_H \
-MD \
-MT \
#
ifneq (,$(filter xtensa%,$(TARGET_ARCH)))
LINKFLAGS = -mlongcalls
LINKFLAGS += -mlongcalls
ESP_SDK_BOOTLOADER_ADD_LINK_FLAGS += -L$(ESP32_SDK_DIR)/components/xtensa/$(CPU_FAM) -lxt_hal
endif
ifneq (,$(filter esp32 esp32s2,$(CPU_FAM)))
LINKFLAGS =
ifneq (,$(filter esp32,$(CPU_FAM)))
ESP_SDK_BOOTLOADER_ADD_LINK_FLAGS += \
-T$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/ld/$(CPU_FAM).rom.newlib-funcs.ld \
-T$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/ld/$(CPU_FAM).rom.spiflash.ld \
#
else ifneq (,$(filter esp32s2,$(CPU_FAM)))
ESP_SDK_BOOTLOADER_ADD_LINK_FLAGS += \
-T$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/ld/$(CPU_FAM).rom.newlib-funcs.ld \
-T$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/ld/$(CPU_FAM).rom.spiflash_legacy.ld \
#
else ifneq (,$(filter esp32s3,$(CPU_FAM)))
ESP_SDK_BOOTLOADER_ADD_LINK_FLAGS += \
-T$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/ld/$(CPU_FAM).rom.newlib.ld \
-T$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/ld/$(CPU_FAM).rom.wdt.ld \
-T$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/ld/$(CPU_FAM).rom.version.ld \
-T$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/ld/$(CPU_FAM).rom.bt_funcs.ld \
#
else ifneq (,$(filter esp32c3,$(CPU_FAM)))
LINKFLAGS += -nostartfiles
LINKFLAGS += --specs=nosys.specs
ESP_SDK_BOOTLOADER_ADD_LINK_FLAGS += \
-T$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/ld/$(CPU_FAM).rom.newlib.ld \
-T$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/ld/$(CPU_FAM).rom.version.ld \
-T$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/ld/$(CPU_FAM).rom.bt_funcs.ld \
-T$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/ld/$(CPU_FAM).rom.eco3.ld \
-T$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/ld/$(CPU_FAM).rom.eco3_bt_funcs.ld \
#
endif
@ -255,7 +346,6 @@ LINKFLAGS += \
$(ESP_SDK_BOOTLOADER_OBJS) \
$(ESP_SDK_BOOTLOADER_ADDOBJS) \
$(ESP_SDK_BOOTLOADER_ASMOBJS) \
-Lgcc \
$(ESP_SDK_BOOTLOADER_ADD_LINK_FLAGS) \
-T$(ESP32_SDK_DIR)/components/bootloader/subproject/main/ld/$(CPU_FAM)/bootloader.ld \
-T$(ESP32_SDK_DIR)/components/bootloader/subproject/main/ld/$(CPU_FAM)/bootloader.rom.ld \
@ -265,6 +355,7 @@ LINKFLAGS += \
-T$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)/ld/$(CPU_FAM).rom.libgcc.ld \
-Wl,--end-group \
-Wl,-EL \
#
# Build the bootloader on the application directory as it depends on the current
# app settings from riotbuild.h.
@ -278,7 +369,6 @@ ESP_SDK_BOOTLOADER_ELF = $(ESP_SDK_BOOTLOADER_DIR)/bootloader.elf
ESP_SDK_BOOTLOADER_OBJ_FILTER = \
components/bootloader/subproject/components/micro-ecc/uECC_verify_antifault.o \
components/bootloader_support/src/secure_boot.o \
components/bootloader_support/src/flash_encrypt.o \
#
ESP_SDK_BOOTLOADER_OBJS = \
@ -310,7 +400,8 @@ $(ESP_SDK_BOOTLOADER_DIR)/%.o: $(ESP32_SDK_DIR)/%.c $(OBJ_DEPS)
$(ESP_SDK_BOOTLOADER_ASMOBJS): \
$(ESP_SDK_BOOTLOADER_DIR)/%.o: $(ESP32_SDK_DIR)/%.S
$(Q)mkdir -p $(dir $@)
$(Q)$(AS) $(ASFLAGS) -o $@ $(abspath $<)
$(Q)$(CCACHE) $(CC) \
$(CFLAGS) $(INCLUDES) -MMD -MP -c $(abspath $<) -o $@
$(ESP_SDK_BOOTLOADER_ADDOBJS): \
$(ESP_SDK_BOOTLOADER_DIR)/%.o: $(CURDIR)/stub.c $(OBJ_DEPS)

10
cpu/esp32/bootloader/sdkconfig.h
View File

@ -1,5 +1,6 @@
/*
* Copyright (C) 2021 iosabi
* Copyright (C) 2024 Gunar Schorcht
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
@ -24,6 +25,7 @@
* bootloader.
*
* @author iosabi <iosabi@protonmail.com>
* @author Gunar Schorcht <gunar@schorcht.net>
*/
#ifndef DOXYGEN
@ -48,8 +50,10 @@
extern "C" {
#endif
#define CONFIG_BOOTLOADER_PROJECT_VER 1
#if MODULE_ESP_LOG_COLORED
#define CONFIG_LOG_COLORS 1
# define CONFIG_BOOTLOADER_LOG_COLORS 1
#endif
#ifndef CONFIG_BOOTLOADER_LOG_LEVEL
@ -104,6 +108,10 @@ extern "C" {
#define CONFIG_ESP_CONSOLE_UART_NUM 0
#endif
#define CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM CONFIG_ESP_CONSOLE_UART_NUM
#define CONFIG_LOG_TAG_LEVEL_IMPL_CACHE_AND_LINKED_LIST 1
#ifdef __cplusplus
}
#endif

1
cpu/esp32/bootloader/sdkconfig_default_common.h
View File

@ -25,7 +25,6 @@ extern "C" {
#endif
#define CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE 1
#define CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V 1
#define CONFIG_BOOTLOADER_WDT_ENABLE 1
#define CONFIG_BOOTLOADER_WDT_TIME_MS 9000
#define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x0

19
cpu/esp32/bootloader/sdkconfig_default_esp32.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2022 Gunar Schorcht
* Copyright (C) 2024 Gunar Schorcht
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
@ -24,17 +24,26 @@
extern "C" {
#endif
#ifndef CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 160
#ifndef CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 160
#endif
#define CONFIG_ESP32_DEBUG_OCDAWARE 1
#define CONFIG_ESP32_XTAL_FREQ 0
#define CONFIG_XTAL_FREQ 40
#define CONFIG_ESP_DEBUG_OCDAWARE 1
#define CONFIG_BOOTLOADER_OFFSET_IN_FLASH 0x1000
#define CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V 1
#define CONFIG_EFUSE_CODE_SCHEME_COMPAT_3_4 1
#define CONFIG_EFUSE_MAX_BLK_LEN 192
#define CONFIG_IDF_FIRMWARE_CHIP_ID 0x0000
#define CONFIG_MMU_PAGE_SIZE 0x10000
#define CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 1
#define CONFIG_ESP_INT_WDT 1
#define CONFIG_ESP_INT_WDT_TIMEOUT_MS 300
#define CONFIG_ESP_INT_WDT_CHECK_CPU 1
#ifdef __cplusplus
}

12
cpu/esp32/bootloader/sdkconfig_default_esp32c3.h
View File

@ -24,16 +24,20 @@
extern "C" {
#endif
#ifndef CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ
#define CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ 160
#define CONFIG_ESP32C3_REV_MIN 3
#ifndef CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 160
#endif
#define CONFIG_ESP32C3_DEBUG_OCDAWARE 1
#define CONFIG_ESP32C3_REV_MIN 3
#define CONFIG_XTAL_FREQ 40
#define CONFIG_ESP_DEBUG_OCDAWARE 1
#define CONFIG_BOOTLOADER_OFFSET_IN_FLASH 0x0
#define CONFIG_EFUSE_MAX_BLK_LEN 256
#define CONFIG_IDF_FIRMWARE_CHIP_ID 0x0005
#define CONFIG_MMU_PAGE_SIZE 0x10000
#define CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG 1

10
cpu/esp32/bootloader/sdkconfig_default_esp32s2.h
View File

@ -24,15 +24,19 @@
extern "C" {
#endif
#ifndef CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ
#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ 160
#ifndef CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 160
#endif
#define CONFIG_ESP32S2_DEBUG_OCDAWARE 1
#define CONFIG_XTAL_FREQ 40
#define CONFIG_ESP_DEBUG_OCDAWARE 1
#define CONFIG_BOOTLOADER_OFFSET_IN_FLASH 0x1000
#define CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V 1
#define CONFIG_EFUSE_MAX_BLK_LEN 256
#define CONFIG_IDF_FIRMWARE_CHIP_ID 0x0002
#define CONFIG_MMU_PAGE_SIZE 0x10000
#ifdef __cplusplus
}

10
cpu/esp32/bootloader/sdkconfig_default_esp32s3.h
View File

@ -24,15 +24,19 @@
extern "C" {
#endif
#ifndef CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ
#define CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ 160
#ifndef CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 160
#endif
#define CONFIG_ESP32S3_DEBUG_OCDAWARE 1
#define CONFIG_XTAL_FREQ 40
#define CONFIG_ESP_DEBUG_OCDAWARE 1
#define CONFIG_BOOTLOADER_OFFSET_IN_FLASH 0x0
#define CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V 1
#define CONFIG_EFUSE_MAX_BLK_LEN 256
#define CONFIG_IDF_FIRMWARE_CHIP_ID 0x0009
#define CONFIG_MMU_PAGE_SIZE 0x10000
#define CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG 1

34
cpu/esp32/doc.txt
View File

@ -818,19 +818,6 @@ Attenuation | Voltage Range | Symbol
@note The reference voltage Vref can vary from device to device in the range
of 1.0V and 1.2V.
The Vref of a device can be read at a predefined GPIO with the function
#adc_line_vref_to_gpio. The results of the ADC input can then be adjusted
accordingly.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~{.c}
extern int adc_line_vref_to_gpio(adc_t line, gpio_t gpio);
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
For the GPIO that can be used with this function, see:
- \ref esp32_adc_channels_esp32 "ESP32"
- \ref esp32_adc_channels_esp32c3 "ESP32-C3"
- \ref esp32_adc_channels_esp32s2 "ESP32-S2"
- \ref esp32_adc_channels_esp32s3 "ESP32-S3"
@note ADC2 is also used by the WiFi module. The GPIOs connected to ADC2 are
therefore not available as ADC channels if the modules `esp_wifi` or
`esp_now` are used.
@ -1405,15 +1392,14 @@ _Light-sleep_ and the _Deep-sleep_ mode:
Parameter | Default | Mode | Description
:----------------|:-------------------------|:------|:------------
ESP_PM_GPIO_HOLD | not defined | Deep | Hold GPIO output level if defined
ESP_PM_WUP_PINS | none | Deep | GPIOs used as wake-up source
ESP_PM_WUP_LEVEL | ESP_PM_WUP_PINS_ANY_HIGH | Deep | Level for wake-up pins to wake-up
ESP_PM_GPIO_HOLD | not defined | Deep | Hold GPIO output level in _Deep-sleep_ mode if defined
ESP_PM_WUP_PINS | none | Deep | GPIOs used as wake-up source from _Deep-sleep_ mode
ESP_PM_WUP_LEVEL | ESP_PM_WUP_PINS_ANY_HIGH | Deep | Level for wake-up pins to wake-up from _Deep-sleep_ mode
ESP_PM_WUP_UART0 | disabled | Light | Positive UART0 RxD signal edges to wake-up
ESP_PM_WUP_UART1 | disabled | Light | Positive UART1 RxD signal edges to wake-up
</center><br>
@note
- If `ESP_PM_GPIO_HOLD` is defined, GPIOs hold their last output level
when entering _Deep-sleep_ mode. Please note that only RTC GPIOs
can hold their output value in _Deep-sleep_ mode.
@ -1431,10 +1417,9 @@ ESP_PM_WUP_UART1 | disabled | Light | Positive UART1 RxD signal
- `ESP_PM_WUP_PINS_ANY_HIGH` (default) - The system is woken up when any of
the GPIOs specified in `ESP_PM_WUP_PINS` becomes HIGH.
- `ESP_PM_WUP_PINS_ANY_LOW` - The system is woken up when any of
the GPIOs specified in `ESP_PM_WUP_PINS` becomes LOW
(only available with the ESP32-C3 variant).
the GPIOs specified in `ESP_PM_WUP_PINS` becomes LOW.
- `ESP_PM_WUP_PINS_ALL_LOW` - The system is woken up when all GPIOs specified
in `ESP_PM_WUP_PINS` become LOW (not available with the ESP32-C3 variant).
in `ESP_PM_WUP_PINS` become LOW.
- `ESP_PM_WUP_UART0` and `ESP_PM_WUP_UART1` define the number of positive
edges of the RxD signal of the respective UART that are necessary to wake
up the system in the _Light-sleep_ mode. The value must be greater than 2,
@ -1442,6 +1427,15 @@ ESP_PM_WUP_UART1 | disabled | Light | Positive UART1 RxD signal
reduced by 2 so that `ESP_PM_WUP_UART0` or `ESP_PM_WUP_UART1` plus 2 is
the number of positive edges required to wake up.
@note
- Wake-up from _Light-sleep_ mode works for any of the GPIOs defined as input
with enabled interrupt.
- `ESP_PM_GPIO_HOLD` is not available on ESP32-C3 variant.
- `ESP_PM_GPIO_HOLD` works only for RTC GPIOs.
- `ESP_PM_WUP_PINS_ANY_LOW` is not available on ESP32 variant.
- `ESP_PM_WUP_PINS_ALL_LOW` is only available on ESP32 variant, all other
ESP32x variants support only `ESP_PM_WUP_PINS_ANY_LOW` instead.
In the following example the system shall be woken up from _Deep-sleep_ if
the pulled-up pin `GPIO25` (`ESP_PM_WUP_PINS=GPIO25`) goes LOW
(`ESP_PM_WUP_LEVEL=ESP_PM_WUP_PINS_ALL_LOW`). The last GPIO output values

1
cpu/esp32/doc_esp32.txt
View File

@ -110,7 +110,6 @@ The maximum number of ADC channels #ADC_NUMOF_MAX is 18
- ADC2 is also used by the WiFi module. The GPIOs connected to ADC2 are
therefore not available as ADC channels if the modules `esp_wifi` or
`esp_now` are used.
- Vref can be read with function #adc_line_vref_to_gpio at GPIO25.
## DAC Channels {#esp32_dac_channels_esp32}

18
cpu/esp32/doc_esp32c3.txt
View File

@ -80,10 +80,13 @@ total:
The maximum number of ADC channels #ADC_NUMOF_MAX is 6.
@note
- ADC2 is also used by the WiFi module. The GPIOs connected to ADC2 are
therefore not available as ADC channels if the modules `esp_wifi` or
- According to the ESP32-C2 Errata Sheet, ADC2 with GPIO5 as ADC channel may
not work correctly. By default it is still possible to use it anyway.
Set `CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3` to 0 if you do not want to use
it and want to activate the configuration check for this channel.
- ADC2 is also used by the WiFi module. GPIO5 connected to ADC2 is
therefore not available as ADC channels if the modules `esp_wifi*` or
`esp_now` are used.
- Vref can be read with function #adc_line_vref_to_gpio at GPIO5.
## I2C Interfaces {#esp32_i2c_interfaces_esp32c3}
@ -116,8 +119,7 @@ mode:
- Controller SPI0 is reserved for caching external memory like Flash
- Controller SPI1 is reserved for external memory like PSRAM
- Controller SPI2 can be used as general purpose SPI (also called HSPI)
- Controller SPI3 can be used as general purpose SPI (also called VSPI)
- Controller SPI2 can be used as general purpose SPI (also called FSPI)
Thus, only SPI2 (FSPI) can be used as general purpose SPI in RIOT as
SPI_DEV(0).
@ -176,15 +178,18 @@ UART_DEV(2) | RxD | GPIO16 |`UART2_RXD` | optional, can be overridden
There are two option on how to uese the JTAG interface on ESP32-C3:
1. Using the built-in USB-to-JTAG bridge connected to an USB cable as follows:
<center>
USB Signal | ESP32-C3 Pin
:--------------|:-----------
D- (white) | GPIO18
D+ (green) | GPIO19
V_Bus (red) | 5V
Ground (black) | GND
</center>
2. Using an external JTAG adapter connected to the JTAG interface exposed
to GPIOs as follows:
<center>
JTAG Signal | ESP32-C3 Pin
:-----------|:-----------
TRST_N | CHIP_PU
@ -193,10 +198,11 @@ There are two option on how to uese the JTAG interface on ESP32-C3:
TCK | GPIO6 (MTCK)
TMS | GPIO4 (MTMS)
GND | GND
<br>
</center><br>
@note This option requires that the USB D- and USB D+ signals are connected
to the ESP32-C3 USB interface at GPIO18 and GPIO19.
<br>
Using the built-in USB-to-JTAG is the default option, i.e. the JTAG interface
of the ESP32-C3 is connected to the built-in USB-to-JTAG bridge. To use an
external JTAG adapter, the JTAG interface of the ESP32-C3 has to be connected

2
cpu/esp32/doc_esp32s2.txt
View File

@ -170,8 +170,6 @@ total:
- ADC2 is also used by the WiFi module. The GPIOs connected to ADC2 are
therefore not available as ADC channels if the modules `esp_wifi` or
`esp_now` are used.
- Vref can be read with function #adc_line_vref_to_gpio at any ADC2 channel,
that is at GPIO11 ... GPIO20.
- GPIO3 is a strapping pin und shouldn't be used as ADC channel
## DAC Channels {#esp32_dac_channels_esp32s2}

2
cpu/esp32/doc_esp32s3.txt
View File

@ -182,8 +182,6 @@ total:
- ADC2 is also used by the WiFi module. The GPIOs connected to ADC2 are
therefore not available as ADC channels if the modules `esp_wifi` or
`esp_now` are used.
- Vref can be read with function #adc_line_vref_to_gpio at any ADC2 channel,
that is at GPIO11 ... GPIO20.
- GPIO3 is a strapping pin und shouldn't be used as ADC channel
## I2C Interfaces {#esp32_i2c_interfaces_esp32s3}

39
cpu/esp32/esp-eth/esp_eth_netdev.c
View File

@ -24,6 +24,7 @@
#include <string.h>
#include <assert.h>
#include <errno.h>
#include <stdarg.h>
#include "net/gnrc/netif/ethernet.h"
#include "net/gnrc.h"
@ -32,7 +33,6 @@
#include "od.h"
#include "timex.h"
#include "ztimer.h"
#include "esp_common.h"
#include "esp_attr.h"
@ -44,7 +44,9 @@
#include "esp_eth.h"
#include "esp_eth_phy.h"
#include "esp_eth_mac.h"
#include "esp_eth_mac_esp.h"
#include "esp_event.h"
#include "esp_event_legacy.h"
#include "board.h"
@ -73,6 +75,10 @@
#define esp_eth_phy_new_xxxxx(cfg) esp_eth_phy_new_ksz8081(cfg)
#elif defined(EMAC_PHY_RTL8201)
#define esp_eth_phy_new_xxxxx(cfg) esp_eth_phy_new_rtl8201(cfg)
#elif defined(EMAC_PHY_GENERIC)
#define esp_eth_phy_new_xxxxx(cfg) esp_eth_phy_new_generic(cfg)
#else
#error "Physiscal layer transceiver not defined"
#endif
/* for source code compatibility of board definitions from ESP-IDF 3.1 */
@ -164,31 +170,36 @@ static int _esp_eth_init(netdev_t *netdev)
phy_config.phy_addr = EMAC_PHY_ADDRESS;
phy_config.reset_gpio_num = EMAC_PHY_POWER_PIN;
/* set MAC configuration */
/* set EMAC configuration */
eth_mac_config_t mac_config = ETH_MAC_DEFAULT_CONFIG();
mac_config.sw_reset_timeout_ms = 500;
mac_config.smi_mdc_gpio_num = EMAC_PHY_SMI_MDC_PIN;
mac_config.smi_mdio_gpio_num = EMAC_PHY_SMI_MDIO_PIN;
mac_config.rx_task_prio = 20;
/* set EMAC configuration */
eth_esp32_emac_config_t emac_config = ETH_ESP32_EMAC_DEFAULT_CONFIG();
emac_config.smi_gpio.mdc_num = EMAC_PHY_SMI_MDC_PIN;
emac_config.smi_gpio.mdio_num = EMAC_PHY_SMI_MDIO_PIN;
if (EMAC_PHY_CLOCK_MODE == ETH_CLOCK_GPIO0_IN) {
mac_config.clock_config.rmii.clock_mode = EMAC_CLK_EXT_IN;
mac_config.clock_config.rmii.clock_gpio = EMAC_CLK_IN_GPIO;
emac_config.clock_config.rmii.clock_mode = EMAC_CLK_EXT_IN;
emac_config.clock_config.rmii.clock_gpio = EMAC_CLK_IN_GPIO;
}
else if (EMAC_PHY_CLOCK_MODE == ETH_CLOCK_GPIO0_OUT) {
mac_config.clock_config.rmii.clock_mode = EMAC_CLK_OUT;
mac_config.clock_config.rmii.clock_gpio = EMAC_APPL_CLK_OUT_GPIO;
emac_config.clock_config.rmii.clock_mode = EMAC_CLK_OUT;
emac_config.clock_config.rmii.clock_gpio = EMAC_APPL_CLK_OUT_GPIO;
}
else if (EMAC_PHY_CLOCK_MODE == ETH_CLOCK_GPIO16_OUT) {
mac_config.clock_config.rmii.clock_mode = EMAC_CLK_OUT;
mac_config.clock_config.rmii.clock_gpio = EMAC_CLK_OUT_GPIO;
emac_config.clock_config.rmii.clock_mode = EMAC_CLK_OUT;
emac_config.clock_config.rmii.clock_gpio = EMAC_CLK_OUT_GPIO;
}
else if (EMAC_PHY_CLOCK_MODE == ETH_CLOCK_GPIO17_OUT) {
mac_config.clock_config.rmii.clock_mode = EMAC_CLK_OUT;
mac_config.clock_config.rmii.clock_gpio = EMAC_CLK_OUT_180_GPIO;
emac_config.clock_config.rmii.clock_mode = EMAC_CLK_OUT;
emac_config.clock_config.rmii.clock_gpio = EMAC_CLK_OUT_180_GPIO;
}
esp_eth_mac_t *mac = esp_eth_mac_new_esp32(&mac_config);
esp_eth_mac_t *mac = esp_eth_mac_new_esp32(&emac_config, &mac_config);
esp_eth_phy_t *phy = esp_eth_phy_new_xxxxx(&phy_config);
/* generate Ethernet driver configuration */
@ -301,7 +312,7 @@ static int _esp_eth_recv(netdev_t *netdev, void *buf, size_t len, void *info)
if (IS_ACTIVE(ENABLE_DEBUG)) {
printf ("%s: received %d byte\n", __func__, dev->rx_len);
if (IS_ACTIVE(ENABLE_DEBUG) && IS_USED(MODULE_OD)) {
if (IS_ACTIVE(ENABLE_DEBUG_HEXDUMP) && IS_USED(MODULE_OD)) {
od_hex_dump(dev->rx_buf, dev->rx_len, OD_WIDTH_DEFAULT);
}
}

18
cpu/esp32/esp-idf-api/Makefile
View File

@ -1,18 +0,0 @@
MODULE = esp_idf_api
# ESP-IDF header files must be found first in this module. Therefore,
# the ESP-IDF include paths must come before the RIOT include paths.
PRE_INCLUDES += -I$(ESP32_SDK_DIR)/components/driver/include
PRE_INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_common/include
PRE_INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_hw_support/include
PRE_INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_rom/include
PRE_INCLUDES += -I$(ESP32_SDK_DIR)/components/hal/include
PRE_INCLUDES += -I$(ESP32_SDK_DIR)/components/hal/platform_port/include
PRE_INCLUDES += -I$(ESP32_SDK_DIR)/components/soc/include
PRE_INCLUDES += -I$(ESP32_SDK_DIR)/components/hal/$(CPU_FAM)/include
PRE_INCLUDES += -I$(ESP32_SDK_DIR)/components/soc/$(CPU_FAM)/include
include $(RIOTBASE)/Makefile.base
INCLUDES := $(PRE_INCLUDES) $(INCLUDES)

23
cpu/esp32/esp-idf-api/doc.txt
View File

@ -1,23 +0,0 @@
/*
* Copyright (C) 2022 Gunar Schorcht
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @defgroup cpu_esp32_esp_idf_api ESP-IDF Interface API
* @ingroup cpu_esp32
* @brief ESP-IDF Interface API
*
* This module implements an interface for ESP-IDF types and functions that are
* required by RIOT-OS but cannot be included directly due to name conflicts.
*
* For this purpose, the header files of this module declare all the types and
* functions that are required from the ESP-IDF, but without using the ESP-IDF
* header files with conflicting names. The implementation of the module then
* uses the ESP-IDF. In most cases, simple wrapper functions are sufficient.
*
* @author Gunar Schorcht <gunar@schorcht.net>
*/

144
cpu/esp32/esp-idf-api/gpio.c
View File

@ -1,144 +0,0 @@
/*
* Copyright (C) 2022 Gunar Schorcht
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_esp32_esp_idf_api
* @{
*
* @file
* @brief Interface for the ESP-IDF GPIO HAL API
*
* @author Gunar Schorcht <gunar@schorcht.net>
* @}
*/
#include <stdbool.h>
#include "driver/gpio.h"
#include "driver/rtc_io.h"
#include "hal/gpio_hal.h"
#include "esp_sleep.h"
#include "esp_idf_api/gpio.h"
esp_err_t esp_idf_gpio_config(const gpio_config_t *cfg)
{
return gpio_config(cfg);
}
esp_err_t esp_idf_gpio_reset_pin(gpio_num_t gpio_num)
{
return gpio_reset_pin(gpio_num);
}
esp_err_t esp_idf_gpio_intr_enable(gpio_num_t gpio_num)
{
return gpio_intr_enable(gpio_num);
}
esp_err_t esp_idf_gpio_intr_disable(gpio_num_t gpio_num)
{
return gpio_intr_disable(gpio_num);
}
esp_err_t esp_idf_gpio_set_intr_type(gpio_num_t gpio_num,
gpio_int_type_t intr_type)
{
return gpio_set_intr_type(gpio_num, intr_type);
}
esp_err_t esp_idf_gpio_install_isr_service(int intr_alloc_flags)
{
return gpio_install_isr_service(intr_alloc_flags);
}
esp_err_t esp_idf_gpio_isr_handler_add(gpio_num_t gpio_num,
gpio_isr_t isr_handler, void *args)
{
return gpio_isr_handler_add(gpio_num, isr_handler, args);
}
esp_err_t esp_idf_gpio_wakeup_enable(gpio_num_t gpio_num,
gpio_int_type_t intr_type)
{
return gpio_wakeup_enable(gpio_num, intr_type);
}
#ifdef ESP_PM_GPIO_HOLD
esp_err_t esp_idf_gpio_deep_sleep_hold(void)
{
#if SOC_RTCIO_HOLD_SUPPORTED
extern esp_err_t rtc_gpio_force_hold_en_all(void);
return rtc_gpio_force_hold_en_all();
#elif SOC_GPIO_SUPPORT_FORCE_HOLD
gpio_deep_sleep_hold_en();
return ESP_OK;
#else
_Static_assert(0, "ESP32x SoC does not support hold feature in deep sleep");
return ESP_FAIL;
#endif
#if CPU_FAM_ESP32
/* isolating GPIO12 from external circuits is especially recommended for
* ESP32-WROVER that have an external pullup on GPIO12 */
rtc_gpio_isolate(GPIO_NUM_12);
#endif
}
#endif /* ESP_PM_GPIO_HOLD */
esp_err_t esp_idf_gpio_set_drive_capability(gpio_num_t gpio_num,
gpio_drive_cap_t strength)
{
return gpio_set_drive_capability(gpio_num, strength);
}
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
esp_err_t esp_idf_rtc_gpio_deinit(gpio_num_t gpio_num)
{
if (!rtc_gpio_is_valid_gpio(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
return rtc_gpio_deinit(gpio_num);
}
esp_err_t esp_idf_rtc_gpio_pullup_en(gpio_num_t gpio_num)
{
if (!rtc_gpio_is_valid_gpio(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
return rtc_gpio_pullup_en(gpio_num);
}
esp_err_t esp_idf_rtc_gpio_pullup_dis(gpio_num_t gpio_num)
{
if (!rtc_gpio_is_valid_gpio(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
return rtc_gpio_pullup_dis(gpio_num);
}
esp_err_t esp_idf_rtc_gpio_pulldown_en(gpio_num_t gpio_num)
{
if (!rtc_gpio_is_valid_gpio(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
return rtc_gpio_pulldown_en(gpio_num);
}
esp_err_t esp_idf_rtc_gpio_pulldown_dis(gpio_num_t gpio_num)
{
if (!rtc_gpio_is_valid_gpio(gpio_num)) {
return ESP_ERR_INVALID_ARG;
}
return rtc_gpio_pulldown_dis(gpio_num);
}
#endif

50
cpu/esp32/esp-idf-api/uart.c
View File

@ -1,50 +0,0 @@
/*
* Copyright (C) 2022 Gunar Schorcht
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_esp32_esp_idf_api
* @{
*
* @file
* @brief Interface for the ESP-IDF UART HAL API
*
* @author Gunar Schorcht <gunar@schorcht.net>
* @}
*/
#include <stdbool.h>
#include <stdint.h>
#include "driver/uart.h"
#include "hal/uart_hal.h"
#include "esp_idf_api/uart.h"
static uart_hal_context_t _uart_hal_ctx[] = {
#if UART_NUM_MAX >= 1
{
.dev = UART_LL_GET_HW(0),
},
#endif
#if UART_NUM_MAX >= 2
{
.dev = UART_LL_GET_HW(1),
},
#endif
#if UART_NUM_MAX >= 3
{
.dev = UART_LL_GET_HW(2),
},
#endif
};
void esp_idf_uart_set_wakeup_threshold(unsigned uart_num, uint32_t threshold)
{
assert(uart_num < ARRAY_SIZE(_uart_hal_ctx));
uart_hal_set_wakeup_thrd(&_uart_hal_ctx[uart_num], threshold);
}

32
cpu/esp32/esp-idf/adc/Makefile
View File

@ -2,28 +2,44 @@ MODULE = esp_idf_adc
# source files to be compiled for this module
ESP32_SDK_SRC = \
components/driver/adc.c \
components/driver/adc_common.c \
components/hal/adc_hal.c \
components/esp_adc/adc_cali.c \
components/esp_adc/adc_common.c \
components/esp_adc/adc_oneshot.c \
components/esp_hw_support/adc_share_hw_ctrl.c \
components/hal/adc_hal_common.c \
components/hal/adc_oneshot_hal.c \
components/soc/$(CPU_FAM)/adc_periph.c \
#
ifneq (,$(filter esp32c3 esp32s2,$(CPU_FAM)))
ESP32_SDK_SRC += components/driver/$(CPU_FAM)/adc2_init_cal.c
INCLUDES += -I$(ESP32_SDK_DIR)/components/driver/include/driver
ifeq (,$(filter esp_idf_gpio,$(USEMODULE)))
ESP32_SDK_SRC += components/hal/rtc_io_hal.c
endif
ifneq (,$(filter esp32c3 esp32h2 esp32s3,$(CPU_FAM)))
ifneq (esp32,$(CPU_FAM))
ESP32_SDK_SRC += components/efuse/$(CPU_FAM)/esp_efuse_rtc_calib.c
endif
ifneq (,$(filter esp32s2,$(CPU_FAM)))
ifeq (esp32s2,$(CPU_FAM))
ESP32_SDK_SRC += components/efuse/esp32s2/esp_efuse_rtc_table.c
endif
ifneq (,$(filter esp32 esp32s2,$(CPU_FAM)))
ESP32_SDK_SRC += components/esp_adc/$(CPU_FAM)/adc_cali_line_fitting.c
else
ESP32_SDK_SRC += components/esp_adc/adc_cali_curve_fitting.c
endif
ifneq (,$(filter esp32h2 esp32s3 esp32c3 esp32c6,$(CPU_FAM)))
ESP32_SDK_SRC += components/esp_adc/$(CPU_FAM)/curve_fitting_coefficients.c
endif
include $(RIOTBASE)/Makefile.base
ESP32_SDK_BIN = $(BINDIR)/$(MODULE)
CFLAGS += -Wno-unused-but-set-variable
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_adc/interface
include ../esp_idf.mk
include ../esp_idf_cflags.mk

29
cpu/esp32/esp-idf/ble/Makefile
View File

@ -1,27 +1,20 @@
MODULE = esp_idf_ble
# source files to be compiled for this module
ESP32_SDK_SRC = \
components/bt/controller/$(CPU_FAM)/bt.c \
#
ifeq (,$(filter esp_idf_wifi,$(USEMODULE)))
ESP32_SDK_SRC += \
components/esp_hw_support/port/$(CPU_FAM)/dport_access.c \
components/esp_phy/src/phy_init.c \
components/esp_wifi/src/wifi_init.c \
#
ifeq (esp32,$(CPU_FAM))
# source files to be compiled for this module
ESP32_SDK_SRC += components/bt/controller/$(CPU_FAM)/bt.c
ESP32_SDK_SRC += components/esp_system/esp_system.c
else ifneq (,$(filter esp32s3 esp32c3,$(CPU_FAM)))
# source files to be compiled for this module
ESP32_SDK_SRC += components/bt/controller/esp32c3/bt.c
ESP32_SDK_SRC += components/esp_system/esp_system.c
endif
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_event/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_netif/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_phy/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_phy/$(CPU_FAM)/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_coex/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_partition/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_wifi/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/nvs_flash/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_phy/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/wpa_supplicant/esp_supplicant/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/tcpip_adapter/include
CFLAGS += -Wno-cast-function-type
CFLAGS += -Wno-implicit-fallthrough

114
cpu/esp32/esp-idf/common/Makefile
View File

@ -2,35 +2,47 @@ MODULE = esp_idf_common
# source files required from ESP-IDF in any case, regardless of additional modules
ESP32_SDK_SRC = \
components/bootloader_support/src/bootloader_flash_config_$(CPU_FAM).c \
components/bootloader_support/src/bootloader_flash.c \
components/bootloader_support/src/bootloader_efuse_$(CPU_FAM).c \
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_$(CPU_FAM).c \
components/bootloader_support/bootloader_flash/src/bootloader_flash.c \
components/bootloader_support/src/bootloader_common.c \
components/bootloader_support/src/bootloader_efuse.c \
components/bootloader_support/src/bootloader_mem.c \
components/bootloader_support/src/bootloader_random_$(CPU_FAM).c \
components/driver/periph_ctrl.c \
components/esp_hw_support/cpu_util.c \
components/esp_app_format/esp_app_desc.c \
components/esp_hw_support/clk_ctrl_os.c \
components/esp_hw_support/esp_clk.c \
components/esp_hw_support/esp_gpio_reserve.c \
components/esp_hw_support/periph_ctrl.c \
components/esp_hw_support/port/$(CPU_FAM)/esp_clk_tree.c \
components/esp_hw_support/port/$(CPU_FAM)/rtc_clk.c \
components/esp_hw_support/port/$(CPU_FAM)/rtc_clk_init.c \
components/esp_hw_support/port/$(CPU_FAM)/rtc_init.c \
components/esp_hw_support/port/$(CPU_FAM)/rtc_sleep.c \
components/esp_hw_support/port/$(CPU_FAM)/rtc_time.c \
components/esp_hw_support/port/$(CPU_FAM)/sar_periph_ctrl.c \
components/esp_hw_support/port/esp_clk_tree_common.c \
components/esp_hw_support/regi2c_ctrl.c \
components/esp_hw_support/sleep_gpio.c \
components/esp_hw_support/sleep_event.c \
components/esp_hw_support/sleep_modes.c \
components/esp_pm/pm_impl.c \
components/esp_hw_support/sleep_modem.c \
components/esp_mm/esp_cache.c \
components/esp_mm/esp_mmu_map.c \
components/esp_mm/port/$(CPU_FAM)/ext_mem_layout.c \
components/esp_rom/patches/esp_rom_sys.c \
components/esp_rom/patches/esp_rom_uart.c \
components/esp_system/esp_err.c \
components/esp_system/esp_system.c \
components/esp_system/port/cpu_start.c \
components/esp_system/port/soc/$(CPU_FAM)/cache_err_int.c \
components/esp_system/port/soc/$(CPU_FAM)/clk.c \
components/esp_system/port/soc/$(CPU_FAM)/reset_reason.c \
components/esp_system/system_time.c \
components/esp_system/port/esp_system_chip.c \
components/esp_timer/src/esp_timer.c \
components/esp_timer/src/esp_timer_impl_common.c \
components/esp_timer/src/esp_timer_init.c \
components/esp_timer/src/system_time.c \
components/hal/cpu_hal.c \
components/hal/mpu_hal.c \
components/hal/timer_hal.c \
components/hal/efuse_hal.c \
components/hal/mmu_hal.c \
components/hal/$(CPU_FAM)/clk_tree_hal.c \
components/hal/$(CPU_FAM)/efuse_hal.c \
components/hal/uart_hal.c \
components/hal/wdt_hal_iram.c \
components/newlib/port/esp_time_impl.c \
@ -38,8 +50,37 @@ ESP32_SDK_SRC = \
components/spi_flash/flash_ops.c \
#
ifneq (,$(filter periph_adc periph_dac,$(USEMODULE)))
ESP32_SDK_SRC += components/hal/rtc_io_hal.c
ifneq (,$(filter esp_idf_nvs_flash,$(USEMODULE)))
ESP32_SDK_SRC += components/bootloader_support/src/flash_encrypt.c
ESP32_SDK_SRC += components/esp_partition/partition.c
ESP32_SDK_SRC += components/esp_partition/partition_target.c
INCLUDES += -I$(ESP32_SDK_DIR)/components/app_update/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_bootloader_format/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_partition/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/nvs_flash/include
endif
ifneq (,$(filter esp_spi_ram,$(USEMODULE)))
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_psram/include
endif
# TODO separate module
ifneq (,$(filter esp_idf_phy,$(USEMODULE)))
ESP32_SDK_SRC += components/esp_phy/$(CPU_FAM)/phy_init_data.c
ESP32_SDK_SRC += components/esp_phy/src/phy_common.c
ESP32_SDK_SRC += components/esp_phy/src/phy_init.c
ESP32_SDK_SRC += components/esp_system/port/soc/$(CPU_FAM)/reset_reason.c
ESP32_SDK_SRC += components/soc/esp32/dport_access.c
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_event/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_netif/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_phy/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_phy/$(CPU_FAM)/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_wifi/include
ifeq (,$(filter esp_idf_wifi,$(USEMODULE)))
ESP32_SDK_SRC += components/esp_wifi/src/wifi_init.c
INCLUDES += -I$(ESP32_SDK_DIR)/components/wpa_supplicant/esp_supplicant/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_coex/include
endif
endif
# TODO separate module
@ -50,7 +91,6 @@ endif
# TODO separate module
ifneq (,$(filter periph_dac,$(USEMODULE)))
ESP32_SDK_SRC += components/driver/dac_common.c
ESP32_SDK_SRC += components/soc/$(CPU_FAM)/dac_periph.c
endif
@ -61,9 +101,7 @@ endif
# TODO separate module
ifneq (,$(filter periph_i2c%,$(USEMODULE)))
ESP32_SDK_SRC += components/driver/i2c.c
ESP32_SDK_SRC += components/hal/i2c_hal.c
ESP32_SDK_SRC += components/hal/i2c_hal_iram.c
ESP32_SDK_SRC += components/soc/$(CPU_FAM)/i2c_periph.c
endif
@ -76,52 +114,66 @@ endif
# TODO separate module
ifneq (,$(filter periph_spi,$(USEMODULE)))
ESP32_SDK_SRC += components/hal/spi_hal.c
ESP32_SDK_SRC += components/soc/$(CPU_FAM)/spi_periph.c
endif
# TODO separate module
ifneq (,$(filter periph_uart,$(USEMODULE)))
ESP32_SDK_SRC += components/soc/$(CPU_FAM)/uart_periph.c
endif
ifneq (,$(filter xtensa%,$(TARGET_ARCH)))
ESP32_SDK_SRC += components/esp_hw_support/port/$(CPU_FAM)/rtc_wdt.c
ESP32_SDK_SRC += components/soc/$(CPU_FAM)/rtc_io_periph.c
endif
ifneq (,$(filter riscv%,$(TARGET_ARCH)))
ESP32_SDK_SRC += components/riscv/interrupt.c
ESP32_SDK_ASMSRC += components/freertos/port/riscv/portasm.S
ESP32_SDK_SRC += components/riscv/interrupt_intc.c
ESP32_SDK_ASMSRC += components/freertos/FreeRTOS-Kernel/portable/riscv/portasm.S
ESP32_SDK_ASMSRC += components/riscv/vectors.S
ESP32_SDK_ASMSRC += components/riscv/vectors_intc.S
endif
ifeq (esp32,$(CPU_FAM))
ESP32_SDK_SRC += components/esp_timer/src/esp_timer_impl_frc_legacy.c
ESP32_SDK_SRC += components/esp_mm/cache_esp32.c
ESP32_SDK_SRC += components/esp_timer/src/esp_timer_impl_lac.c
ESP32_SDK_SRC += components/hal/esp32/cache_hal_esp32.c
endif
ifeq (esp32c3,$(CPU_FAM))
ESP32_SDK_SRC += components/esp_hw_support/port/$(CPU_FAM)/cpu_util_$(CPU_FAM).c
ESP32_SDK_SRC += components/esp_hw_support/sleep_retention.c
ESP32_SDK_SRC += components/esp_hw_support/lowpower/port/$(CPU_FAM)/sleep_cpu.c
ESP32_SDK_SRC += components/esp_hw_support/port/$(CPU_FAM)/systimer.c
ESP32_SDK_SRC += components/esp_hw_support/sleep_console.c
ESP32_SDK_SRC += components/esp_timer/src/esp_timer_impl_systimer.c
ESP32_SDK_SRC += components/hal/$(CPU_FAM)/rtc_cntl_hal.c
ESP32_SDK_SRC += components/hal/cache_hal.c
ESP32_SDK_SRC += components/hal/systimer_hal.c
endif
ifeq (esp32s2,$(CPU_FAM))
ESP32_SDK_SRC += components/esp_hw_support/port/$(CPU_FAM)/regi2c_ctrl.c
ESP32_SDK_SRC += components/esp_rom/patches/esp_rom_regi2c_$(CPU_FAM).c
ESP32_SDK_SRC += components/esp_hw_support/port/$(CPU_FAM)/systimer.c
ESP32_SDK_SRC += components/esp_hw_support/port/$(CPU_FAM)/memprot.c
ESP32_SDK_SRC += components/esp_hw_support/sleep_retention.c
ESP32_SDK_SRC += components/esp_system/port/brownout.c
ESP32_SDK_SRC += components/esp_timer/src/esp_timer_impl_systimer.c
ESP32_SDK_SRC += components/hal/$(CPU_FAM)/brownout_hal.c
ESP32_SDK_SRC += components/hal/$(CPU_FAM)/touch_sensor_hal.c
ESP32_SDK_SRC += components/hal/brownout_hal.c
ESP32_SDK_SRC += components/hal/cache_hal.c
ESP32_SDK_SRC += components/hal/systimer_hal.c
endif
ifeq (esp32s3,$(CPU_FAM))
ESP32_SDK_SRC += components/esp_hw_support/sleep_retention.c
ESP32_SDK_SRC += components/esp_hw_support/mspi_timing_tuning.c
ESP32_SDK_SRC += components/esp_hw_support/port/$(CPU_FAM)/mspi_timing_config.c
ESP32_SDK_SRC += components/esp_hw_support/port/$(CPU_FAM)/systimer.c
ESP32_SDK_SRC += components/esp_hw_support/sleep_console.c
ESP32_SDK_SRC += components/esp_rom/patches/esp_rom_cache_esp32s2_esp32s3.c
ESP32_SDK_SRC += components/esp_rom/patches/esp_rom_efuse.c
ESP32_SDK_SRC += components/esp_timer/src/esp_timer_impl_systimer.c
ESP32_SDK_SRC += components/hal/$(CPU_FAM)/rtc_cntl_hal.c
ESP32_SDK_SRC += components/hal/$(CPU_FAM)/touch_sensor_hal.c
ESP32_SDK_SRC += components/hal/cache_hal.c
ESP32_SDK_SRC += components/hal/systimer_hal.c
ESP32_SDK_SRC += components/spi_flash/spi_flash_timing_tuning.c
ESP32_SDK_SRC += components/spi_flash/$(CPU_FAM)/spi_timing_config.c
ESP32_SDK_SRC += components/spi_flash/$(CPU_FAM)/spi_flash_oct_flash_init.c
endif
include $(RIOTBASE)/Makefile.base

4
cpu/esp32/esp-idf/efuse/Makefile
View File

@ -11,9 +11,9 @@ ESP32_SDK_SRC = \
#
ifneq (,$(filter esp32,$(CPU_FAM)))
ESP32_SDK_SRC += components/efuse/src/esp_efuse_api_key_esp32.c
ESP32_SDK_SRC += components/efuse/src/efuse_controller/keys/without_key_purposes/three_key_blocks/esp_efuse_api_key.c
else
ESP32_SDK_SRC += components/efuse/src/esp_efuse_api_key_esp32xx.c
ESP32_SDK_SRC += components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c
endif
# additional include pathes required by this module

24
cpu/esp32/esp-idf/esp_idf.mk
View File

@ -1,19 +1,25 @@
# common definitions for all ESP-IDF modules
# additional include pathes required by ESP-IDF module
INCLUDES += -I$(ESP32_SDK_DIR)/components/bootloader_support/bootloader_flash/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/bootloader_support/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/bootloader_support/include_bootloader
INCLUDES += -I$(ESP32_SDK_DIR)/components/driver/$(CPU_FAM)/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/bootloader_support/private_include
INCLUDES += -I$(ESP32_SDK_DIR)/components/efuse/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/efuse/$(CPU_FAM)/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/efuse/$(CPU_FAM)/private_include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_app_format/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_driver_gpio/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_hw_support/ldo/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_hw_support/port/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_hw_support/port/$(CPU_FAM)
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_hw_support/port/$(CPU_FAM)/private_include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_ipc/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_mm/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_pm/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_system/port/public_compat
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_system/port/include/private
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_timer/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_timer/private_include
INCLUDES += -I$(ESP32_SDK_DIR)/components/freertos/esp_additions/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/hal/platform_port/include/hal
INCLUDES += -I$(ESP32_SDK_DIR)/components/hal/$(CPU_FAM)/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/newlib/priv_include
INCLUDES += -I$(ESP32_SDK_DIR)/components/spi_flash/include
@ -22,8 +28,12 @@ ifneq (,$(filter xtensa%,$(TARGET_ARCH)))
INCLUDES += -I$(ESP32_SDK_DIR)/components/xtensa/$(CPU_FAM)/include
endif
ifneq (,$(filter esp32c3 esp32h2 esp32s3,$(CPU_FAM)))
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_hw_support/port/$(CPU_FAM)/private_include
ifeq (esp32s3,$(CPU_FAM))
INCLUDES += -I$(ESP32_SDK_DIR)/components/spi_flash/include/spi_flash
endif
ifneq (,$(filter periph_i2c%,$(USEMODULE)))
INCLUDES += -I$(ESP32_SDK_DIR)/components/driver/i2c/include
endif
SRC := $(addprefix $(ESP32_SDK_DIR)/,$(ESP32_SDK_SRC))

7
cpu/esp32/esp-idf/esp_idf_cflags.mk
View File

@ -34,13 +34,10 @@ CFLAGS += -Wno-enum-compare
# those are false positives.
CFLAGS += -Wno-cast-align
# TODO: required to be able to compile with GCC 12.1, remove them after upgrade to ESP-IDF 5.1
CFLAGS += -Wno-attributes
# TODO: required to be able to compile with GCC 14.0, remove them later
CFLAGS += -Wno-enum-conversion
CFLAGS += -Wno-error=format=
CFLAGS += -Wno-format
CFLAGS += -Wno-use-after-free
CFLAGS += -Wno-incompatible-pointer-types
CFLAGS += -Wno-unused-function
# additional CFLAGS required for RISC-V architecture
ifneq (,$(filter riscv32%,$(TARGET_ARCH)))

48
cpu/esp32/esp-idf/esp_idf_support.c
View File

@ -36,39 +36,6 @@
ESP_EVENT_DEFINE_BASE(IP_EVENT);
#endif
/* Global variables required by ESP-IDF */
uint8_t *g_wpa_anonymous_identity;
int g_wpa_anonymous_identity_len;
uint8_t *g_wpa_username;
int g_wpa_username_len;
uint8_t *g_wpa_password;
int g_wpa_password_len;
uint8_t *g_wpa_new_password;
int g_wpa_new_password_len;
const uint8_t *g_wpa_client_cert;
int g_wpa_client_cert_len;
const uint8_t *g_wpa_private_key;
int g_wpa_private_key_len;
const uint8_t *g_wpa_private_key_passwd;
int g_wpa_private_key_passwd_len;
const uint8_t *g_wpa_ca_cert;
int g_wpa_ca_cert_len;
char *g_wpa_ttls_phase2_type;
bool g_wpa_suiteb_certification;
char *g_wpa_phase1_options;
uint8_t *g_wpa_pac_file;
int g_wpa_pac_file_len;
/*
* provided by: /path/to/esp-idf/components/log/log_freertos.c
*/
@ -88,7 +55,7 @@ static esp_log_level_entry_t _log_levels[] = {
};
/*
* provided by: /path/to/esp-idf/component/log/log.c
* provided by: /path/to/esp-idf/components/log/log.c
*/
void IRAM_ATTR esp_log_write(esp_log_level_t level,
const char* tag, const char* format, ...)
@ -100,7 +67,7 @@ void IRAM_ATTR esp_log_write(esp_log_level_t level,
}
/*
* provided by: /path/to/esp-idf/component/log/log.c
* provided by: /path/to/esp-idf/components/log/log.c
*/
void IRAM_ATTR esp_log_writev(esp_log_level_t level,
const char *tag,
@ -134,7 +101,7 @@ void IRAM_ATTR esp_log_writev(esp_log_level_t level,
}
/*
* provided by: /path/to/esp-idf/component/log/log.c
* provided by: /path/to/esp-idf/components/log/log.c
*/
void esp_log_level_set(const char* tag, esp_log_level_t level)
{
@ -152,3 +119,12 @@ void esp_log_level_set(const char* tag, esp_log_level_t level)
_log_levels[i].level = level;
}
/*
* provided by: /path/to/esp-idf/components/newlib/time.c
*/
void esp_newlib_time_init(void)
{
extern void esp_time_impl_init(void);
esp_time_impl_init();
}

19
cpu/esp32/esp-idf/eth/Makefile
View File

@ -3,15 +3,20 @@ MODULE = esp_idf_eth
# source files to be compiled for this module
ESP32_SDK_SRC = \
components/esp_eth/src/esp_eth.c \
components/esp_eth/src/esp_eth_mac_esp.c \
components/esp_eth/src/esp_eth_netif_glue.c \
components/esp_eth/src/esp_eth_phy.c \
components/esp_eth/src/esp_eth_phy_dp83848.c \
components/esp_eth/src/esp_eth_phy_ip101.c \
components/esp_eth/src/esp_eth_phy_ksz80xx.c \
components/esp_eth/src/esp_eth_phy_lan87xx.c \
components/esp_eth/src/esp_eth_phy_rtl8201.c \
components/esp_eth/src/mac/esp_eth_mac_esp.c \
components/esp_eth/src/mac/esp_eth_mac_esp_dma.c \
components/esp_eth/src/mac/esp_eth_mac_esp_gpio.c \
components/esp_eth/src/phy/esp_eth_phy_802_3.c \
components/esp_eth/src/phy/esp_eth_phy_dp83848.c \
components/esp_eth/src/phy/esp_eth_phy_generic.c \
components/esp_eth/src/phy/esp_eth_phy_ip101.c \
components/esp_eth/src/phy/esp_eth_phy_ksz80xx.c \
components/esp_eth/src/phy/esp_eth_phy_lan87xx.c \
components/esp_eth/src/phy/esp_eth_phy_rtl8201.c \
components/esp_hw_support/esp_clock_output.c \
components/hal/emac_hal.c \
components/soc/$(CPU_FAM)/emac_periph.c \
#
include $(RIOTBASE)/Makefile.base

7
cpu/esp32/esp-idf/gpio/Makefile
View File

@ -2,10 +2,11 @@ MODULE = esp_idf_gpio
# source files to be compiled for this module
ESP32_SDK_SRC = \
components/driver/gpio.c \
components/driver/rtc_io.c \
components/driver/rtc_module.c \
components/esp_driver_gpio/src/gpio.c \
components/esp_driver_gpio/src/rtc_io.c \
components/esp_hw_support/rtc_module.c \
components/hal/gpio_hal.c \
components/hal/rtc_io_hal.c \
components/soc/$(CPU_FAM)/gpio_periph.c \
#

6
cpu/esp32/esp-idf/heap/Makefile
View File

@ -2,12 +2,11 @@ MODULE = esp_idf_heap
# source files to be compiled for this module
ESP32_SDK_SRC = \
components/esp_mm/heap_align_hw.c \
components/heap/heap_caps.c \
components/heap/heap_caps_base.c \
components/heap/heap_caps_init.c \
components/heap/heap_task_info.c \
components/heap/heap_trace_standalone.c \
components/heap/multi_heap.c \
components/heap/multi_heap_poisoning.c \
components/heap/port/$(CPU_FAM)/memory_layout.c \
components/heap/port/memory_layout_utils.c \
#
@ -22,6 +21,7 @@ ESP32_SDK_SRC = \
# additional include pathes required by this module
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_rom/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_system/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/heap/tlsf
include $(RIOTBASE)/Makefile.base

21
cpu/esp32/esp-idf/include/driver/gpio.h
View File

@ -1,21 +0,0 @@
#pragma once
#ifdef ESP_IDF_CODE
#include_next "driver/gpio.h"
#else
#include "hal/gpio_types.h"
#define GPIO_PIN_COUNT (SOC_GPIO_PIN_COUNT)
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif

21
cpu/esp32/esp-idf/include/log/esp_log.h
View File

@ -25,6 +25,7 @@
extern "C" {
#endif
#include "log.h"
#include_next "esp_log.h"
#if defined(RIOT_VERSION)
@ -55,7 +56,7 @@ extern "C" {
} while (0)
#define ESP_LOG_LEVEL_LOCAL(level, tag, format, ...) \
do { \
do { \
if ( LOG_LOCAL_LEVEL >= level ) { \
ESP_LOG_LEVEL(level, tag, format, ##__VA_ARGS__); \
} \
@ -69,26 +70,32 @@ extern "C" {
#if MODULE_ESP_LOG_TAGGED
#define ESP_DRAM_LOGE(tag, format, ...) \
#define ESP_DRAM_LOG_LEVEL(level, letter, tag, format, ...) \
do { \
if ((esp_log_level_t)LOG_LOCAL_LEVEL >= ESP_LOG_ERROR ) { \
esp_rom_printf(DRAM_STR(LOG_FORMAT(E, format)), \
if ((esp_log_level_t)LOG_LOCAL_LEVEL >= level ) { \
esp_rom_printf(DRAM_STR(LOG_FORMAT(letter, format)), \
system_get_time_ms(), ##__VA_ARGS__); \
}\
} while (0U)
#else
#define ESP_DRAM_LOGE(tag, format, ...) \
#define ESP_DRAM_LOG_LEVEL(level, letter, tag, format, ...) \
do { \
if ((esp_log_level_t)LOG_LOCAL_LEVEL >= ESP_LOG_ERROR ) { \
esp_rom_printf(DRAM_STR(LOG_FORMAT(E, format)), \
if ((esp_log_level_t)LOG_LOCAL_LEVEL >= level ) { \
esp_rom_printf(DRAM_STR(LOG_FORMAT(letter, format)), \
##__VA_ARGS__); \
}\
} while (0U)
#endif
#define ESP_DRAM_LOGE(tag, format, ...) ESP_DRAM_LOG_LEVEL(LOG_ERROR , E, tag, format "\n", ##__VA_ARGS__)
#define ESP_DRAM_LOGW(tag, format, ...) ESP_DRAM_LOG_LEVEL(LOG_WARNING, W, tag, format "\n", ##__VA_ARGS__)
#define ESP_DRAM_LOGI(tag, format, ...) ESP_DRAM_LOG_LEVEL(LOG_INFO , I, tag, format "\n", ##__VA_ARGS__)
#define ESP_DRAM_LOGD(tag, format, ...) ESP_DRAM_LOG_LEVEL(LOG_DEBUG , D, tag, format "\n", ##__VA_ARGS__)
#define ESP_DRAM_LOGV(tag, format, ...) ESP_DRAM_LOG_LEVEL(LOG_ALL , V, tag, format "\n", ##__VA_ARGS__)
#endif /* defined(RIOT_VERSION) */
#ifdef __cplusplus

23
cpu/esp32/esp-idf/lcd/Makefile
View File

@ -9,13 +9,21 @@ ESP32_SDK_SRC = \
#
ifeq (esp32s3,$(CPU_FAM))
ESP32_SDK_SRC += \
components/driver/gdma.c \
components/esp_lcd/src/esp_lcd_panel_io_i80.c \
components/hal/gdma_hal.c \
components/hal/lcd_hal.c \
components/soc/$(CPU_FAM)/gdma_periph.c \
#
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_hw_support/dma/include
ESP32_SDK_SRC += components/esp_lcd/i80/esp_lcd_panel_io_i80.c
ESP32_SDK_SRC += components/hal/lcd_hal.c
ifeq (,$(filter esp_idf_rmt,$(USEMODULE)))
ESP32_SDK_SRC += components/bootloader_support/src/flash_encrypt.c
ESP32_SDK_SRC += components/esp_hw_support/dma/gdma.c
ESP32_SDK_SRC += components/esp_hw_support/dma/gdma_link.c
ESP32_SDK_SRC += components/hal/gdma_hal_ahb_v1.c
ESP32_SDK_SRC += components/hal/gdma_hal_top.c
ESP32_SDK_SRC += components/soc/$(CPU_FAM)/gdma_periph.c
ESP32_SDK_ASMSRC += components/esp_rom/patches/esp_rom_cache_writeback_esp32s3.S
endif
ifeq (,$(filter esp_idf_sdmmc,$(USEMODULE)))
ESP32_SDK_SRC += components/esp_hw_support/esp_memory_utils.c
endif
else ifneq (,$(filter esp32 esp32s2,$(CPU_FAM)))
ESP32_SDK_SRC = \
components/driver/i2s.c \
@ -27,6 +35,7 @@ endif
# additional include pathes required by this module
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_lcd/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_lcd/interface
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_lcd/priv_include
include $(RIOTBASE)/Makefile.base

6
cpu/esp32/esp-idf/nvs_flash/Makefile
View File

@ -3,8 +3,6 @@ MODULE = esp_idf_nvs_flash
# source files to be compiled for this module
ESP32_SDK_SRCXX = \
components/nvs_flash/src/nvs_api.cpp \
components/nvs_flash/src/nvs_cxx_api.cpp \
components/nvs_flash/src/nvs_handle_locked.cpp \
components/nvs_flash/src/nvs_handle_simple.cpp \
components/nvs_flash/src/nvs_item_hash_list.cpp \
components/nvs_flash/src/nvs_page.cpp \
@ -12,13 +10,15 @@ ESP32_SDK_SRCXX = \
components/nvs_flash/src/nvs_partition.cpp \
components/nvs_flash/src/nvs_partition_lookup.cpp \
components/nvs_flash/src/nvs_partition_manager.cpp \
components/nvs_flash/src/nvs_platform.cpp \
components/nvs_flash/src/nvs_storage.cpp \
components/nvs_flash/src/nvs_types.cpp \
#
# additional include pathes required by this module
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_rom/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_partition/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/nvs_flash/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/nvs_flash/private_include
include $(RIOTBASE)/Makefile.base

18
cpu/esp32/esp-idf/rmt/Makefile
View File

@ -2,11 +2,25 @@ MODULE = esp_idf_rmt
# source files to be compiled for this module
ESP32_SDK_SRC = \
components/driver/rmt.c \
components/soc/$(CPU_FAM)/rmt_periph.c \
components/esp_driver_rmt/src/rmt_common.c \
components/esp_driver_rmt/src/rmt_encoder.c \
components/esp_driver_rmt/src/rmt_tx.c \
components/esp_pm/pm_locks.c \
components/hal/rmt_hal.c \
components/soc/$(CPU_FAM)/rmt_periph.c \
#
ifeq (esp32s3,$(CPU_FAM))
ESP32_SDK_SRC += components/bootloader_support/src/flash_encrypt.c
ESP32_SDK_SRC += components/esp_hw_support/dma/gdma.c
ESP32_SDK_SRC += components/hal/gdma_hal_ahb_v1.c
ESP32_SDK_SRC += components/hal/gdma_hal_top.c
ESP32_SDK_SRC += components/soc/$(CPU_FAM)/gdma_periph.c
ESP32_SDK_ASMSRC += components/esp_rom/patches/esp_rom_cache_writeback_esp32s3.S
endif
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_hw_support/dma/include
include $(RIOTBASE)/Makefile.base
ESP32_SDK_BIN = $(BINDIR)/$(MODULE)

11
cpu/esp32/esp-idf/sdmmc/Makefile
View File

@ -2,13 +2,18 @@ MODULE = esp_idf_sdmmc
# source files to be compiled for this module
ESP32_SDK_SRC = \
components/driver/sdmmc_host.c \
components/driver/sdmmc_transaction.c \
components/esp_driver_sdmmc/src/sdmmc_host.c \
components/esp_driver_sdmmc/src/sdmmc_transaction.c \
components/soc/$(CPU_FAM)/sdmmc_periph.c \
components/hal/sdmmc_hal.c \
components/esp_hw_support/dma/esp_dma_utils.c \
components/esp_hw_support/esp_memory_utils.c \
#
# additional include pathes required by this module
# INCLUDES += -I$(ESP32_SDK_DIR)/components/driver/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_driver_sdmmc/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/sdmmc/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_hw_support/dma/include
include $(RIOTBASE)/Makefile.base

54
cpu/esp32/esp-idf/spi_flash/Makefile
View File

@ -2,32 +2,56 @@ MODULE = esp_idf_spi_flash
# source files to be compiled for this module
ESP32_SDK_SRC = \
components/bootloader_support/src/bootloader_common.c \
components/driver/spi_common.c \
components/spi_flash/$(CPU_FAM)/flash_ops_$(CPU_FAM).c \
components/spi_flash/$(CPU_FAM)/spi_flash_rom_patch.c \
components/spi_flash/partition.c \
components/esp_rom/patches/esp_rom_spiflash.c \
components/hal/spi_flash_encrypt_hal_iram.c \
components/hal/spi_flash_hal.c \
components/hal/spi_flash_hal_iram.c \
components/spi_flash/esp_flash_api.c \
components/spi_flash/esp_flash_spi_init.c \
components/spi_flash/flash_mmap.c \
components/spi_flash/memspi_host_driver.c \
components/spi_flash/spi_flash_os_func_app.c \
components/spi_flash/spi_flash_os_func_noos.c \
components/spi_flash/spi_flash_chip_boya.c \
components/spi_flash/spi_flash_chip_drivers.c \
components/spi_flash/spi_flash_chip_gd.c \
components/spi_flash/spi_flash_chip_generic.c \
components/spi_flash/spi_flash_chip_issi.c \
components/spi_flash/spi_flash_chip_mxic.c \
components/spi_flash/spi_flash_chip_mxic_opi.c \
components/spi_flash/spi_flash_chip_th.c \
components/spi_flash/spi_flash_chip_winbond.c \
#
ifneq (,$(filter esp32,$(CPU_FAM)))
endif
ifneq (,$(filter esp32s2,$(CPU_FAM)))
ESP32_SDK_SRC += components/hal/spi_flash_hal_gpspi.c
endif
ifneq (,$(filter esp32s3,$(CPU_FAM)))
ESP32_SDK_SRC += components/hal/spi_flash_hal_gpspi.c
endif
ifneq (,$(filter esp32c3,$(CPU_FAM)))
ESP32_SDK_SRC += components/hal/spi_flash_hal_gpspi.c
endif
ifeq (,$(filter periph_spi,$(USEMODULE)))
# no need to compile it here if it is already compiled for periph_spi
ESP32_SDK_SRC += components/soc/$(CPU_FAM)/spi_periph.c
endif
ifneq (,$(filter esp32,$(CPU_FAM)))
ESP32_SDK_SRC += components/spi_flash/esp_flash_spi_init.c
endif
ifneq (,$(filter esp32 esp32s2 esp32s3,$(CPU_FAM)))
ESP32_SDK_SRC += components/spi_flash/flash_mmap.c
endif
# additional include pathes required by this module
INCLUDES += -I$(ESP32_SDK_DIR)/components/app_update/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/bootloader_support/include_bootloader
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_rom/$(CPU_FAM)
INCLUDES += -I$(ESP32_SDK_DIR)/components/spi_flash/include/spi_flash
ifeq (,$(filter esp_spi_ram,$(USEMODULE)))
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_psram/include
endif
include $(RIOTBASE)/Makefile.base
ESP32_SDK_BIN = $(BINDIR)/$(MODULE)

23
cpu/esp32/esp-idf/spi_ram/Makefile
View File

@ -1,20 +1,31 @@
MODULE = esp_idf_spi_ram
# source files to be compiled for this module
ESP32_SDK_SRC = \
components/esp_hw_support/port/$(CPU_FAM)/spiram.c \
components/esp_hw_support/port/$(CPU_FAM)/spiram_psram.c \
#
ESP32_SDK_SRC += components/esp_psram/esp_psram.c
ifeq (esp32,$(CPU_FAM))
ESP32_SDK_SRC += components/esp_hw_support/port/$(CPU_FAM)/cache_sram_mmu.c
ESP32_SDK_SRC += components/esp_psram/$(CPU_FAM)/esp_psram_extram_cache.c
ESP32_SDK_SRC += components/esp_psram/$(CPU_FAM)/esp_psram_impl_quad.c
endif
ifneq (,$(filter esp_spi_oct,$(USEMODULE)))
ESP32_SDK_SRC += components/esp_hw_support/port/$(CPU_FAM)/opiram_psram.c
ifeq (esp32s2,$(CPU_FAM))
ESP32_SDK_SRC += components/esp_psram/$(CPU_FAM)/esp_psram_impl_quad.c
endif
ifeq (esp32s3,$(CPU_FAM))
ifneq (,$(filter esp_spi_oct,$(USEMODULE)))
ESP32_SDK_SRC += components/esp_psram/$(CPU_FAM)/esp_psram_impl_octal.c
else
ESP32_SDK_SRC += components/esp_psram/device/esp_psram_impl_ap_quad.c
endif
endif
CFLAGS += -Wno-unused-but-set-variable
# additional include pathes required by this module
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_driver_spi/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_psram/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/soc/$(CPU_FAM)/include
include $(RIOTBASE)/Makefile.base

11
cpu/esp32/esp-idf/usb/Makefile
View File

@ -2,13 +2,16 @@ MODULE = esp_idf_usb
# source files to be compiled for this module
ESP32_SDK_SRC = \
components/hal/usb_hal.c \
components/hal/usb_phy_hal.c \
components/soc/$(CPU_FAM)/usb_periph.c \
components/soc/$(CPU_FAM)/usb_phy_periph.c \
components/hal/usb_dwc_hal.c \
components/hal/usb_wrap_hal.c \
components/soc/$(CPU_FAM)/usb_dwc_periph.c \
components/usb/usb_phy.c \
#
ifeq (esp32s3,$(CPU_FAM))
ESP32_SDK_SRC += components/hal/usb_serial_jtag_hal.c
endif
include $(RIOTBASE)/Makefile.base
ESP32_SDK_BIN = $(BINDIR)/$(MODULE)

21
cpu/esp32/esp-idf/wifi/Makefile
View File

@ -1,21 +1,24 @@
MODULE = esp_idf_wifi
# source files to be compiled for this module
ESP32_SDK_SRC = \
components/esp_event/event_send.c \
components/esp_hw_support/port/$(CPU_FAM)/dport_access.c \
components/esp_phy/src/phy_init.c \
components/esp_wifi/$(CPU_FAM)/esp_adapter.c \
components/esp_wifi/src/wifi_init.c \
#
ESP32_SDK_SRC += components/esp_coex/$(CPU_FAM)/esp_coex_adapter.c
ESP32_SDK_SRC += components/esp_wifi/$(CPU_FAM)/esp_adapter.c
ESP32_SDK_SRC += components/esp_wifi/src/wifi_init.c
# additional include pathes required by this module
INCLUDES += -I$(ESP32_SDK_DIR)/components/app_update/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_bootloader_format/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_coex/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_partition/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_phy/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_phy/$(CPU_FAM)/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/tcpip_adapter/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/nvs_flash/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/wpa_supplicant/port/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/wpa_supplicant/esp_supplicant/include
ifneq (,$(filter esp32c3 esp32s2,$(CPU_FAM)))
ESP32_SDK_SRC += components/esp_hw_support/port/$(CPU_FAM)/adc2_init_cal.c
endif
include $(RIOTBASE)/Makefile.base
ESP32_SDK_BIN = $(BINDIR)/$(MODULE)

22
cpu/esp32/esp-idf/wpa_supplicant/esp_idf_wpa_supplicant.mk
View File

@ -5,31 +5,39 @@ INCLUDES += -I$(ESP32_SDK_DIR)/components/wpa_supplicant/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/wpa_supplicant/port/include
INCLUDES += -I$(ESP32_SDK_DIR)/components/wpa_supplicant/src
INCLUDES += -I$(ESP32_SDK_DIR)/components/wpa_supplicant/src/utils
INCLUDES += -I$(ESP32_SDK_DIR)/components/wpa_supplicant/src/crypto
include $(RIOTBASE)/Makefile.base
ESP32_SDK_BIN = $(BINDIR)/$(MODULE)
# definitions for wpa_supplicant from components/wpa_supplicant/component.mk
# definitions for wpa_supplicant from components/wpa_supplicant/CMakeList.txt
CFLAGS += -D__ets__
CFLAGS += -DCONFIG_DPP
CFLAGS += -DCONFIG_CRYPTO_INTERNAL
CFLAGS += -DCONFIG_ECC
CFLAGS += -DCONFIG_FAST_PBKDF2
CFLAGS += -DCONFIG_GMAC
CFLAGS += -DCONFIG_IEEE80211W
CFLAGS += -DCONFIG_NO_RADIUS
CFLAGS += -DCONFIG_SHA256
CFLAGS += -DCONFIG_WNM
CFLAGS += -DCONFIG_WPS_PIN
CFLAGS += -DCONFIG_WPS2
CFLAGS += -DCONFIG_TLSV11
CFLAGS += -DCONFIG_TLSV12
CFLAGS += -DCONFIG_TLS_INTERNAL_CLIENT
CFLAGS += -DCONFIG_WPS
CFLAGS += -DEAP_FAST
CFLAGS += -DEAP_MSCHAPv2
CFLAGS += -DEAP_PEAP
CFLAGS += -DEAP_PEER_METHOD
CFLAGS += -DEAP_TLS
CFLAGS += -DEAP_TTLS
CFLAGS += -DESP_SUPPLICANT
CFLAGS += -DESP32_WORKAROUND
CFLAGS += -DESPRESSIF_USE
CFLAGS += -DESP_PLATFORM
CFLAGS += -DESP_SUPPLICANT
CFLAGS += -DIEEE8021X_EAPOL
CFLAGS += -DUSE_WPA2_TASK
CFLAGS += -DUSE_WPS_TASK
# additional compiler flags to avoid compile errors
CFLAGS += -Wno-strict-aliasing
CFLAGS += -Wno-format-nonliteral
CFLAGS += -Wno-format-security

6
cpu/esp32/esp-idf/wpa_supplicant/esp_supplicant/Makefile
View File

@ -2,9 +2,11 @@ MODULE = esp_idf_wpa_supplicant_esp_supplicant
# source file list to be compiled as configured in component.mk
ESP32_SDK_SRC = \
components/wpa_supplicant/esp_supplicant/src/esp_dpp.c \
components/wpa_supplicant/esp_supplicant/src/esp_common.c \
components/wpa_supplicant/esp_supplicant/src/esp_eap_client.c \
components/wpa_supplicant/esp_supplicant/src/esp_hostap.c \
components/wpa_supplicant/esp_supplicant/src/esp_wpa2.c \
components/wpa_supplicant/esp_supplicant/src/esp_owe.c \
components/wpa_supplicant/esp_supplicant/src/esp_wpa2_api_port.c \
components/wpa_supplicant/esp_supplicant/src/esp_wpa3.c \
components/wpa_supplicant/esp_supplicant/src/esp_wpa_main.c \
components/wpa_supplicant/esp_supplicant/src/esp_wpas_glue.c \

5
cpu/esp32/esp-idf/wpa_supplicant/port/Makefile
View File

@ -1,8 +1,7 @@
MODULE = esp_idf_wpa_supplicant_port
# source file list to be compiled as configured in component.mk
ESP32_SDK_SRC = \
components/wpa_supplicant/port/os_xtensa.c \
#
ESP32_SDK_SRC += components/wpa_supplicant/port/os_xtensa.c
ESP32_SDK_SRC += components/wpa_supplicant/port/eloop.c
include $(ESP_IDF_WPA_SUPPLICANT_PATH)/esp_idf_wpa_supplicant.mk

4
cpu/esp32/esp-idf/wpa_supplicant/src/ap/Makefile
View File

@ -3,7 +3,11 @@ MODULE = esp_idf_wpa_supplicant_ap
# source file list to be compiled as configured in component.mk
ESP32_SDK_SRC = \
components/wpa_supplicant/src/ap/ap_config.c \
components/wpa_supplicant/src/ap/comeback_token.c \
components/wpa_supplicant/src/ap/ieee802_11.c \
components/wpa_supplicant/src/ap/ieee802_1x.c \
components/wpa_supplicant/src/ap/pmksa_cache_auth.c \
components/wpa_supplicant/src/ap/sta_info.c \
components/wpa_supplicant/src/ap/wpa_auth.c \
components/wpa_supplicant/src/ap/wpa_auth_ie.c \
#

3
cpu/esp32/esp-idf/wpa_supplicant/src/common/Makefile
View File

@ -2,7 +2,8 @@ MODULE = esp_idf_wpa_supplicant_common
# source file list to be compiled as configured in component.mk
ESP32_SDK_SRC = \
components/wpa_supplicant/src/common/dpp.c \
components/wpa_supplicant/src/common/dragonfly.c \
components/wpa_supplicant/src/common/ieee802_11_common.c \
components/wpa_supplicant/src/common/sae.c \
components/wpa_supplicant/src/common/wpa_common.c \
#

2
cpu/esp32/esp-idf/wpa_supplicant/src/crypto/Makefile
View File

@ -32,6 +32,7 @@ ESP32_SDK_SRC = \
components/wpa_supplicant/src/crypto/sha1-pbkdf2.c \
components/wpa_supplicant/src/crypto/sha1-prf.c \
components/wpa_supplicant/src/crypto/sha1-tlsprf.c \
components/wpa_supplicant/src/crypto/sha1-tprf.c \
components/wpa_supplicant/src/crypto/sha256.c \
components/wpa_supplicant/src/crypto/sha256-internal.c \
components/wpa_supplicant/src/crypto/sha256-kdf.c \
@ -41,6 +42,7 @@ ESP32_SDK_SRC = \
components/wpa_supplicant/src/crypto/sha384-prf.c \
components/wpa_supplicant/src/crypto/sha384-tlsprf.c \
components/wpa_supplicant/src/crypto/sha512-internal.c \
components/wpa_supplicant/src/crypto/tls_internal.c \
#
include $(ESP_IDF_WPA_SUPPLICANT_PATH)/esp_idf_wpa_supplicant.mk

5
cpu/esp32/esp-idf/wpa_supplicant/src/eap_peer/Makefile
View File

@ -2,9 +2,12 @@ MODULE = esp_idf_wpa_supplicant_eap_peer
# source file list to be compiled as configured in component.mk
ESP32_SDK_SRC = \
components/wpa_supplicant/src/eap_common/eap_wsc_common.c \
components/wpa_supplicant/src/eap_peer/chap.c \
components/wpa_supplicant/src/eap_peer/eap.c \
components/wpa_supplicant/src/eap_peer/eap_common.c \
components/wpa_supplicant/src/eap_peer/eap_fast.c \
components/wpa_supplicant/src/eap_peer/eap_fast_common.c \
components/wpa_supplicant/src/eap_peer/eap_mschapv2.c \
components/wpa_supplicant/src/eap_peer/eap_peap.c \
components/wpa_supplicant/src/eap_peer/eap_peap_common.c \
@ -12,6 +15,8 @@ ESP32_SDK_SRC = \
components/wpa_supplicant/src/eap_peer/eap_tls_common.c \
components/wpa_supplicant/src/eap_peer/eap_ttls.c \
components/wpa_supplicant/src/eap_peer/mschapv2.c \
# eap_fast_pac.c is included by eap_fast.c
# components/wpa_supplicant/src/eap_peer/eap_fast_pac.c \
#
include $(ESP_IDF_WPA_SUPPLICANT_PATH)/esp_idf_wpa_supplicant.mk

5
cpu/esp32/esp-idf/wpa_supplicant/src/tls/Makefile
View File

@ -8,16 +8,13 @@ ESP32_SDK_SRC = \
components/wpa_supplicant/src/tls/pkcs5.c \
components/wpa_supplicant/src/tls/pkcs8.c \
components/wpa_supplicant/src/tls/rsa.c \
components/wpa_supplicant/src/tls/tls_internal.c \
components/wpa_supplicant/src/tls/tlsv1_client.c \
components/wpa_supplicant/src/tls/tlsv1_client_ocsp.c \
components/wpa_supplicant/src/tls/tlsv1_client_read.c \
components/wpa_supplicant/src/tls/tlsv1_client_write.c \
components/wpa_supplicant/src/tls/tlsv1_common.c \
components/wpa_supplicant/src/tls/tlsv1_cred.c \
components/wpa_supplicant/src/tls/tlsv1_record.c \
components/wpa_supplicant/src/tls/tlsv1_server.c \
components/wpa_supplicant/src/tls/tlsv1_server_read.c \
components/wpa_supplicant/src/tls/tlsv1_server_write.c \
components/wpa_supplicant/src/tls/x509v3.c \
#

4
cpu/esp32/esp-idf/wpa_supplicant/src/wps/Makefile
View File

@ -9,8 +9,8 @@ ESP32_SDK_SRC = \
components/wpa_supplicant/src/wps/wps_common.c \
components/wpa_supplicant/src/wps/wps_dev_attr.c \
components/wpa_supplicant/src/wps/wps_enrollee.c \
components/wpa_supplicant/src/wps/wps_registrar.c \
components/wpa_supplicant/src/wps/wps_validate.c \
#
include $(ESP_IDF_WPA_SUPPLICANT_PATH)/esp_idf_wpa_supplicant.mk
CFLAGS += -Wno-format

7
cpu/esp32/esp-lcd/esp_lcd_mcu.c
View File

@ -27,6 +27,7 @@
#include "periph/gpio.h"
#include "ztimer.h"
#include "esp_lcd_common.h"
#include "esp_lcd_panel_io.h"
#include "soc/gpio_reg.h"
@ -57,6 +58,10 @@
static_assert(CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE >= 32,
"CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE mus be at least 32");
static_assert(CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE <= LCD_I80_IO_FORMAT_BUF_SIZE,
"CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE must be less or equal to "
"LCD_I80_IO_FORMAT_BUF_SIZE");
/* ESP32x SoCs support only one LCD peripheral so we can use single instances
* of the following variables */
@ -91,7 +96,7 @@ static void _lcd_ll_mcu_init(lcd_t *dev)
esp_lcd_i80_bus_config_t i80_bus_config = {
.dc_gpio_num = dev->params->dcx_pin,
.wr_gpio_num = dev->params->wrx_pin,
.clk_src = LCD_CLK_SRC_PLL160M,
.clk_src = LCD_CLK_SRC_DEFAULT,
#if IS_USED(MODULE_LCD_PARALLEL_16BIT)
.data_gpio_nums = {
dev->params->d0_pin,

95
cpu/esp32/include/adc_arch.h
View File

@ -34,7 +34,7 @@ extern "C" {
#include "periph/gpio.h"
#include "driver/adc.h"
#include "hal/adc_types.h"
#include "driver/adc_types_legacy.h"
/**
* @brief Attenuations that can be set for ADC lines
@ -47,16 +47,26 @@ typedef enum {
ADC_ATTENUATION_0_DB = ADC_ATTEN_DB_0, /**< full-range is about 1.1 V (Vref) */
ADC_ATTENUATION_3_DB = ADC_ATTEN_DB_2_5, /**< full-range is about 1.5 V */
ADC_ATTENUATION_6_DB = ADC_ATTEN_DB_6, /**< full-range is about 2.2 V */
ADC_ATTENUATION_11_DB = ADC_ATTEN_DB_11, /**< full-range is about 3.3 V */
ADC_ATTENUATION_12_DB = ADC_ATTEN_DB_12, /**< full-range is about 3.3 V */
} adc_attenuation_t;
/**
* @brief Set the attenuation for the ADC line. Default attenuation is 11 dB.
* @brief Attenuation of 11 dB is depcricated and has to be mapped
*
* The define ensures the compatibility with older versions.
*
* @deprecated `ADC_ATTENUATION_11_DB` is deprecated, use
* `ADC_ATTENUATION_12_DB` instead.
*/
#define ADC_ATTENUATION_11_DB ADC_ATTENUATION_12_DB
/**
* @brief Set the attenuation for the ADC line. Default attenuation is 12 dB.
*
* For each ADC line, an attenuation of the input signal can be defined
* separately. This results in different full ranges of the measurable voltage
* at the input. The attenuation can be set to 0 dB, 3 dB, 6 dB and 11 dB,
* with 11 dB being the standard attenuation. Since an ADC input is measured
* at the input. The attenuation can be set to 0 dB, 3 dB, 6 dB and 12 dB,
* with 12 dB being the standard attenuation. Since an ADC input is measured
* against a reference voltage Vref of 1.1 V, approximately the following
* measurement ranges are given when using a corresponding attenuation:
*
@ -64,41 +74,71 @@ typedef enum {
*
* Attenuation | Voltage Range | Symbol
* ----------------|-------------------|----------------------
* 0 dB | 0 ... 1.1V (Vref) | ADC_ATTEN_DB_0
* 2.5 dB | 0 ... 1.5V | ADC_ATTEN_DB_2_5
* 6 dB | 0 ... 2.2V | ADC_ATTEN_DB_6
* 11 dB (default) | 0 ... 3.3V | ADC_ATTEN_DB_11
* 0 dB | 0 ... 1.1V (Vref) | `ADC_ATTEN_DB_0`
* 2.5 dB | 0 ... 1.5V | `ADC_ATTEN_DB_2_5`
* 6 dB | 0 ... 2.2V | `ADC_ATTEN_DB_6`
* 12 dB (default) | 0 ... 3.3V | `ADC_ATTEN_DB_12`
*
* </center>
*
* @note: The reference voltage Vref can vary from ADC unit to ADC unit in
* the range of 1.0V and 1.2V. The Vref of a unit can be routed with
* function *adc_vref_to_gpio* to a GPIO pin.
* @pre #adc_init must have been executed for the line before.
* @note The function has to be executed before @ref adc_sample if required.
* The configured attenuation is then used for all subsequent samples.
*
* @param line ADC line for which the attenuation is set
* @param atten Attenuation, see type definition of *adc_attenuation_t
* @return 0 on success
* @return -1 on error
* @param [in] line ADC line for which the attenuation is set
* @param [in] atten Attenuation, see type definition of @ref adc_attenuation_t
* @retval 0 on success
* @retval -1 on error
*/
int adc_set_attenuation(adc_t line, adc_atten_t atten);
/**
* @brief Output reference voltage of a ADC line to GPIO n
* @brief Get the voltage for a given sample value
*
* The Vref of the ADC unit of the given ADC line is routed to a GPIO pin n.
* The function converts the given sample value as read from the channel
* according to the attenuation set with @ref adc_set_attenuation and the
* resolution used to read the sample with @ref adc_sample. It uses a predefined
* calibration scheme and the calibration parameters that have been burned
* into the eFuses of the ESP32x SoC. If the calibration parameters have not
* been burned into the eFuses and the initialization of the calibration
* fails, a linear conversion according to the predefined voltage
* ranges is used as a fallback.
*
* @note In the case that the initialization of the calibration fails,
* the function returns `-EINVAL` and the value in parameter `voltage`
* is expected to be inaccurate.
* @note For ESP32, the valid voltages start at around 140 mV.
*
* @param [in] line ADC line
* @param [in] sample sample sample as read by adc_read
* @param [out] voltage voltage in mV
* @retval 0 on success
* @retval -EINVAL if the initialization of the calibration failed
*/
int adc_raw_to_voltage(adc_t line, int sample, int *voltage);
#if !DOXYGEN
/**
* @brief Output reference voltage of a ADC line to a GPIO pin
*
* The Vref of the ADC unit for the given ADC line is routed to a GPIO pin.
* This allows to measure the Vref used by the ADC unit to adjusted the
* results of the conversions accordingly.
*
* @warning The function is not supported any longer, use
* @ref adc_raw_to_voltage to get the voltage for a sample value.
*
* @note
* - The given GPIO must be a valid ADC channel of ADC2 unit.
* - For ESP32 and ESP32C3, the given ADC line has to be a channel of ADC2 unit.
* - For ESP32, only the internal reference voltage of ADC2 is given.
*
* @param line ADC line for which Vref of its ADC unit is routed to the GPIO
* @param gpio GPIO to which Vref is routed (ADC2 channel GPIOs only)
* @param [in] line ADC line for which Vref of its ADC unit is routed to the GPIO
* @param [in] gpio GPIO to which Vref is routed (ADC2 channel GPIOs only)
*
* @return 0 on success
* @return -1 on error
* @retval 0 on success
* @retval -1 on error
*/
__attribute__((__deprecated__))
int adc_line_vref_to_gpio(adc_t line, gpio_t gpio);
#if defined(CPU_FAM_ESP32)
@ -107,14 +147,19 @@ int adc_line_vref_to_gpio(adc_t line, gpio_t gpio);
*
* This function is deprecated and will be removed in future versions.
*
* @return 0 on success
* @return -1 on invalid ADC line
* @warning The function is not supported any longer, use
* @ref adc_raw_to_voltage to get the voltage for a sample value.
*
* @retval 0 on success
* @retval -1 on invalid ADC line
*/
__attribute__((__deprecated__))
static inline int adc_vref_to_gpio25(void)
{
return adc_vref_to_gpio(ADC_UNIT_2, GPIO25);
}
#endif
#endif /* !DOXYGEN */
#ifdef __cplusplus
}

10
cpu/esp32/include/adc_arch_private.h
View File

@ -23,14 +23,22 @@
extern "C" {
#endif
#include "hal/adc_types.h"
#include "driver/adc_types_legacy.h"
#include "periph/gpio.h"
#include "soc/soc_caps.h"
#ifndef DOXYGEN /* hide implementation details from doxygen */
#define RTCIO_GPIO(n) n /* n-th RTCIO GPIO */
#define RTCIO_NA UINT8_MAX /* RTCIO pin not available */
#define ADC_UNIT_INV ((adc_unit_t)255) /* Invalid ADC unit ID */
#define ADC_CHANNEL_INV SOC_ADC_MAX_CHANNEL_NUM /* Invalid ADC channel ID */
#define ADC1_CHANNEL_MAX (SOC_ADC_CHANNEL_NUM(ADC_UNIT_1)) /* Number of channels of ADC1 */
#define ADC2_CHANNEL_MAX (SOC_ADC_CHANNEL_NUM(ADC_UNIT_2)) /* Number of channels of ADC2 */
#define ADC_CHANNEL_MAX(u) ((u == ADC_UNIT_1) ? ADC1_CHANNEL_MAX : ADC2_CHANNEL_MAX)
/**
* @brief ADC hardware descriptor (for internal use only)
*/

4
cpu/esp32/include/cpu_conf.h
View File

@ -79,7 +79,7 @@
*/
#if !DOXYGEN && !defined(__ASSEMBLER__)
/* start address of flash pages in CPU address space as determined by the linker */
extern uint8_t _fp_mem_start;
extern uint8_t _fp_mmu_start;
#endif
#define FLASHPAGE_SIZE (4096U) /**< Size of pages (flash sectors) in bytes */
@ -94,7 +94,7 @@ extern uint8_t _fp_mem_start;
/**
* @brief CPU base address for flash page access as determined by the linker
*/
#define CPU_FLASH_BASE ((uint32_t)&_fp_mem_start)
#define CPU_FLASH_BASE ((uint32_t)&_fp_mmu_start)
/** @} */

64
cpu/esp32/include/esp_idf_api/gpio.h
View File

@ -1,64 +0,0 @@
/*
* Copyright (C) 2022 Gunar Schorcht
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
#pragma once
/**
* @ingroup cpu_esp32_esp_idf_api
* @{
*
* @file
* @brief Interface for the ESP-IDF GPIO API
*
* @author Gunar Schorcht <gunar@schorcht.net>
* @}
*/
#include "esp_err.h"
#include "hal/gpio_types.h"
#ifndef DOXYGEN /* Hide implementation details from doxygen */
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name ESP-IDF interface wrapper functions
* @{
*/
esp_err_t esp_idf_gpio_config(const gpio_config_t *cfg);
esp_err_t esp_idf_gpio_reset_pin(gpio_num_t gpio_num);
esp_err_t esp_idf_gpio_intr_enable(gpio_num_t gpio_num);
esp_err_t esp_idf_gpio_intr_disable(gpio_num_t gpio_num);
esp_err_t esp_idf_gpio_set_intr_type(gpio_num_t gpio_num,
gpio_int_type_t intr_type);
esp_err_t esp_idf_gpio_install_isr_service(int intr_alloc_flags);
esp_err_t esp_idf_gpio_isr_handler_add(gpio_num_t gpio_num,
gpio_isr_t isr_handler, void *args);
esp_err_t esp_idf_gpio_wakeup_enable(gpio_num_t gpio_num,
gpio_int_type_t intr_type);
esp_err_t esp_idf_gpio_deep_sleep_hold(void);
esp_err_t esp_idf_gpio_set_drive_capability(gpio_num_t gpio_num,
gpio_drive_cap_t strength);
esp_err_t esp_idf_rtc_gpio_deinit(gpio_num_t gpio_num);
esp_err_t esp_idf_rtc_gpio_pullup_en(gpio_num_t gpio_num);
esp_err_t esp_idf_rtc_gpio_pullup_dis(gpio_num_t gpio_num);
esp_err_t esp_idf_rtc_gpio_pulldown_en(gpio_num_t gpio_num);
esp_err_t esp_idf_rtc_gpio_pulldown_dis(gpio_num_t gpio_num);
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* DOXYGEN */

34
cpu/esp32/include/esp_idf_api/uart.h
View File

@ -1,34 +0,0 @@
/*
* Copyright (C) 2022 Gunar Schorcht
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
#pragma once
/**
* @ingroup cpu_esp32_esp_idf_api
* @{
*
* @file
* @brief Interface for the ESP-IDF UART HAL API
*
* @author Gunar Schorcht <gunar@schorcht.net>
* @}
*/
#ifndef DOXYGEN /* Hide implementation details from doxygen */
#ifdef __cplusplus
extern "C" {
#endif
void esp_idf_uart_set_wakeup_threshold(unsigned uart_num, uint32_t threshold);
#ifdef __cplusplus
}
#endif
#endif /* DOXYGEN */

34
cpu/esp32/include/irq_arch.h
View File

@ -35,24 +35,34 @@ extern "C" {
*
* @{
*/
#define CPU_INUM_RMT 1 /**< Level interrupt with low priority 1 */
/* On Xtensa-based ESP32x SoCs, interrupt 0 is reserved for the WiFi interface
* and interrupt 1 is available. However, since interrupt 0 is not available on
* RISC-V-based ESP32x SoCs, interrupt 1 is used for the WiFi interface instead.
* Therefore, we use interrupt 1 for the RMT peripheral on Xtensa-based ESP32x
* SoCs, but we use interrupt 11 for the RMT peripheral on RISC-V-based ESP32x
* SoCs. Interrupt 11 is reserved for profiling on Xtensa-based ESP32x SoCs. */
#if defined(__XTENSA__)
# define CPU_INUM_RMT 1 /**< Level interrupt with low priority 1 */
#else
# define CPU_INUM_RMT 11 /**< Level interrupt with low priority 1 */
#endif
#define CPU_INUM_GPIO 2 /**< Level interrupt with low priority 1 */
#define CPU_INUM_CAN 3 /**< Level interrupt with low priority 1 */
#define CPU_INUM_UART 4 /**< Level interrupt with low priority 1 */
#define CPU_INUM_USB 8 /**< Level interrupt with low priority 1 */
#define CPU_INUM_BLE 5 /**< Level interrupt with low priority 1 */
#define CPU_INUM_RTT 9 /**< Level interrupt with low priority 1 */
#define CPU_INUM_SERIAL_JTAG 10 /**< Level interrupt with low priority 1 */
#define CPU_INUM_SERIAL_JTAG 10 /**< Edge interrupt with low priority 1 */
#define CPU_INUM_I2C 12 /**< Level interrupt with low priority 1 */
#define CPU_INUM_WDT 13 /**< Level interrupt with low priority 1 */
#define CPU_INUM_SOFTWARE 17 /**< Level interrupt with low priority 1 */
#define CPU_INUM_UART 13 /**< Level interrupt with low priority 1 */
#define CPU_INUM_CAN 17 /**< Level interrupt with low priority 1 */
#define CPU_INUM_ETH 18 /**< Level interrupt with low priority 1 */
#define CPU_INUM_LCD 18 /**< Level interrupt with low priority 1 */
#define CPU_INUM_TIMER 19 /**< Level interrupt with medium priority 2 */
#define CPU_INUM_USB 18 /**< Level interrupt with low priority 1 */
#define CPU_INUM_LCDCAM 19 /**< Level interrupt with medium priority 2 */
#define CPU_INUM_FRC2 20 /**< Level interrupt with medium priority 2 */
#define CPU_INUM_SYSTIMER 20 /**< Level interrupt with medium priority 2 */
#define CPU_INUM_BLE 21 /**< Level interrupt with medium priority 2 */
#define CPU_INUM_SDMMC 23 /**< Level interrupt with medium priority 2 */
#define CPU_INUM_CACHEERR 25 /**< Level interrupt with high priority 4 */
#define CPU_INUM_SDMMC 21 /**< Level interrupt with medium priority 2 */
#define CPU_INUM_TIMER 22 /**< Edge interrupt with medium priority 2 */
#define CPU_INUM_WDT 23 /**< Level interrupt with medium priority 3 */
#define CPU_INUM_SOFTWARE 29 /**< Software interrupt with medium priority 3 */
/** @} */
/**

72
cpu/esp32/include/periph_cpu.h
View File

@ -27,6 +27,8 @@
#include "soc/periph_defs.h"
#include "soc/soc_caps.h"
#include "modules.h"
#ifdef __cplusplus
extern "C" {
#endif
@ -184,13 +186,20 @@ typedef enum {
GPIO_PULL_STRONGEST = 0
} gpio_pull_strength_t;
/*
* This include is placed here by intention to avoid type name conflicts.
* Having the macros HAVE_GPIO_* defined before including this file allows to
* use these macros in `hal/gpio_types.h` to decide whether to use the
* ESP-IDF types when compiling ESP-IDF modules or to use the RIOT types
* when compiling RIOT source code.
*/
#include "hal/gpio_types.h"
#define HAVE_GPIO_PULL_T
typedef enum {
GPIO_FLOATING = 0,
GPIO_PULL_UP = 1,
GPIO_PULL_DOWN = 2,
GPIO_PULL_KEEP = 3 /*< not supported */
} gpio_pull_t;
typedef gpio_pull_mode_t gpio_pull_t;
#define GPIO_PULL_UP GPIO_PULLUP_ONLY
#define GPIO_PULL_DOWN GPIO_PULLDOWN_ONLY
#define GPIO_PULL_KEEP GPIO_PULLUP_PULLDOWN
/**
* @brief Current an output pin can drive in active and sleep modes
@ -329,18 +338,6 @@ union gpio_conf_esp32 {
* @note The reference voltage Vref can vary from device to device in the range
* of 1.0V and 1.2V.
*
* The Vref of a device can be read at a predefined GPIO with the function
* #adc_line_vref_to_gpio. The results of the ADC input can then be adjusted
* accordingly.
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~{.c}
* extern int adc_line_vref_to_gpio(adc_t line, gpio_t gpio);
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
* For the GPIO that can be used with this function, see:
*
* - \ref esp32_adc_channels_esp32 "ESP32"
* - \ref esp32_adc_channels_esp32c3 "ESP32-C3"
* - \ref esp32_adc_channels_esp32s3 "ESP32-S3"
*
* @{
*/
@ -914,9 +911,9 @@ typedef struct {
#endif
/** Timer group used for system time */
#define TIMER_SYSTEM_GROUP TIMER_GROUP_0
/** Index of the timer in the timer timer group used for system time */
#define TIMER_SYSTEM_INDEX TIMER_0
#define TIMER_SYSTEM_GROUP 0 /* formerly TIMER_GROUP_0 */
/** Index of the timer in the timer group used for system time */
#define TIMER_SYSTEM_INDEX 0 /* formerly TIMER_0 */
/** System time interrupt source */
#define TIMER_SYSTEM_INT_SRC ETS_TG0_T0_LEVEL_INTR_SOURCE
@ -977,6 +974,39 @@ typedef struct {
gpio_t rxd; /**< GPIO used as RxD pin */
} uart_conf_t;
#ifndef DOXYGEN
/**
* @brief Override UART stop bits
*/
typedef enum {
UART_STOP_BITS_1 = 0x1, /*!< stop bit: 1bit*/
UART_STOP_BITS_1_5 = 0x2, /*!< stop bit: 1.5bits*/
UART_STOP_BITS_2 = 0x3, /*!< stop bit: 2bits*/
} uart_stop_bits_t;
#define HAVE_UART_STOP_BITS_T
/**
* @brief Marker for unsupported UART parity modes
*/
#define UART_MODE_UNSUPPORTED 0xf0
/**
* @brief Override UART parity values
*/
typedef enum {
UART_PARITY_NONE = 0x0,
UART_PARITY_EVEN = 0x2,
UART_PARITY_ODD = 0x3,
UART_PARITY_MARK = UART_MODE_UNSUPPORTED | 0,
UART_PARITY_SPACE = UART_MODE_UNSUPPORTED | 1,
} uart_parity_t;
#define UART_PARITY_DISABLE UART_PARITY_NONE
#define HAVE_UART_PARITY_T
#endif /* !DOXYGEN */
/**
* @brief Maximum number of UART interfaces
*/

3
cpu/esp32/include/periph_cpu_esp32.h
View File

@ -25,7 +25,7 @@ extern "C" {
#endif
/** Mapping configured ESP32 default clock to CLOCK_CORECLOCK define */
#define CLOCK_CORECLOCK (1000000UL * CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ)
#define CLOCK_CORECLOCK (1000000UL * CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ)
/**
* @brief CPU cycles per busy wait loop
@ -96,7 +96,6 @@ extern "C" {
* - ADC2 is also used by the WiFi module. The GPIOs connected to ADC2 are
* therefore not available as ADC channels if the modules `esp_wifi` or
* `esp_now` are used.
* - Vref can be read with function #adc_line_vref_to_gpio at GPIO25.
*/
/**

5
cpu/esp32/include/periph_cpu_esp32c3.h
View File

@ -25,7 +25,7 @@ extern "C" {
#endif
/** Mapping configured ESP32-C3 default clock to CLOCK_CORECLOCK define */
#define CLOCK_CORECLOCK (1000000UL * CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ)
#define CLOCK_CORECLOCK (1000000UL * CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ)
/**
* @brief CPU cycles per busy wait loop
@ -72,10 +72,9 @@ extern "C" {
* The maximum number of ADC channels #ADC_NUMOF_MAX is 6.
*
* @note
* - ADC2 is also used by the WiFi module. The GPIOs connected to ADC2 are
* ADC2 is also used by the WiFi module. The GPIOs connected to ADC2 are
* therefore not available as ADC channels if the modules `esp_wifi` or
* `esp_now` are used.
* - Vref can be read with function #adc_line_vref_to_gpio at GPIO5.
*/
/**

4
cpu/esp32/include/periph_cpu_esp32s2.h
View File

@ -25,7 +25,7 @@ extern "C" {
#endif
/** Mapping configured ESP32-S2 default clock to CLOCK_CORECLOCK define */
#define CLOCK_CORECLOCK (1000000UL * CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ)
#define CLOCK_CORECLOCK (1000000UL * CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ)
/**
* @brief CPU cycles per busy wait loop
@ -95,8 +95,6 @@ extern "C" {
* - ADC2 is also used by the WiFi module. The GPIOs connected to ADC2 are
* therefore not available as ADC channels if the modules `esp_wifi` or
* `esp_now` are used.
* - Vref can be read with function #adc_line_vref_to_gpio at an ADC2 channel,
* that is at GPIO11 ... GPIO20.
* - GPIO3 is a strapping pin und shouldn't be used as ADC channel
*/

4
cpu/esp32/include/periph_cpu_esp32s3.h
View File

@ -23,7 +23,7 @@ extern "C" {
#endif
/** Mapping configured ESP32-S3 default clock to CLOCK_CORECLOCK define */
#define CLOCK_CORECLOCK (1000000UL * CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ)
#define CLOCK_CORECLOCK (1000000UL * CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ)
/**
* @brief CPU cycles per busy wait loop
@ -95,8 +95,6 @@ extern "C" {
* - ADC2 is also used by the WiFi module. The GPIOs connected to ADC2 are
* therefore not available as ADC channels if the modules `esp_wifi` or
* `esp_now` are used.
* - Vref can be read with function #adc_line_vref_to_gpio at an ADC2 channel,
* that is at GPIO11 ... GPIO20.
* - GPIO3 is a strapping pin und shouldn't be used as ADC channel
*/

318
cpu/esp32/include/sdkconfig.h
View File

@ -21,15 +21,6 @@
* @author Gunar Schorcht <gunar@schorcht.net>
*/
/*
* Some files in ESP-IDF use functions from `stdlib.h` without including the
* header. To avoid having to patch all these files, `stdlib.h` is included
* in this header file, which in turn is included by every ESP-IDF file.
*/
#if !defined(__ASSEMBLER__) && !defined(LD_FILE_GEN)
#include <stdlib.h>
#endif
/*
* The SoC capability definitions are often included indirectly in the
* ESP-IDF files, although all ESP-IDF files require them. Since not all
@ -38,7 +29,9 @@
* capabilities are included in this file and are thus available to all
* ESP-IDF files. This avoids to update vendor code.
*/
#include "soc/soc_caps.h"
#ifndef LD_FILE_GEN
# include "soc/soc_caps.h"
#endif
/**
* @brief SDK version number
@ -46,7 +39,7 @@
* Determined with `git describe --tags` in `$ESP32_SDK_DIR`
*/
#if !defined(IDF_VER)
#include "esp_idf_ver.h"
# include "esp_idf_ver.h"
#endif
#ifndef DOXYGEN
@ -58,25 +51,27 @@
* can be overridden by an application specific configuration.
*/
#ifdef CONFIG_CONSOLE_UART_NUM
#define CONFIG_ESP_CONSOLE_UART_NUM CONFIG_CONSOLE_UART_NUM
# define CONFIG_ESP_CONSOLE_UART_NUM CONFIG_CONSOLE_UART_NUM
#else
#define CONFIG_ESP_CONSOLE_UART_NUM 0
# define CONFIG_ESP_CONSOLE_UART_NUM 0
#endif
#define CONFIG_ESP_CONSOLE_UART_BAUDRATE STDIO_UART_BAUDRATE
#define CONFIG_ESP_CONSOLE_UART_BAUDRATE STDIO_UART_BAUDRATE
#define CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM CONFIG_ESP_CONSOLE_UART_NUM
/**
* Log output configuration (DO NOT CHANGE)
*/
#ifndef CONFIG_LOG_DEFAULT_LEVEL
#define CONFIG_LOG_DEFAULT_LEVEL LOG_LEVEL
# define CONFIG_LOG_DEFAULT_LEVEL LOG_LEVEL
#endif
#define CONFIG_LOG_MAXIMUM_LEVEL LOG_LEVEL
#define CONFIG_LOG_MAXIMUM_LEVEL LOG_LEVEL
/**
* System specific configuration (DO NOT CHANGE)
*/
#ifdef MODULE_NEWLIB_NANO
#define CONFIG_NEWLIB_NANO_FORMAT 1
#if MODULE_NEWLIB_NANO
# define CONFIG_NEWLIB_NANO_FORMAT 1
#endif
#define CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 1
@ -87,12 +82,18 @@
#define CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER 1
#define CONFIG_ESP_TIMER_TASK_STACK_SIZE 3584
#define CONFIG_ESP_TIMER_INTERRUPT_LEVEL 1
#define CONFIG_ESP_TIMER_TASK_AFFINITY 0
#define CONFIG_ESP_TIMER_ISR_AFFINITY_CPU0 1
#define CONFIG_TIMER_TASK_STACK_SIZE CONFIG_ESP_TIMER_TASK_STACK_SIZE
#define CONFIG_APP_BUILD_TYPE_APP_2NDBOOT 1
#define CONFIG_APP_BUILD_GENERATE_BINARIES 1
#define CONFIG_APP_BUILD_BOOTLOADER 1
#define CONFIG_APP_BUILD_USE_FLASH_SECTIONS 1
#define CONFIG_APP_COMPILE_TIME_DATE 1
#define CONFIG_APP_EXCLUDE_PROJECT_VER_VAR 1
#define CONFIG_APP_RETRIEVE_LEN_ELF_SHA 9
#define CONFIG_PARTITION_TABLE_CUSTOM_FILENAME "partitions.csv"
#define CONFIG_PARTITION_TABLE_FILENAME "partitions_singleapp.csv"
@ -102,34 +103,38 @@
/**
* BLE driver configuration (DO NOT CHANGE)
*/
#ifdef MODULE_ESP_BLE
#define CONFIG_ESP32_WIFI_ENABLED 1 /* WiFi module has to be enabled */
#define CONFIG_BT_ENABLED 1
#define CONFIG_BT_CONTROLLER_ONLY 1
#else
#define CONFIG_BT_ENABLED 0
#if MODULE_ESP_BLE
# define CONFIG_BT_ENABLED 1
# define CONFIG_BT_CONTROLLER_ENABLED 1
# define CONFIG_BT_CONTROLLER_ONLY 1
# define CONFIG_SOC_BT_SUPPORTED SOC_BT_SUPPORTED
# define CONFIG_SOC_PM_SUPPORT_BT_PD SOC_PM_SUPPORT_BT_PD
# define CONFIG_SOC_PM_SUPPORT_BT_WAKEUP SOC_PM_SUPPORT_BT_WAKEUP
#endif
/**
* SPI RAM configuration (DO NOT CHANGE)
*/
#ifdef MODULE_ESP_SPI_RAM
#define CONFIG_SPIRAM_TYPE_AUTO 1
#define CONFIG_SPIRAM_SIZE -1
#define CONFIG_SPIRAM_SPEED_40M 1
#define CONFIG_SPIRAM 1
#define CONFIG_SPIRAM_BOOT_INIT 1
#define CONFIG_SPIRAM_USE_MALLOC 0 /* using malloc requires QStaticQueue */
#define CONFIG_SPIRAM_MEMTEST 1
#define CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL 16384
#define CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL 32768
#if MODULE_ESP_SPI_RAM
# define CONFIG_SPIRAM 1
# define CONFIG_SPIRAM_TYPE_AUTO 1
# define CONFIG_SPIRAM_SIZE -1
# define CONFIG_SPIRAM_SPEED_40M 1
# define CONFIG_SPIRAM_SPEED 40
# define CONFIG_SPIRAM_BOOT_INIT 1
# define CONFIG_SPIRAM_USE_MALLOC 1 /* using malloc requires QStaticQueue */
# define CONFIG_SPIRAM_USE_CAPS_ALLOC 0 /* using cap instead of malloc */
# define CONFIG_SPIRAM_MEMTEST 1
# define CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL 16384
# define CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL 32768
# define CONFIG_SOC_SPIRAM_SUPPORTED SOC_SPIRAM_SUPPORTED
# define CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND 1
#endif
/**
* SPI Flash driver configuration (DO NOT CHANGE)
*/
#define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1
#define CONFIG_SPI_FLASH_USE_LEGACY_IMPL 1
#define CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS 1
#define CONFIG_SPI_FLASH_YIELD_DURING_ERASE 1
#define CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS 20
@ -143,11 +148,20 @@
#define CONFIG_SPI_FLASH_SUPPORT_TH_CHIP 1
#define CONFIG_SPI_FLASH_SUPPORT_MXIC_OPI_CHIP 1
/**
* RTC Clock configuration
*/
#if MODULE_ESP_RTC_TIMER_32K
# define CONFIG_RTC_CLK_SRC_EXT_CRYS 1
#else
# define CONFIG_RTC_CLK_SRC_INT_RC 1
#endif
/**
* Ethernet driver configuration (DO NOT CHANGE)
*/
#ifdef MODULE_ESP_ETH
#define CONFIG_ETH_ENABLED 1
#if MODULE_ESP_ETH
# define CONFIG_ETH_ENABLED 1
#endif
/**
@ -157,78 +171,114 @@
!defined(CONFIG_FLASHMODE_DIO) && \
!defined(CONFIG_FLASHMODE_QOUT) && \
!defined(CONFIG_FLASHMODE_QIO)
#error "Flash mode not configured"
# error "Flash mode not configured"
#endif
/**
* Wi-Fi driver configuration (DO NOT CHANGE)
*/
#ifdef MODULE_ESP_WIFI_ANY
#define CONFIG_ESP32_WIFI_ENABLED 1
#define CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM 10
#define CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM 32
#define CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER 1
#define CONFIG_ESP32_WIFI_TX_BUFFER_TYPE 1
#define CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM 32
#define CONFIG_ESP32_WIFI_CACHE_TX_BUFFER_NUM 32 /* required when CONFIG_SPIRAM_USE_MALLOC=0 */
#define CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED 1
#define CONFIG_ESP32_WIFI_TX_BA_WIN 6
#define CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED 1
#define CONFIG_ESP32_WIFI_RX_BA_WIN 6
#if defined(MODULE_ESP_IDF_NVS_FLASH) && !defined(CPU_FAM_ESP32C3)
#define CONFIG_ESP32_WIFI_NVS_ENABLED 1
#endif
#define CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0 1
#define CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN 752
#define CONFIG_ESP32_WIFI_MGMT_SBUF_NUM 32
#define CONFIG_ESP32_WIFI_IRAM_OPT 1
#define CONFIG_ESP32_WIFI_RX_IRAM_OPT 1
#define CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE 1
#if defined(MODULE_ESP_WIFI_AP) || defined(MODULE_ESP_NOW)
#define CONFIG_ESP_WIFI_SOFTAP_SUPPORT 1
#endif
#ifdef MODULE_ESP_BLE
#define CONFIG_ESP32_WIFI_SW_COEXIST_ENABLE 1
#endif
#if MODULE_ESP_WIFI_ANY
# define CONFIG_ESP_WIFI_ENABLED 1
# define CONFIG_ESP_WIFI_AMPDU_RX_ENABLED 1
# define CONFIG_ESP_WIFI_AMPDU_TX_ENABLED 1
# define CONFIG_ESP_WIFI_AUTH_WPA2_PSK 1
# define CONFIG_ESP_WIFI_CACHE_TX_BUFFER_NUM 32
# define CONFIG_ESP_WIFI_DYNAMIC_RX_BUFFER_NUM 32
# define CONFIG_ESP_WIFI_DYNAMIC_RX_MGMT_BUF 0
# define CONFIG_ESP_WIFI_DYNAMIC_TX_BUFFER 1
# define CONFIG_ESP_WIFI_DYNAMIC_TX_BUFFER_NUM 32
# define CONFIG_ESP_WIFI_ENABLE_SAE_PK 0 /* default 1 for WPA3 */
# define CONFIG_ESP_WIFI_ENABLE_WPA3_OWE_STA 0 /* default 1 for WPA3 */
# define CONFIG_ESP_WIFI_ENABLE_WPA3_SAE 0 /* default 1 for WPA3 */
# define CONFIG_ESP_WIFI_ESPNOW_MAX_ENCRYPT_NUM 7
# define CONFIG_ESP_WIFI_GMAC_SUPPORT 1
# define CONFIG_ESP_WIFI_IRAM_OPT 0 /* default 1 */
# define CONFIG_ESP_WIFI_MBEDTLS_CRYPTO 0 /* default 1 for WPA3 */
# define CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT 0 /* default 1 for WPA3 */
# define CONFIG_ESP_WIFI_MGMT_SBUF_NUM 32
# define CONFIG_ESP_WIFI_NVS_ENABLED MODULE_ESP_IDF_NVS_FLASH
# define CONFIG_ESP_WIFI_PW_ID ""
# define CONFIG_ESP_WIFI_RX_BA_WIN 6
# define CONFIG_ESP_WIFI_RX_IRAM_OPT 0 /* default 1 */
# define CONFIG_ESP_WIFI_RX_MGMT_BUF_NUM_DEF 5
# define CONFIG_ESP_WIFI_SOFTAP_BEACON_MAX_LEN 752
# define CONFIG_ESP_WIFI_STA_DISCONNECTED_PM_ENABLE 1
# define CONFIG_ESP_WIFI_STATIC_RX_BUFFER_NUM 10
# define CONFIG_ESP_WIFI_STATIC_RX_MGMT_BUFFER 1
# define CONFIG_ESP_WIFI_TASK_PINNED_TO_CORE_0 1
# define CONFIG_ESP_WIFI_TX_BA_WIN 6
# define CONFIG_ESP_WIFI_TX_BUFFER_TYPE 1
# define CONFIG_CRYPTO_INTERNAL 1
# if MODULE_ESP_WIFI_AP || MODULE_ESP_NOW
# define CONFIG_ESP_WIFI_SOFTAP_SUPPORT 1
# endif
# if MODULE_ESP_WIFI_ENTERPRISE
# define CONFIG_ESP_WIFI_ENTERPRISE_SUPPORT 1
# endif
#endif
#define CONFIG_ESP_WIFI_SLP_DEFAULT_MAX_ACTIVE_TIME 10
#define CONFIG_ESP_WIFI_SLP_DEFAULT_MIN_ACTIVE_TIME 50
#define CONFIG_ESP_WIFI_SLP_DEFAULT_WAIT_BROADCAST_DATA_TIME 15
/**
* PHY configuration
*/
#if MODULE_ESP_IDF_NVS_ENABLED
#define CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE 1
#if SOC_PHY_SUPPORTED
# define CONFIG_ESP_PHY_ENABLED 1
# define CONFIG_ESP_PHY_CALIBRATION_MODE 0
# define CONFIG_ESP_PHY_MAX_TX_POWER 20
# define CONFIG_ESP_PHY_MAX_WIFI_TX_POWER 20
# define CONFIG_ESP_PHY_RF_CAL_PARTIAL 1
# if MODULE_ESP_IDF_NVS_FLASH
# define CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE 1
# endif
#endif
#define CONFIG_ESP_PHY_MAX_TX_POWER 20
#define CONFIG_ESP_PHY_MAX_WIFI_TX_POWER 20
#define CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE
#define CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER CONFIG_ESP_PHY_MAX_WIFI_TX_POWER
/**
* Coexist configuration (DO NOT CHANGE)
*/
#if !SOC_WIRELESS_HOST_SUPPORTED
# define CONFIG_ESP_COEX_ENABLED 1
# if CONFIG_ESP_WIFI_ENABLED && CONFIG_BT_ENABLED
# define CONFIG_ESP_COEX_SW_COEXIST_ENABLE 1
# endif
# if 0
/* TODO:
* CONFIG_SW_COEXIST_ENABLE is deprecated but still used in code.
* It is not defined in IDF sdkconfigs and does not work if defined. */
# define CONFIG_SW_COEXIST_ENABLE 1
# endif
#endif /* !SOC_WIRELESS_HOST_SUPPORTED */
/**
* Flashpage configuration
*/
#ifndef CONFIG_ESP_FLASHPAGE_CAPACITY
#ifdef MODULE_PERIPH_FLASHPAGE
#if CONFIG_ESP_FLASHPAGE_CAPACITY_64K
#define CONFIG_ESP_FLASHPAGE_CAPACITY 0x10000
#elif CONFIG_ESP_FLASHPAGE_CAPACITY_128K
#define CONFIG_ESP_FLASHPAGE_CAPACITY 0x20000
#elif CONFIG_ESP_FLASHPAGE_CAPACITY_256K
#define CONFIG_ESP_FLASHPAGE_CAPACITY 0x40000
#elif CONFIG_ESP_FLASHPAGE_CAPACITY_512K
#define CONFIG_ESP_FLASHPAGE_CAPACITY 0x80000
#elif CONFIG_ESP_FLASHPAGE_CAPACITY_1M
#define CONFIG_ESP_FLASHPAGE_CAPACITY 0x100000
#elif CONFIG_ESP_FLASHPAGE_CAPACITY_2M
#define CONFIG_ESP_FLASHPAGE_CAPACITY 0x200000
#else
#define CONFIG_ESP_FLASHPAGE_CAPACITY 0x80000
#endif
#else /* MODULE_PERIPH_FLASHPAGE_IN_ADDRESS_SPACE */
#define CONFIG_ESP_FLASHPAGE_CAPACITY 0x0
#endif /* MODULE_PERIPH_FLASHPAGE_IN_ADDRESS_SPACE */
#if MODULE_PERIPH_FLASHPAGE
# if CONFIG_ESP_FLASHPAGE_CAPACITY_64K
# define CONFIG_ESP_FLASHPAGE_CAPACITY 0x10000
# elif CONFIG_ESP_FLASHPAGE_CAPACITY_128K
# define CONFIG_ESP_FLASHPAGE_CAPACITY 0x20000
# elif CONFIG_ESP_FLASHPAGE_CAPACITY_256K
# define CONFIG_ESP_FLASHPAGE_CAPACITY 0x40000
# elif CONFIG_ESP_FLASHPAGE_CAPACITY_512K
# define CONFIG_ESP_FLASHPAGE_CAPACITY 0x80000
# elif CONFIG_ESP_FLASHPAGE_CAPACITY_1M
# define CONFIG_ESP_FLASHPAGE_CAPACITY 0x100000
# elif CONFIG_ESP_FLASHPAGE_CAPACITY_2M
# define CONFIG_ESP_FLASHPAGE_CAPACITY 0x200000
# else
# define CONFIG_ESP_FLASHPAGE_CAPACITY 0x80000
# endif
#else /* MODULE_PERIPH_FLASHPAGE */
# define CONFIG_ESP_FLASHPAGE_CAPACITY 0x0
#endif /* MODULE_PERIPH_FLASHPAGE */
#endif /* !CONFIG_ESP_FLASHPAGE_CAPACITY */
@ -236,30 +286,92 @@
* LCD driver configuration
*/
#if MODULE_ESP_IDF_LCD
#ifndef CONFIG_LCD_DATA_BUF_SIZE
#define CONFIG_LCD_DATA_BUF_SIZE 512
# ifndef CONFIG_LCD_DATA_BUF_SIZE
# define CONFIG_LCD_DATA_BUF_SIZE 512
# endif
# define CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE CONFIG_LCD_DATA_BUF_SIZE
#endif
#define CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE CONFIG_LCD_DATA_BUF_SIZE
#endif
#endif /* DOXYGEN */
/**
* @brief Include ESP32x family specific SDK configuration
*/
#if defined(CPU_FAM_ESP32)
#include "sdkconfig_esp32.h"
# include "sdkconfig_esp32.h"
#elif defined(CPU_FAM_ESP32C3)
#include "sdkconfig_esp32c3.h"
# include "sdkconfig_esp32c3.h"
#elif defined(CPU_FAM_ESP32S2)
#include "sdkconfig_esp32s2.h"
# include "sdkconfig_esp32s2.h"
#elif defined(CPU_FAM_ESP32S3)
#include "sdkconfig_esp32s3.h"
# include "sdkconfig_esp32s3.h"
#else
#error "ESP32x family implementation missing"
# error "ESP32x family implementation missing"
#endif
#ifndef CONFIG_MMU_PAGE_SIZE
# define CONFIG_MMU_PAGE_SIZE_64KB 1
# define CONFIG_MMU_PAGE_SIZE 0x10000
#endif
#ifndef CONFIG_FREERTOS_NUMBER_OF_CORES
# define CONFIG_FREERTOS_NUMBER_OF_CORES 1
#endif
#define CONFIG_ESP_DEBUG_OCDAWARE 1
#define CONFIG_ADC_SUPPRESS_DEPRECATE_WARN 1
#define CONFIG_HEAP_POISONING_DISABLED 1
#define CONFIG_HEAP_TRACING_OFF 1
#define CONFIG_LOG_TAG_LEVEL_CACHE_BINARY_MIN_HEAP 1
#define CONFIG_ULP_COPROC_RESERVE_MEM 0
#ifdef SOC_RTC_MEM_SUPPORTED
# define CONFIG_SOC_RTC_MEM_SUPPORTED 1
#endif
#ifdef SOC_RTC_FAST_MEM_SUPPORTED
# define CONFIG_SOC_RTC_FAST_MEM_SUPPORTED 1
#endif
#ifdef SOC_RTC_SLOW_SUPPORTED
# define CONFIG_SOC_RTC_SLOW_MEM_SUPPORTED 1
#endif
/**
* SDMMC Host configuration
*/
#ifdef SOC_SDMMC_HOST_SUPPORTED
# define CONFIG_SOC_SDMMC_HOST_SUPPORTED SOC_SDMMC_HOST_SUPPORTED
# define CONFIG_SOC_SDMMC_DELAY_PHASE_NUM SOC_SDMMC_DELAY_PHASE_NUM
# define CONFIG_SOC_SDMMC_NUM_SLOTS SOC_SDMMC_NUM_SLOTS
# define CONFIG_SOC_SDMMC_SUPPORT_XTAL_CLOCK SOC_SDMMC_SUPPORT_XTAL_CLOCK
# define CONFIG_SOC_SDMMC_USE_GPIO_MATRIX SOC_SDMMC_USE_GPIO_MATRIX
# define CONFIG_SOC_SDMMC_USE_IOMUX SOC_SDMMC_USE_IOMUX
#endif /* SOC_SDMMC_HOST_SUPPORTED */
/**
* USB Serial/JTAG configuration
*/
#ifdef SOC_USB_SERIAL_JTAG_SUPPORTED
# ifndef CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG
# define CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG 1
# endif
# ifndef CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
# define CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG 0
# endif
# define CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED (CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG || \
CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG)
# define CONFIG_SOC_EFUSE_DIS_USB_JTAG SOC_EFUSE_DIS_USB_JTAG
# define CONFIG_SOC_EFUSE_HARD_DIS_JTAG SOC_EFUSE_HARD_DIS_JTAG
# define CONFIG_SOC_EFUSE_SOFT_DIS_JTAG SOC_EFUSE_SOFT_DIS_JTAG
# define CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED 1
# define CONFIG_USJ_ENABLE_USB_SERIAL_JTAG CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED
#endif /* SOC_USB_SERIAL_JTAG_SUPPORTED */
/* should be RIOT_APPLICATION but PROJECT_NAME must be less than 24 characters */
#define PROJECT_NAME "RIOT-OS Application"
#endif /* DOXYGEN */
#ifdef __cplusplus
extern "C" {
#endif

181
cpu/esp32/include/sdkconfig_esp32.h
View File

@ -34,41 +34,50 @@ extern "C" {
/* Mapping of Kconfig defines to the respective enumeration values */
#if CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_2
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 2
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 2
#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_5
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 5
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 5
#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_10
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 10
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 10
#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_20
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 20
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 20
#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_40
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 40
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 40
#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_80
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 80
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 80
#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_160
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 160
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 160
#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_240
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 240
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 240
#endif
/**
* @brief Defines the CPU frequency [values = 2, 5, 10, 20, 40, 80, 160, 240]
*/
#ifndef CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 80
#ifndef CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 80
#endif
/** @} */
/**
* ESP32 specific RTC clock configuration
*/
#define CONFIG_ESP32_RTC_CLK_CAL_CYCLES (8 * 1024)
#define CONFIG_RTC_CLK_CAL_CYCLES 1024
#ifdef MODULE_ESP_RTC_TIMER_32K
# define CONFIG_RTC_EXT_CRYST_ADDIT_CURRENT_NONE 1
# define CONFIG_RTC_XTAL_CAL_RETRY 1
# define CONFIG_ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES 5
#endif
/**
* ESP32 specific EFUSE configuration
*/
#define CONFIG_EFUSE_MAX_BLK_LEN 192
#define CONFIG_EFUSE_CODE_SCHEME_COMPAT_3_4 1
#define CONFIG_ESP_EFUSE_BLOCK_REV_MIN_FULL 0
#define CONFIG_ESP_EFUSE_BLOCK_REV_MAX_FULL 99
/**
* ESP32 specific MAC configuration
@ -82,38 +91,34 @@ extern "C" {
/**
* ESP32 specific system configuration (DO NOT CHANGE)
*/
#define CONFIG_ESP_TIMER_IMPL_FRC2 1
#define CONFIG_ESP_CONSOLE_MULTIPLE_UART 1
#define CONFIG_ESP32_DEBUG_OCDAWARE 1
#define CONFIG_ESP32_REV_MIN 0
#define CONFIG_ESP32_BROWNOUT_DET 1
#define CONFIG_ESP32_BROWNOUT_DET_LVL 0
#define CONFIG_BROWNOUT_DET CONFIG_ESP32_BROWNOUT_DET
#define CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY 2000
#define CONFIG_ESP32_TRACEMEM_RESERVE_DRAM 0x0
#define CONFIG_ESP32_ULP_COPROC_RESERVE_MEM 0
#define CONFIG_ESP_BROWNOUT_DET 1
#define CONFIG_ESP_BROWNOUT_DET_LVL 0
#define CONFIG_ESP_CONSOLE_MULTIPLE_UART 1
#define CONFIG_ESP_DEBUG_OCDAWARE 1
#define CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY 2000
#define CONFIG_ULP_COPROC_RESERVE_MEM 0
/**
* ESP32 specific sleep configuration (DO NOT CHANGE)
*/
#define CONFIG_ESP_SLEEP_RTC_BUS_ISO_WORKAROUND 1
#define CONFIG_ESP_SLEEP_RTC_BUS_ISO_WORKAROUND 1
#define CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY 2000
/**
* ESP32 specific ADC calibration
*/
#define CONFIG_ADC_CAL_EFUSE_TP_ENABLE 1
#define CONFIG_ADC_CAL_EFUSE_VREF_ENABLE 1
#define CONFIG_ADC_CAL_LUT_ENABLE 1
#define CONFIG_ADC_CALI_EFUSE_TP_ENABLE 1
#define CONFIG_ADC_CALI_EFUSE_VREF_ENABLE 1
#define CONFIG_ADC_CALI_LUT_ENABLE 1
/**
* ESP32 specific PHY configuration
*/
#define CONFIG_ESP_PHY_REDUCE_TX_POWER 1
#define CONFIG_ESP32_REDUCE_PHY_TX_POWER CONFIG_ESP_PHY_REDUCE_TX_POWER
#define CONFIG_REDUCE_PHY_TX_POWER CONFIG_ESP_PHY_REDUCE_TX_POWER
/**
* ESP32 specific XTAL configuration
@ -121,93 +126,77 @@ extern "C" {
* Main clock crystal frequency (MHz). Zero means to auto-configure.
* This is configured at the board level, defaulting to 40.
*/
#ifndef CONFIG_ESP32_XTAL_FREQ
#define CONFIG_ESP32_XTAL_FREQ 0
#ifndef CONFIG_XTAL_FREQ
# define CONFIG_XTAL_FREQ 0
#endif
#ifdef MODULE_ESP_RTC_TIMER_32K
#define CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS 1
#endif
#define CONFIG_ESP32_RTC_XTAL_BOOTSTRAP_CYCLES 100
/**
* ESP32 specific SPI RAM configuration
*/
#ifdef MODULE_ESP_SPI_RAM
#define CONFIG_ESP32_SPIRAM_SUPPORT 1
#define CONFIG_D0WD_PSRAM_CLK_IO 17
#define CONFIG_D0WD_PSRAM_CS_IO 16
#define CONFIG_D2WD_PSRAM_CLK_IO 9
#define CONFIG_D2WD_PSRAM_CS_IO 10
#define CONFIG_PICO_PSRAM_CS_IO 10
#define CONFIG_SPIRAM_BANKSWITCH_ENABLE 1
#define CONFIG_SPIRAM_BANKSWITCH_RESERVE 8
#define CONFIG_SPIRAM_CACHE_WORKAROUND 1
#define CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_MEMW 1
#define CONFIG_SPIRAM_SPIWP_SD3_PIN 7
#define CONFIG_SPIRAM_SUPPORT CONFIG_ESP32_SPIRAM_SUPPORT
# define CONFIG_D0WD_PSRAM_CLK_IO 17
# define CONFIG_D0WD_PSRAM_CS_IO 16
# define CONFIG_D2WD_PSRAM_CLK_IO 9
# define CONFIG_D2WD_PSRAM_CS_IO 10
# define CONFIG_PICO_PSRAM_CS_IO 10
# define CONFIG_SPIRAM_BANKSWITCH_ENABLE 1
# define CONFIG_SPIRAM_BANKSWITCH_RESERVE 8
# define CONFIG_SPIRAM_CACHE_WORKAROUND 1
# define CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_MEMW 1
# define CONFIG_SPIRAM_MODE_QUAD 1
# define CONFIG_SPIRAM_SPIWP_SD3_PIN 7
#endif
/**
* ESP32 specific ETH configuration
*/
#ifdef MODULE_ESP_ETH
#define CONFIG_ETH_USE_ESP32_EMAC 1
#define CONFIG_ETH_PHY_INTERFACE_RMII 1
#define CONFIG_ETH_RMII_CLK_INPUT 1
#define CONFIG_ETH_RMII_CLK_IN_GPIO 0
#define CONFIG_ETH_DMA_BUFFER_SIZE 512
#define CONFIG_ETH_DMA_RX_BUFFER_NUM 10
#define CONFIG_ETH_DMA_TX_BUFFER_NUM 10
# define CONFIG_ETH_USE_ESP32_EMAC 1
# define CONFIG_ETH_PHY_INTERFACE_RMII 1
# define CONFIG_ETH_RMII_CLK_INPUT 1
# define CONFIG_ETH_RMII_CLK_IN_GPIO 0
# define CONFIG_ETH_DMA_BUFFER_SIZE 512
# define CONFIG_ETH_DMA_RX_BUFFER_NUM 10
# define CONFIG_ETH_DMA_TX_BUFFER_NUM 10
#endif
/**
* ESP32 specific BLE driver configuration (DO NOT CHANGE)
*/
#ifdef MODULE_ESP_BLE
#define CONFIG_BTDM_BLE_ADV_REPORT_DISCARD_THRSHOLD 20
#define CONFIG_BTDM_BLE_ADV_REPORT_FLOW_CTRL_SUPP 1
#define CONFIG_BTDM_BLE_ADV_REPORT_FLOW_CTRL_NUM 100
#define CONFIG_BTDM_BLE_DEFAULT_SCA_250PPM 1
#define CONFIG_BTDM_BLE_SCAN_DUPL 1
#define CONFIG_BTDM_BLE_SLEEP_CLOCK_ACCURACY_INDEX_EFF 1
#define CONFIG_BTDM_CTRL_BLE_MAX_CONN 3
#define CONFIG_BTDM_CTRL_BLE_MAX_CONN_EFF 3
#define CONFIG_BTDM_CTRL_BR_EDR_MAX_ACL_CONN_EFF 0
#define CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF 0
#define CONFIG_BTDM_CTRL_BR_EDR_SCO_DATA_PATH_EFF 0
#define CONFIG_BTDM_CTRL_FULL_SCAN_SUPPORTED 1
#define CONFIG_BTDM_CTRL_HCI_MODE_VHCI 1
#define CONFIG_BTDM_CTRL_HLI 0 /* ESP-IDF uses 1 by default */
#define CONFIG_BTDM_CTRL_LPCLK_SEL_MAIN_XTAL 1
#define CONFIG_BTDM_CTRL_MODE_BLE_ONLY 1
#define CONFIG_BTDM_CTRL_MODEM_SLEEP 1
#define CONFIG_BTDM_CTRL_MODEM_SLEEP_MODE_ORIG 1
#define CONFIG_BTDM_CTRL_PCM_ROLE_EFF 0
#define CONFIG_BTDM_CTRL_PCM_POLAR_EFF 0
#define CONFIG_BTDM_CTRL_PINNED_TO_CORE_0 1
#define CONFIG_BTDM_CTRL_PINNED_TO_CORE 0
#define CONFIG_BTDM_RESERVE_DRAM 0xe000 /* at least 0xdb5c, we use 56 kB */
#define CONFIG_BTDM_SCAN_DUPL_CACHE_SIZE 200
#define CONFIG_BTDM_SCAN_DUPL_TYPE_DEVICE 1
#define CONFIG_BTDM_SCAN_DUPL_TYPE 0
#define CONFIG_BLE_ADV_REPORT_DISCARD_THRSHOLD CONFIG_ BTDM_BLE_ADV_REPORT_DISCARD_THRSHOLD
#define CONFIG_BLE_ADV_REPORT_FLOW_CONTROL_NUM CONFIG_ BTDM_BLE_ADV_REPORT_FLOW_CTRL_NUM
#define CONFIG_BLE_ADV_REPORT_FLOW_CONTROL_SUPPORTED CONFIG_BTDM_BLE_ADV_REPORT_FLOW_CTRL_SUPP
#define CONFIG_BLE_SCAN_DUPLICATE CONFIG_BTDM_BLE_SCAN_DUPL
#define CONFIG_BTDM_CONTROLLER_BLE_MAX_CONN CONFIG_BTDM_CTRL_BLE_MAX_CONN
#define CONFIG_BTDM_CONTROLLER_FULL_SCAN_SUPPORTED CONFIG_BTDM_CTRL_FULL_SCAN_SUPPORTED
#define CONFIG_BTDM_CONTROLLER_HCI_MODE_VHCI CONFIG_BTDM_CTRL_HCI_MODE_VHCI
#define CONFIG_BTDM_CONTROLLER_MODEM_SLEEP CONFIG_BTDM_CTRL_MODEM_SLEEP
#define CONFIG_BTDM_CONTROLLER_MODE_BLE_ONLY CONFIG_BTDM_CTRL_MODE_BLE_ONLY
#define CONFIG_DUPLICATE_SCAN_CACHE_SIZE CONFIG_BTDM_SCAN_DUPL_CACHE_SIZE
#define CONFIG_SCAN_DUPLICATE_BY_DEVICE_ADDR CONFIG_BTDM_SCAN_DUPL_TYPE_DEVICE
# define CONFIG_BT_ALARM_MAX_NUM 50
# define CONFIG_BTDM_BLE_ADV_REPORT_DISCARD_THRSHOLD 20
# define CONFIG_BTDM_BLE_ADV_REPORT_FLOW_CTRL_NUM 100
# define CONFIG_BTDM_BLE_ADV_REPORT_FLOW_CTRL_SUPP 1
# define CONFIG_BTDM_BLE_CHAN_ASS_EN 1
# define CONFIG_BTDM_BLE_DEFAULT_SCA_250PPM 1
# define CONFIG_BTDM_BLE_PING_EN 1
# define CONFIG_BTDM_BLE_SCAN_DUPL 1
# define CONFIG_BTDM_BLE_SLEEP_CLOCK_ACCURACY_INDEX_EFF 1
# define CONFIG_BTDM_CTRL_BLE_MAX_CONN 3
# define CONFIG_BTDM_CTRL_BLE_MAX_CONN_EFF 3
# define CONFIG_BTDM_CTRL_BR_EDR_MAX_ACL_CONN_EFF 0
# define CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF 0
# define CONFIG_BTDM_CTRL_BR_EDR_SCO_DATA_PATH_EFF 0
# define CONFIG_BTDM_CTRL_FULL_SCAN_SUPPORTED 1
# define CONFIG_BTDM_CTRL_HCI_MODE_VHCI 1
# define CONFIG_BTDM_CTRL_HLI 0 /* ESP-IDF uses 1 by default */
# define CONFIG_BTDM_CTRL_LPCLK_SEL_MAIN_XTAL 1
# define CONFIG_BTDM_CTRL_MODE_BLE_ONLY 1
# define CONFIG_BTDM_CTRL_MODEM_SLEEP_MODE_ORIG 1
# define CONFIG_BTDM_CTRL_MODEM_SLEEP 1
# define CONFIG_BTDM_CTRL_PCM_FSYNCSHP_EFF 1
# define CONFIG_BTDM_CTRL_PCM_POLAR_EFF 0
# define CONFIG_BTDM_CTRL_PCM_ROLE_EFF 0
# define CONFIG_BTDM_CTRL_PINNED_TO_CORE 0
# define CONFIG_BTDM_CTRL_PINNED_TO_CORE_0 1
# define CONFIG_BTDM_RESERVE_DRAM 0xe000 /* at least 0xdb5c, we use 56 kB */
# define CONFIG_BTDM_SCAN_DUPL_CACHE_REFRESH_PERIOD 0
# define CONFIG_BTDM_SCAN_DUPL_CACHE_SIZE 200
# define CONFIG_BTDM_SCAN_DUPL_TYPE 0
# define CONFIG_BTDM_SCAN_DUPL_TYPE_DEVICE 1
#else
#define CONFIG_BTDM_RESERVE_DRAM 0
# define CONFIG_BTDM_RESERVE_DRAM 0
#endif
#ifdef __cplusplus

119
cpu/esp32/include/sdkconfig_esp32c3.h
View File

@ -34,38 +34,41 @@ extern "C" {
/* Mapping of Kconfig defines to the respective enumeration values */
#if CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_2
#define CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ 2
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 2
#elif CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_5
#define CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ 5
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 5
#elif CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_10
#define CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ 10
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 10
#elif CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_20
#define CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ 20
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 20
#elif CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_40
#define CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ 40
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 40
#elif CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_80
#define CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ 80
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 80
#elif CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_160
#define CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ 160
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 160
#endif
/**
* @brief Defines the CPU frequency [values = 2, 5, 10, 20, 40, 80, 160]
*/
#ifndef CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ
#define CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ 80
#ifndef CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 80
#endif
/** @} */
/**
* ESP32-C3 specific RTC clock configuration
*/
#define CONFIG_ESP32C3_RTC_CLK_CAL_CYCLES (8 * 1024)
#define CONFIG_RTC_CLK_CAL_CYCLES 1024
/**
* ESP32-C3 specific EFUSE configuration
*/
#define CONFIG_EFUSE_MAX_BLK_LEN 256
#define CONFIG_ESP_EFUSE_BLOCK_REV_MIN_FULL 0
#define CONFIG_ESP_EFUSE_BLOCK_REV_MAX_FULL 199
/**
* ESP32-C3 specific MAC configuration
@ -90,50 +93,76 @@ extern "C" {
/**
* ESP32-C3 specific sleep configuration (DO NOT CHANGE)
*/
#define CONFIG_ESP_SLEEP_POWER_DOWN_FLASH 1
#define CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND 1
#define CONFIG_ESP32C3_LIGHTSLEEP_GPIO_RESET_WORKAROUND 1
#define CONFIG_ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB 1
#define CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND 1
#define CONFIG_ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS 0 /* we realize it */
#define CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND 1
#define CONFIG_ESP_SLEEP_POWER_DOWN_FLASH 1
#define CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY 0
#define CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP 1
/**
* ESP32-C3 specific USB configuration
*/
#define CONFIG_ESP_PHY_ENABLE_USB 1
#define CONFIG_ESP_PHY_ENABLE_USB 1
/**
* ESP32-C3 BLE driver configuration (DO NOT CHANGE)
*/
#ifdef MODULE_ESP_BLE
#define CONFIG_BT_CTRL_ADV_DUP_FILT_MAX 30
#define CONFIG_BT_CTRL_BLE_ADV_REPORT_DISCARD_THRSHOLD 20
#define CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_NUM 100
#define CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_SUPP 1
#define CONFIG_BT_CTRL_BLE_MAX_ACT 10
#define CONFIG_BT_CTRL_BLE_MAX_ACT_EFF 10
#define CONFIG_BT_CTRL_BLE_SCAN_DUPL 1
#define CONFIG_BT_CTRL_BLE_STATIC_ACL_TX_BUF_NB 0
#define CONFIG_BT_CTRL_CE_LENGTH_TYPE_EFF 0
#define CONFIG_BT_CTRL_CE_LENGTH_TYPE_ORIG 1
#define CONFIG_BT_CTRL_COEX_PHY_CODED_TX_RX_TLIM_DIS 1
#define CONFIG_BT_CTRL_COEX_PHY_CODED_TX_RX_TLIM_EFF 0
#define CONFIG_BT_CTRL_DFT_TX_POWER_LEVEL_EFF 10
#define CONFIG_BT_CTRL_DFT_TX_POWER_LEVEL_P3 1
#define CONFIG_BT_CTRL_HCI_MODE_VHCI 1
#define CONFIG_BT_CTRL_HCI_TL 1
#define CONFIG_BT_CTRL_HCI_TL_EFF 1
#define CONFIG_BT_CTRL_HW_CCA_EFF 0
#define CONFIG_BT_CTRL_HW_CCA_VAL 20
#define CONFIG_BT_CTRL_MODE_EFF 1
#define CONFIG_BT_CTRL_PINNED_TO_CORE 0
#define CONFIG_BT_CTRL_RX_ANTENNA_INDEX_0 1
#define CONFIG_BT_CTRL_RX_ANTENNA_INDEX_EFF 0
#define CONFIG_BT_CTRL_SCAN_DUPL_CACHE_SIZE 100
#define CONFIG_BT_CTRL_SCAN_DUPL_TYPE 0
#define CONFIG_BT_CTRL_SCAN_DUPL_TYPE_DEVICE 1
#define CONFIG_BT_CTRL_SLEEP_CLOCK_EFF 0
#define CONFIG_BT_CTRL_SLEEP_MODE_EFF 0
#define CONFIG_BT_CTRL_TX_ANTENNA_INDEX_0 1
#define CONFIG_BT_CTRL_TX_ANTENNA_INDEX_EFF 0
#define CONFIG_BT_ENABLED 1
#define CONFIG_BT_SOC_SUPPORT_5_0 1
# define CONFIG_BT_ALARM_MAX_NUM 50
# define CONFIG_BT_BLE_CCA_MODE 0
# define CONFIG_BT_BLE_CCA_MODE_NONE 1
# define CONFIG_BT_CTRL_ADV_DUP_FILT_MAX 30
# define CONFIG_BT_CTRL_BLE_ADV_REPORT_DISCARD_THRSHOLD 20
# define CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_NUM 100
# define CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_SUPP 1
# define CONFIG_BT_CTRL_BLE_MAX_ACT 10
# define CONFIG_BT_CTRL_BLE_MAX_ACT_EFF 10
# define CONFIG_BT_CTRL_BLE_SCAN_DUPL 1
# define CONFIG_BT_CTRL_BLE_STATIC_ACL_TX_BUF_NB 0
# define CONFIG_BT_CTRL_CE_LENGTH_TYPE_EFF 0
# define CONFIG_BT_CTRL_CE_LENGTH_TYPE_ORIG 1
# define CONFIG_BT_CTRL_CHAN_ASS_EN 1
# define CONFIG_BT_CTRL_COEX_PHY_CODED_TX_RX_TLIM_DIS 1
# define CONFIG_BT_CTRL_COEX_PHY_CODED_TX_RX_TLIM_EFF 0
# define CONFIG_BT_CTRL_DFT_TX_POWER_LEVEL_EFF 11
# define CONFIG_BT_CTRL_DFT_TX_POWER_LEVEL_P9 1
# define CONFIG_BT_CTRL_DUPL_SCAN_CACHE_REFRESH_PERIOD 0
# define CONFIG_BT_CTRL_HCI_MODE_VHCI 1
# define CONFIG_BT_CTRL_HCI_TL 1
# define CONFIG_BT_CTRL_HCI_TL_EFF 1
# define CONFIG_BT_CTRL_HW_CCA_EFF 0
# define CONFIG_BT_CTRL_HW_CCA_VAL 20
# define CONFIG_BT_CTRL_LE_PING_EN 1
# define CONFIG_BT_CTRL_MODE_EFF 1
# define CONFIG_BT_CTRL_PINNED_TO_CORE 0
# define CONFIG_BT_CTRL_PINNED_TO_CORE_0 1
# define CONFIG_BT_CTRL_RX_ANTENNA_INDEX_0 1
# define CONFIG_BT_CTRL_RX_ANTENNA_INDEX_EFF 0
# define CONFIG_BT_CTRL_SCAN_DUPL_CACHE_SIZE 100
# define CONFIG_BT_CTRL_SCAN_DUPL_TYPE 0
# define CONFIG_BT_CTRL_SCAN_DUPL_TYPE_DEVICE 1
# define CONFIG_BT_CTRL_SLEEP_CLOCK_EFF 0
# define CONFIG_BT_CTRL_SLEEP_MODE_EFF 0
# define CONFIG_BT_CTRL_TX_ANTENNA_INDEX_0 1
# define CONFIG_BT_CTRL_TX_ANTENNA_INDEX_EFF 0
# define CONFIG_BT_NIMBLE_COEX_PHY_CODED_TX_RX_TLIM_DIS 1
#endif
/* According to the ESP32-C3 Errata Sheet ADC2 does not work correctly.
* To use ADC2 and GPIO5 as ADC channel, CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3
* has to be set (default). */
#ifndef CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3
# define CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3 1
#endif
/* According to the ESP32-C3 Errata Sheet ADC2 does not work correctly.
* To use ADC2 and GPIO5 as ADC channel, CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3
* has to be set (default). */
#ifndef CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3
#define CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3 1
#endif
#ifdef __cplusplus

69
cpu/esp32/include/sdkconfig_esp32s2.h
View File

@ -34,40 +34,47 @@ extern "C" {
/* Mapping of Kconfig defines to the respective enumeration values */
#if CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ_2
#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ 2
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 2
#elif CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ_5
#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ 5
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 5
#elif CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ_10
#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ 10
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 10
#elif CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ_20
#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ 20
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 20
#elif CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ_40
#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ 40
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 40
#elif CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ_80
#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ 80
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 80
#elif CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ_160
#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ 160
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 160
#elif CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ_240
#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ 240
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 240
#endif
/**
* @brief Defines the CPU frequency [values = 2, 5, 10, 10, 40, 80, 160, 240]
*/
#ifndef CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ
#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ 80
#ifndef CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 80
#endif
/** @} */
/**
* ESP32-S2 specific RTC clock configuration
*/
#define CONFIG_ESP32S2_RTC_CLK_CAL_CYCLES (8 * 1024)
#define CONFIG_RTC_CLK_CAL_CYCLES 576
#ifdef MODULE_ESP_RTC_TIMER_32K
# define CONFIG_RTC_XTAL_CAL_RETRY 3
#endif
/**
* ESP32-S2 specific EFUSE configuration
*/
#define CONFIG_EFUSE_MAX_BLK_LEN 256
#define CONFIG_ESP_EFUSE_BLOCK_REV_MIN_FULL 0
#define CONFIG_ESP_EFUSE_BLOCK_REV_MAX_FULL 99
/**
* ESP32-S2 specific MAC configuration
@ -85,49 +92,49 @@ extern "C" {
/**
* ESP32-S2 specific system configuration (DO NOT CHANGE)
*/
#define CONFIG_ESP_TIMER_IMPL_SYSTIMER 1
#define CONFIG_ESP_CONSOLE_MULTIPLE_UART 1
#define CONFIG_ESP32S2_DEBUG_OCDAWARE 1
#define CONFIG_ESP32S2_BROWNOUT_DET 1
#define CONFIG_ESP32S2_BROWNOUT_DET_LVL 7
#define CONFIG_ESP32S2_TRACEMEM_RESERVE_DRAM 0x0
#define CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM 0
#define CONFIG_ESP_BROWNOUT_DET 1
#define CONFIG_ESP_BROWNOUT_DET_LVL 7
#define CONFIG_ESP_CONSOLE_MULTIPLE_UART 1
#define CONFIG_ESP_DEBUG_OCDAWARE 1
#define CONFIG_ESP_TIMER_IMPL_SYSTIMER 1
#define CONFIG_ULP_COPROC_RESERVE_MEM 0
/**
* ESP32-S2 specific sleep configuration (DO NOT CHANGE)
*/
#define CONFIG_ESP_SLEEP_RTC_BUS_ISO_WORKAROUND 1
#define CONFIG_ESP_SLEEP_RTC_BUS_ISO_WORKAROUND 1
#define CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY 0
/**
* ESP32-S2 specific USB configuration
*/
#ifdef MODULE_ESP_IDF_USB
#define CONFIG_USB_OTG_SUPPORTED 1
# define CONFIG_USB_OTG_SUPPORTED 1
#endif
/**
* ESP32-S2 specific SPI RAM configuration
*/
#ifdef MODULE_ESP_SPI_RAM
#define CONFIG_ESP32S2_SPIRAM_SUPPORT 1
#ifdef MODULE_ESP_SPI_OCT
#define CONFIG_SPIRAM_MODE_OCT 1
#else
#define CONFIG_SPIRAM_MODE_QUAD 1
#endif
#define CONFIG_DEFAULT_PSRAM_CLK_IO 30
#define CONFIG_DEFAULT_PSRAM_CS_IO 26
#define CONFIG_SPIRAM_SUPPORT CONFIG_ESP32S2_SPIRAM_SUPPORT
# ifdef MODULE_ESP_SPI_OCT
# define CONFIG_SPIRAM_MODE_OCT 1
# else
# define CONFIG_SPIRAM_MODE_QUAD 1
# endif
# define CONFIG_SPIRAM_CLK_IO 30
# define CONFIG_SPIRAM_CS_IO 26
#endif
/**
* ESP32-S2 specific Cache config
*/
#define CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB 1
#define CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE 0x2000
#define CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_32B 1
#define CONFIG_ESP32S2_DATA_CACHE_8KB 1
#define CONFIG_ESP32S2_DATA_CACHE_SIZE 0x2000
#define CONFIG_ESP32S2_DATA_CACHE_LINE_32B 1
/**

132
cpu/esp32/include/sdkconfig_esp32s3.h
View File

@ -34,40 +34,43 @@ extern "C" {
/* Mapping of Kconfig defines to the respective enumeration values */
#if CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ_2
#define CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ 2
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 2
#elif CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ_5
#define CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ 5
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 5
#elif CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ_10
#define CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ 10
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 10
#elif CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ_20
#define CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ 20
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 20
#elif CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ_40
#define CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ 40
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 40
#elif CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ_80
#define CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ 80
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 80
#elif CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ_160
#define CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ 160
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 160
#elif CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ_240
#define CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ 240
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 240
#endif
/**
* @brief Defines the CPU frequency [values = 2, 5, 10, 10, 40, 80, 160, 240]
*/
#ifndef CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ
#define CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ 80
#ifndef CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 80
#endif
/** @} */
/**
* ESP32-S3 specific RTC clock configuration
*/
#define CONFIG_ESP32S3_RTC_CLK_CAL_CYCLES (8 * 1024)
#define CONFIG_RTC_CLK_CAL_CYCLES 1024
/**
* ESP32-S3 specific EFUSE configuration
*/
#define CONFIG_EFUSE_MAX_BLK_LEN 256
#define CONFIG_ESP_EFUSE_BLOCK_REV_MIN_FULL 0
#define CONFIG_ESP_EFUSE_BLOCK_REV_MAX_FULL 199
/**
* ESP32-S3 specific MAC configuration
@ -83,49 +86,47 @@ extern "C" {
*/
#define CONFIG_ESPTOOLPY_FLASHFREQ_80M 1
#define CONFIG_ESPTOOLPY_FLASHFREQ "80m"
#define CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR 1
/**
* ESP32-S3 specific system configuration (DO NOT CHANGE)
*/
#define CONFIG_ESP_TIMER_IMPL_SYSTIMER 1
#define CONFIG_ESP_CONSOLE_MULTIPLE_UART 1
#define CONFIG_ESP32S3_DEBUG_OCDAWARE 1
#define CONFIG_ESP32S3_BROWNOUT_DET 1
#define CONFIG_ESP32S3_BROWNOUT_DET_LVL 7
#define CONFIG_ESP32S3_DEEP_SLEEP_WAKEUP_DELAY 2000
#define CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM 0x0
#define CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM 0
#define CONFIG_ESP_BROWNOUT_DET 1
#define CONFIG_ESP_BROWNOUT_DET_LVL 7
#define CONFIG_ESP_CONSOLE_MULTIPLE_UART 1
#define CONFIG_ESP_DEBUG_OCDAWARE 1
#define CONFIG_ESP_TIMER_IMPL_SYSTIMER 1
#define CONFIG_ULP_COPROC_RESERVE_MEM 0
/**
* ESP32-S3 specific sleep configuration (DO NOT CHANGE)
*/
#define CONFIG_ESP_SLEEP_RTC_BUS_ISO_WORKAROUND 1
#define CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND 1
#define CONFIG_ESP_SLEEP_RTC_BUS_ISO_WORKAROUND 1
#define CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND 1
#define CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY 2000
/**
* ESP32-S3 specific USB configuration
*/
#define CONFIG_ESP_PHY_ENABLE_USB 1
#ifdef MODULE_ESP_IDF_USB
#define CONFIG_USB_OTG_SUPPORTED 1
# define CONFIG_USB_OTG_SUPPORTED 1
#endif
/**
* ESP32-S3 specific SPI RAM configuration
*/
#ifdef MODULE_ESP_SPI_RAM
#define CONFIG_ESP32S3_SPIRAM_SUPPORT 1
#ifdef MODULE_ESP_SPI_OCT
#define CONFIG_SPIRAM_MODE_OCT 1
# define CONFIG_SPIRAM_MODE_OCT 1
#else
#define CONFIG_SPIRAM_MODE_QUAD 1
# define CONFIG_SPIRAM_MODE_QUAD 1
#endif
#define CONFIG_DEFAULT_PSRAM_CLK_IO 30
#define CONFIG_DEFAULT_PSRAM_CS_IO 26
#define CONFIG_SPIRAM_SUPPORT CONFIG_ESP32S3_SPIRAM_SUPPORT
# define CONFIG_SPIRAM_CLK_IO 30
# define CONFIG_SPIRAM_CS_IO 26
#endif
/**
@ -148,40 +149,43 @@ extern "C" {
* ESP32-S3 BLE driver configuration (DO NOT CHANGE)
*/
#ifdef MODULE_ESP_BLE
#define CONFIG_BT_CONTROLLER_ONLY 1
#define CONFIG_BT_CTRL_ADV_DUP_FILT_MAX 30
#define CONFIG_BT_CTRL_BLE_ADV_REPORT_DISCARD_THRSHOLD 20
#define CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_NUM 100
#define CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_SUPP 1
#define CONFIG_BT_CTRL_BLE_MAX_ACT 10
#define CONFIG_BT_CTRL_BLE_MAX_ACT_EFF 10
#define CONFIG_BT_CTRL_BLE_SCAN_DUPL 1
#define CONFIG_BT_CTRL_BLE_STATIC_ACL_TX_BUF_NB 0
#define CONFIG_BT_CTRL_CE_LENGTH_TYPE_EFF 0
#define CONFIG_BT_CTRL_CE_LENGTH_TYPE_ORIG 1
#define CONFIG_BT_CTRL_COEX_PHY_CODED_TX_RX_TLIM_DIS 1
#define CONFIG_BT_CTRL_COEX_PHY_CODED_TX_RX_TLIM_EFF 0
#define CONFIG_BT_CTRL_DFT_TX_POWER_LEVEL_EFF 10
#define CONFIG_BT_CTRL_DFT_TX_POWER_LEVEL_P3 1
#define CONFIG_BT_CTRL_HCI_MODE_VHCI 1
#define CONFIG_BT_CTRL_HCI_TL 1
#define CONFIG_BT_CTRL_HCI_TL_EFF 1
#define CONFIG_BT_CTRL_HW_CCA_EFF 0
#define CONFIG_BT_CTRL_HW_CCA_VAL 20
#define CONFIG_BT_CTRL_MODE_EFF 1
#define CONFIG_BT_CTRL_PINNED_TO_CORE 0
#define CONFIG_BT_CTRL_PINNED_TO_CORE_0 1
#define CONFIG_BT_CTRL_RX_ANTENNA_INDEX_0 1
#define CONFIG_BT_CTRL_RX_ANTENNA_INDEX_EFF 0
#define CONFIG_BT_CTRL_SCAN_DUPL_CACHE_SIZE 100
#define CONFIG_BT_CTRL_SCAN_DUPL_TYPE 0
#define CONFIG_BT_CTRL_SCAN_DUPL_TYPE_DEVICE 1
#define CONFIG_BT_CTRL_SLEEP_CLOCK_EFF 0
#define CONFIG_BT_CTRL_SLEEP_MODE_EFF 0
#define CONFIG_BT_CTRL_TX_ANTENNA_INDEX_0 1
#define CONFIG_BT_CTRL_TX_ANTENNA_INDEX_EFF 0
#define CONFIG_BT_ENABLED 1
#define CONFIG_BT_SOC_SUPPORT_5_0 1
# define CONFIG_BT_ALARM_MAX_NUM 50
# define CONFIG_BT_BLE_CCA_MODE 0
# define CONFIG_BT_BLE_CCA_MODE_NONE 1
# define CONFIG_BT_CTRL_ADV_DUP_FILT_MAX 30
# define CONFIG_BT_CTRL_BLE_ADV_REPORT_DISCARD_THRSHOLD 20
# define CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_NUM 100
# define CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_SUPP 1
# define CONFIG_BT_CTRL_BLE_MAX_ACT 10
# define CONFIG_BT_CTRL_BLE_MAX_ACT_EFF 10
# define CONFIG_BT_CTRL_BLE_SCAN_DUPL 1
# define CONFIG_BT_CTRL_BLE_STATIC_ACL_TX_BUF_NB 0
# define CONFIG_BT_CTRL_CE_LENGTH_TYPE_EFF 0
# define CONFIG_BT_CTRL_CE_LENGTH_TYPE_ORIG 1
# define CONFIG_BT_CTRL_CHAN_ASS_EN 1
# define CONFIG_BT_CTRL_COEX_PHY_CODED_TX_RX_TLIM_DIS 1
# define CONFIG_BT_CTRL_COEX_PHY_CODED_TX_RX_TLIM_EFF 0
# define CONFIG_BT_CTRL_DFT_TX_POWER_LEVEL_EFF 11
# define CONFIG_BT_CTRL_DFT_TX_POWER_LEVEL_P9 1
# define CONFIG_BT_CTRL_DUPL_SCAN_CACHE_REFRESH_PERIOD 0
# define CONFIG_BT_CTRL_HCI_MODE_VHCI 1
# define CONFIG_BT_CTRL_HCI_TL 1
# define CONFIG_BT_CTRL_HCI_TL_EFF 1
# define CONFIG_BT_CTRL_HW_CCA_EFF 0
# define CONFIG_BT_CTRL_HW_CCA_VAL 20
# define CONFIG_BT_CTRL_LE_PING_EN 1
# define CONFIG_BT_CTRL_MODE_EFF 1
# define CONFIG_BT_CTRL_PINNED_TO_CORE 0
# define CONFIG_BT_CTRL_PINNED_TO_CORE_0 1
# define CONFIG_BT_CTRL_RX_ANTENNA_INDEX_0 1
# define CONFIG_BT_CTRL_RX_ANTENNA_INDEX_EFF 0
# define CONFIG_BT_CTRL_SCAN_DUPL_CACHE_SIZE 100
# define CONFIG_BT_CTRL_SCAN_DUPL_TYPE 0
# define CONFIG_BT_CTRL_SCAN_DUPL_TYPE_DEVICE 1
# define CONFIG_BT_CTRL_SLEEP_CLOCK_EFF 0
# define CONFIG_BT_CTRL_SLEEP_MODE_EFF 0
# define CONFIG_BT_CTRL_TX_ANTENNA_INDEX_0 1
# define CONFIG_BT_CTRL_TX_ANTENNA_INDEX_EFF 0
#endif
#ifdef __cplusplus

2
cpu/esp32/include/syscalls.h
View File

@ -27,7 +27,7 @@ extern "C" {
#endif
/** Time since boot in us (64bit version) */
int64_t system_get_time_64 (void);
uint64_t system_get_time_64 (void);
/** initialize system watchdog timer and start it */
void system_wdt_init (void);

108
cpu/esp32/irq_arch.c
View File

@ -19,14 +19,17 @@
*/
#include "irq_arch.h"
#include "log.h"
#include "esp_attr.h"
#include "esp_bit_defs.h"
#include "esp_cpu.h"
#include "esp_err.h"
#include "freertos/FreeRTOS.h"
#include "hal/interrupt_controller_types.h"
#include "hal/interrupt_controller_ll.h"
#include "rom/ets_sys.h"
#include "soc/interrupts.h"
#include "soc/periph_defs.h"
#include "soc/soc.h"
#include "esp_intr_alloc.h"
#define ENABLE_DEBUG 0
@ -44,83 +47,87 @@ typedef struct intr_handle_data_t {
/* TODO change to a clearer approach */
static const struct intr_handle_data_t _irq_data_table[] = {
#ifndef __XTENSA__
{ ETS_FROM_CPU_INTR0_SOURCE, CPU_INUM_SOFTWARE, 1 },
#endif
{ ETS_TG0_WDT_LEVEL_INTR_SOURCE, CPU_INUM_WDT, 1 },
{ ETS_TG0_T0_LEVEL_INTR_SOURCE, CPU_INUM_RTT, 1 },
#if defined(CPU_FAM_ESP32) || defined(CPU_FAM_ESP32S2) || defined(CPU_FAM_ESP32S3)
#if SOC_TIMER_GROUP_TIMERS_PER_GROUP > 1
{ ETS_TG0_T1_LEVEL_INTR_SOURCE, CPU_INUM_TIMER, 2 },
#endif
#if defined(CPU_FAM_ESP32) || defined(CPU_FAM_ESP32S2)
{ ETS_TG0_LACT_LEVEL_INTR_SOURCE, CPU_INUM_TIMER, 2 },
#endif
#if !defined(CPU_FAM_ESP32C2)
#if SOC_TIMER_GROUPS > 1
{ ETS_TG1_T0_LEVEL_INTR_SOURCE, CPU_INUM_TIMER, 2 },
#endif
#if defined(CPU_FAM_ESP32) || defined(CPU_FAM_ESP32S2) || defined(CPU_FAM_ESP32S3)
# if SOC_TIMER_GROUP_TIMERS_PER_GROUP > 1
{ ETS_TG1_T1_LEVEL_INTR_SOURCE, CPU_INUM_TIMER, 2 },
# endif /* SOC_TIMER_GROUP_TIMERS_PER_GROUP > 1 */
#endif /* SOC_TIMER_GROUPS > 1 */
#if defined(CPU_FAM_ESP32)
{ ETS_TG0_LACT_LEVEL_INTR_SOURCE, CPU_INUM_SYSTIMER, 2 },
#elif defined(CPU_FAM_ESP32S2) || defined(CPU_FAM_ESP32S3) || defined(CPU_FAM_ESP32C3)
{ ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, CPU_INUM_SYSTIMER, 2 },
#else
# error "Platform implementation is missing"
#endif
{ ETS_UART0_INTR_SOURCE, CPU_INUM_UART, 1 },
{ ETS_UART1_INTR_SOURCE, CPU_INUM_UART, 1 },
#if defined(CPU_FAM_ESP32) || defined(CPU_FAM_ESP32S2) || defined(CPU_FAM_ESP32S3)
#if SOC_UART_NUM > 2
{ ETS_UART2_INTR_SOURCE, CPU_INUM_UART, 1 },
#endif
{ ETS_GPIO_INTR_SOURCE, CPU_INUM_GPIO, 1 },
{ ETS_I2C_EXT0_INTR_SOURCE, CPU_INUM_I2C, 1 },
#if defined(CPU_FAM_ESP32) || defined(CPU_FAM_ESP32S2) || defined(CPU_FAM_ESP32S3)
#if SOC_I2C_NUM > 1
{ ETS_I2C_EXT1_INTR_SOURCE, CPU_INUM_I2C, 1 },
#endif
#if defined(CPU_FAM_ESP32)
#if defined(SOC_BLE_SUPPORTED)
# if defined(CPU_FAM_ESP32) || defined(CPU_FAM_ESP32S3) || defined(CPU_FAM_ESP32C3)
{ ETS_RWBLE_INTR_SOURCE, CPU_INUM_BLE, 2 },
# else
# error "Platform implementation is missing"
# endif
#endif /* SOC_BLE_SUPPORTED */
#if defined(SOC_EMAC_SUPPORTED)
{ ETS_ETH_MAC_INTR_SOURCE, CPU_INUM_ETH, 1 },
#endif
#if !defined(CPU_FAM_ESP32C2)
#if defined(SOC_RMT_SUPPORTED)
{ ETS_RMT_INTR_SOURCE, CPU_INUM_RMT, 1 },
#endif
#if defined(SOC_SDMMC_HOST_SUPPORTED)
{ ETS_SDIO_HOST_INTR_SOURCE, CPU_INUM_SDMMC, 2 },
#endif
#if defined(SOC_TWAI_SUPPORTED)
{ ETS_TWAI_INTR_SOURCE, CPU_INUM_CAN, 1 },
{ ETS_TIMER2_INTR_SOURCE, CPU_INUM_FRC2, 2 },
#endif
#if !defined(CPU_FAM_ESP32)
{ ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, CPU_INUM_SYSTIMER, 2 },
#endif
{ ETS_INTERNAL_SW1_INTR_SOURCE, CPU_INUM_BLE, 2 },
#if defined(CPU_FAM_ESP32S2) || defined(CPU_FAM_ESP32S3)
#if defined(SOC_USB_OTG_SUPPORTED)
{ ETS_USB_INTR_SOURCE, CPU_INUM_USB, 1 },
#endif
#if defined(ETS_USB_SERIAL_JTAG_INTR_SOURCE)
#if defined(SOC_USB_SERIAL_JTAG_SUPPORTED)
{ ETS_USB_SERIAL_JTAG_INTR_SOURCE, CPU_INUM_SERIAL_JTAG, 1 },
#endif
{ ETS_RMT_INTR_SOURCE, CPU_INUM_RMT, 1 },
#if defined(CPU_FAM_ESP32) || defined(CPU_FAM_ESP32S2)
{ ETS_I2S0_INTR_SOURCE, CPU_INUM_LCD, 1 },
#elif defined(CPU_FAM_ESP32S3)
{ ETS_LCD_CAM_INTR_SOURCE, CPU_INUM_LCD, 1 },
#endif
#if defined(CPU_FAM_ESP32) || defined(CPU_FAM_ESP32S2) || defined(CPU_FAM_ESP32S3)
{ ETS_SDIO_HOST_INTR_SOURCE, CPU_INUM_SDMMC, 2 },
#if SOC_LCDCAM_SUPPORTED
{ ETS_LCD_CAM_INTR_SOURCE, CPU_INUM_LCDCAM, 2 },
#endif
};
#define IRQ_DATA_TABLE_SIZE ARRAY_SIZE(_irq_data_table)
#if defined(CPU_FAM_ESP32) && MODULE_ESP_LCD && MODULE_ESP_ETH
#error "esp_eth and esp_lcd can't be used at the same time because of an interrupt conflict"
#endif
void esp_irq_init(void)
{
#ifdef SOC_CPU_HAS_FLEXIBLE_INTC
/* to avoid to do it in every component, we initialize levels here once */
for (unsigned i = 0; i < IRQ_DATA_TABLE_SIZE; i++) {
intr_cntrl_ll_set_int_level(_irq_data_table[i].intr, _irq_data_table[i].level);
esp_cpu_intr_set_priority(_irq_data_table[i].intr, _irq_data_table[i].level);
}
#endif
}
void esp_intr_enable_source(int inum)
{
intr_cntrl_ll_enable_interrupts(BIT(inum));
esp_cpu_intr_enable(BIT(inum));
}
void esp_intr_disable_source(int inum)
{
intr_cntrl_ll_disable_interrupts(BIT(inum));
esp_cpu_intr_disable(BIT(inum));
}
esp_err_t esp_intr_enable(intr_handle_t handle)
@ -150,6 +157,8 @@ esp_err_t esp_intr_disable(intr_handle_t handle)
esp_err_t esp_intr_alloc(int source, int flags, intr_handler_t handler,
void *arg, intr_handle_t *ret_handle)
{
DEBUG("%s source=%d flags=0x%04"PRIx16" handler=%p arg=%p\n",
__func__, source, (uint16_t)flags, handler, arg);
unsigned i;
for (i = 0; i < IRQ_DATA_TABLE_SIZE; i++) {
if (_irq_data_table[i].src == source) {
@ -158,6 +167,8 @@ esp_err_t esp_intr_alloc(int source, int flags, intr_handler_t handler,
}
if (i == IRQ_DATA_TABLE_SIZE) {
LOG_ERROR("%s source=%d not found in interrupt allocation table\n",
__func__, source);
return ESP_ERR_NOT_FOUND;
}
@ -165,16 +176,16 @@ esp_err_t esp_intr_alloc(int source, int flags, intr_handler_t handler,
intr_matrix_set(PRO_CPU_NUM, _irq_data_table[i].src, _irq_data_table[i].intr);
/* set the interrupt handler */
intr_cntrl_ll_set_int_handler(_irq_data_table[i].intr, handler, arg);
esp_cpu_intr_set_handler(_irq_data_table[i].intr, handler, arg);
#ifdef SOC_CPU_HAS_FLEXIBLE_INTC
/* set interrupt level given by flags */
intr_cntrl_ll_set_int_level(_irq_data_table[i].intr, esp_intr_flags_to_level(flags));
esp_cpu_intr_set_priority(_irq_data_table[i].intr, esp_intr_flags_to_level(flags));
#endif
/* enable the interrupt if ESP_INTR_FLAG_INTRDISABLED is not set */
if ((flags & ESP_INTR_FLAG_INTRDISABLED) == 0) {
intr_cntrl_ll_enable_interrupts(BIT(_irq_data_table[i].intr));
esp_cpu_intr_enable(BIT(_irq_data_table[i].intr));
}
if (ret_handle) {
@ -204,3 +215,24 @@ int esp_intr_get_cpu(intr_handle_t handle)
{
return PRO_CPU_NUM;
}
static volatile uint32_t esp_intr_noniram_state;
static uint32_t esp_intr_noniram_call_counter = 0;
void IRAM_ATTR esp_intr_noniram_disable(void)
{
if (esp_intr_noniram_call_counter == 0) {
esp_intr_noniram_state = irq_disable();
}
esp_intr_noniram_call_counter++;
}
void IRAM_ATTR esp_intr_noniram_enable(void)
{
if (esp_intr_noniram_call_counter) {
esp_intr_noniram_call_counter--;
if (esp_intr_noniram_call_counter == 0) {
irq_restore(esp_intr_noniram_state);
}
};
}

648
cpu/esp32/ld/esp32/sections.ld.in
View File

@ -1,648 +0,0 @@
/* Automatically generated file; DO NOT EDIT */
/* Espressif IoT Development Framework Linker Script */
/* Generated from: esp-idf/components/esp_system/ld/esp32/sections.ld.in */
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Default entry point: */
ENTRY(call_start_cpu0);
SECTIONS
{
/* RTC fast memory holds RTC wake stub code,
including from any source file named rtc_wake_stub*.c
*/
.rtc.text :
{
. = ALIGN(4);
_rtc_text_start = ABSOLUTE(.);
*(.rtc.literal .rtc.text .rtc.text.*)
*rtc_wake_stub*.*(.literal .text .literal.* .text.*)
_rtc_text_end = ABSOLUTE(.);
} > rtc_iram_seg
/*
This section is required to skip rtc.text area because rtc_iram_seg and
rtc_data_seg are reflect the same address space on different buses.
*/
.rtc.dummy :
{
_rtc_dummy_start = ABSOLUTE(.);
_rtc_fast_start = ABSOLUTE(.);
. = SIZEOF(.rtc.text);
_rtc_dummy_end = ABSOLUTE(.);
} > rtc_data_seg
/* This section located in RTC FAST Memory area.
It holds data marked with RTC_FAST_ATTR attribute.
See the file "esp_attr.h" for more information.
*/
.rtc.force_fast :
{
. = ALIGN(4);
_rtc_force_fast_start = ABSOLUTE(.);
_coredump_rtc_fast_start = ABSOLUTE(.);
*(.rtc.fast.coredump .rtc.fast.coredump.*)
_coredump_rtc_fast_end = ABSOLUTE(.);
*(.rtc.force_fast .rtc.force_fast.*)
. = ALIGN(4) ;
_rtc_force_fast_end = ABSOLUTE(.);
} > rtc_data_seg
/* RTC data section holds RTC wake stub
data/rodata, including from any source file
named rtc_wake_stub*.c and the data marked with
RTC_DATA_ATTR, RTC_RODATA_ATTR attributes.
The memory location of the data is dependent on
CONFIG_ESP32_RTCDATA_IN_FAST_MEM option.
*/
.rtc.data :
{
_rtc_data_start = ABSOLUTE(.);
_coredump_rtc_start = ABSOLUTE(.);
*(.rtc.coredump .rtc.coredump.*)
_coredump_rtc_end = ABSOLUTE(.);
*(.rtc.data .rtc.data.*)
*(.rtc.rodata .rtc.rodata.*)
*rtc_wake_stub*.*(.data .rodata .data.* .rodata.* .bss .bss.*)
_rtc_data_end = ABSOLUTE(.);
} > rtc_data_location
/* RTC bss, from any source file named rtc_wake_stub*.c */
.rtc.bss (NOLOAD) :
{
/* part that is initialized if not waking up from deep sleep */
_rtc_bss_start = ABSOLUTE(.);
*rtc_wake_stub*.*(.bss .bss.*)
*rtc_wake_stub*.*(COMMON)
_rtc_bss_end = ABSOLUTE(.);
/* part that saves some data for rtc periph module, this part is
only initialized at power on reset */
_rtc_bss_rtc_start = ABSOLUTE(.);
*(.rtc.bss .rtc.bss.*)
_rtc_bss_rtc_end = ABSOLUTE(.);
} > rtc_data_location
/* This section holds data that should not be initialized at power up
and will be retained during deep sleep.
User data marked with RTC_NOINIT_ATTR will be placed
into this section. See the file "esp_attr.h" for more information.
The memory location of the data is dependent on
CONFIG_ESP32_RTCDATA_IN_FAST_MEM option.
*/
.rtc_noinit (NOLOAD):
{
. = ALIGN(4);
_rtc_noinit_start = ABSOLUTE(.);
*(.rtc_noinit .rtc_noinit.*)
. = ALIGN(4) ;
_rtc_noinit_end = ABSOLUTE(.);
} > rtc_data_location
/* This section located in RTC SLOW Memory area.
It holds data marked with RTC_SLOW_ATTR attribute.
See the file "esp_attr.h" for more information.
*/
.rtc.force_slow :
{
. = ALIGN(4);
_rtc_force_slow_start = ABSOLUTE(.);
*(.rtc.force_slow .rtc.force_slow.*)
. = ALIGN(4) ;
_rtc_force_slow_end = ABSOLUTE(.);
} > rtc_slow_seg
/* Get size of rtc slow data based on rtc_data_location alias */
_rtc_slow_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location))
? (_rtc_force_slow_end - _rtc_data_start)
: (_rtc_force_slow_end - _rtc_force_slow_start);
_rtc_fast_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location))
? (_rtc_force_fast_end - _rtc_fast_start)
: (_rtc_noinit_end - _rtc_fast_start);
ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)),
"RTC_SLOW segment data does not fit.")
ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)),
"RTC_FAST segment data does not fit.")
/* Send .iram0 code to iram */
.iram0.vectors :
{
_iram_start = ABSOLUTE(.);
/* Vectors go to IRAM */
_vector_table = ABSOLUTE(.);
/* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */
. = 0x0;
KEEP(*(.WindowVectors.text));
. = 0x180;
KEEP(*(.Level2InterruptVector.text));
. = 0x1c0;
KEEP(*(.Level3InterruptVector.text));
. = 0x200;
KEEP(*(.Level4InterruptVector.text));
. = 0x240;
KEEP(*(.Level5InterruptVector.text));
. = 0x280;
KEEP(*(.DebugExceptionVector.text));
. = 0x2c0;
KEEP(*(.NMIExceptionVector.text));
. = 0x300;
KEEP(*(.KernelExceptionVector.text));
. = 0x340;
KEEP(*(.UserExceptionVector.text));
. = 0x3C0;
KEEP(*(.DoubleExceptionVector.text));
. = 0x400;
_invalid_pc_placeholder = ABSOLUTE(.);
*(.*Vector.literal)
*(.UserEnter.literal);
*(.UserEnter.text);
. = ALIGN (16);
*(.entry.text)
*(.init.literal)
*(.init)
_init_end = ABSOLUTE(.);
} > iram0_0_seg
/* If Bluetooth is not used, this DRAM section can be used as heap */
. = _data_start_btdm; /* 0x3ffae6e0 */
. = ALIGN (4);
_sheap1 = ABSOLUTE(.);
. = 0x3ffb0000;
_eheap1 = ABSOLUTE(.);
.iram0.text :
{
/* Code marked as running out of IRAM */
_iram_text_start = ABSOLUTE(.);
*(.iram1 .iram1.*)
/* Xtensa basic functionality written in assembler should be placed in IRAM */
*xtensa/*(.literal .text .literal.* .text.*)
/* parts of RIOT that should run in IRAM */
*core/*(.literal .text .literal.* .text.*)
*syscalls.*(.literal .text .literal.* .text.*)
*esp_common_periph/flash.*(.literal .text .literal.* .text.*)
*esp_common/thread_arch.*(.literal .text .literal.* .text.*)
*esp_freertos_common/*(.literal .text .literal.* .text.*)
/* parts of ESP-IDF that should run in IRAM */
/* find components/ -type f -name linker.lf -exec grep "(noflash)" {} \; -print */
/* find components/ -type f -name linker.lf -exec grep "(noflash_text)" {} \; -print */
*components/app_trace/app_trace.*(.literal .literal.* .text .text.*)
*components/app_trace/app_trace_util.*(.literal .literal.* .text .text.*)
*components/esp_event/default_event_loop.*(.literal.esp_event_isr_post .text.esp_event_isr_post)
*components/esp_event/esp_event.*(.literal.esp_event_isr_post_to .text.esp_event_isr_post_to)
*components/esp_hw_support/cpu_util.*(.literal .literal.* .text .text.*)
*components/esp_hw_support/*/rtc_clk.*(.literal .literal.* .text .text.*)
*components/esp_hw_support/*/rtc_init.*(.literal.rtc_vddsdio_set_config .text.rtc_vddsdio_set_config)
*components/esp_hw_support/*/rtc_pm.*(.literal .literal.* .text .text.*)
*components/esp_hw_support/*/rtc_sleep.*(.literal .literal.* .text .text.*)
*components/esp_hw_support/*/rtc_time.*(.literal .literal.* .text .text.*)
*components/esp_hw_support/*/rtc_wdt.*(.literal .literal.* .text .text.*)
*components/esp_ringbuf/*(.literal .literal.* .text .text.*)
*components/esp_rom/esp_rom_spiflash.*(.literal .literal.* .text .text.*)
*components/esp_system/esp_err.*(.literal .literal.* .text .text.*)
*components/esp_system/esp_system.*(.literal.esp_system_abort .text.esp_system_abort)
*components/esp_system/ubsan.*(.literal .literal.* .text .text.*)
*libgcc.a:_divsf3.*(.literal .literal.* .text .text.*)
*libgcc.a:lib2funcs.*(.literal .literal.* .text .text.*)
*libgcc.a:save-restore.*(.literal .literal.* .text .text.*)
*libgcov.a:(.literal .literal.* .text .text.*)
*components/hal/cpu_hal.*(.literal .literal.* .text .text.*)
*components/hal/i2c_hal_iram.*(.literal .literal.* .text .text.*)
*components/hal/ledc_hal_iram.*(.literal .literal.* .text .text.*)
*components/hal/soc_hal.*(.literal .literal.* .text .text.*)
*components/hal/spi_flash_encrypt_hal_iram.*(.literal .literal.* .text .text.*)
*components/hal/spi_flash_hal_gpspi.*(.literal .literal.* .text .text.*)
*components/hal/spi_flash_hal_iram.*(.literal .literal.* .text .text.*)
*components/hal/spi_hal_iram.*(.literal .literal.* .text .text.*)
*components/hal/spi_slave_hal_iram.*(.literal .literal.* .text .text.*)
*components/hal/systimer_hal.*(.literal .literal.* .text .text.*)
*components/hal/twai_hal.*(.literal .literal.* .text .text.*)
*components/hal/uart_hal.*(.literal .literal.* .text .text.*)
*components/hal/wdt_hal_iram.*(.literal .literal.* .text .text.*)
*components/heap/heap_tlsf.*(.literal .literal.* .text .text.*)
*components/heap/multi_heap.*(.literal .literal.* .text .text.*)
*esp-idf/esp_idf_support.*(.literal.esp_log_write .text.esp_log_write)
*libnet80211.a:(.wifi0iram .wifi0iram.*)
*libnet80211.a:(.wifirxiram .wifirxiram.*)
*libnet80211.a:(.wifislprxiram .wifislprxiram.*)
*components/newlib/abort.*(.literal .literal.* .text .text.*)
*components/newlib/assert.*(.literal .literal.* .text .text.*)
*components/newlib/heap.*(.literal .literal.* .text .text.*)
*components/newlib/stdatomic.*(.literal .literal.* .text .text.*)
*libpp.a:(.wifi0iram .wifi0iram.*)
*libpp.a:(.wifiorslpiram .wifiorslpiram.*)
*libpp.a:(.wifirxiram .wifirxiram.*)
*libpp.a:(.wifislprxiram .wifislprxiram.*)
*librtc.a:(.literal .literal.* .text .text.*)
*components/soc/lldesc.*(.literal .literal.* .text .text.*)
*components/spi_flash/memspi_host_driver.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_chip_boya.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_chip_gd.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_chip_generic.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_chip_issi.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_chip_mxic.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_chip_mxic_opi.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_chip_th.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_chip_winbond.*(.literal .literal.* .text .text.*)
*components/spi_flash/*/spi_flash_rom_patch.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_timing_tuning.*(.literal .literal.* .text .text.*)
*components/spi_flash/*/spi_timing_config.*(.literal .literal.* .text .text.*)
*libxt_hal.a:(.literal .literal.* .text .text.*)
*libxtensa.a:eri.*(.literal .literal.* .text .text.*)
*libxtensa.a:xtensa_intr_asm.*(.literal .literal.* .text .text.*)
} > iram0_0_seg
.dram0.data :
{
_data_start = ABSOLUTE(.);
*(.gnu.linkonce.d.*)
*(.data1)
*(.sdata)
*(.sdata.*)
KEEP (*(SORT(.xfa.*)))
*(.gnu.linkonce.s.*)
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
*(.jcr)
_esp_system_init_fn_array_start = ABSOLUTE(.);
KEEP (*(SORT(.esp_system_init_fn) SORT(.esp_system_init_fn.*)))
_esp_system_init_fn_array_end = ABSOLUTE(.);
*(EXCLUDE_FILE(*components/bt/* *libbtdm_app.a) .data EXCLUDE_FILE(*components/bt/* *libbtdm_app.a) .data.*)
*(.dram1 .dram1.*)
_coredump_dram_start = ABSOLUTE(.);
*(.dram1.coredump .dram1.coredump.*)
_coredump_dram_end = ABSOLUTE(.);
*components/app_trace/app_trace.*(.rodata .rodata.*)
*components/app_trace/app_trace_util.*(.rodata .rodata.*)
_bt_data_start = ABSOLUTE(.);
*components/bt/*(.data .data.*)
. = ALIGN(4);
_bt_data_end = ABSOLUTE(.);
_btdm_data_start = ABSOLUTE(.);
*libbtdm_app.a:(.data .data.*)
. = ALIGN(4);
_btdm_data_end = ABSOLUTE(.);
/* find components/ -type f -name linker.lf -exec grep "(noflash)" {} \; -print */
*components/esp_hw_support/port/*/rtc_clk.*(.rodata .rodata.*)
*components/esp_rom/esp_rom_spiflash.*(.rodata .rodata.*)
*components/esp_system/esp_err.*(.rodata .rodata.*)
*components/esp_system/ubsan.*(.rodata .rodata.*)
*libgcc.a:_divsf3.*(.rodata .rodata.*)
*libgcc.a:save-restore.*(.rodata .rodata.*)
*libgcov.a:(.rodata .rodata.*)
*components/hal/cpu_hal.*(.rodata .rodata.*)
*components/hal/i2c_hal_iram.*(.rodata .rodata.*)
*components/hal/ledc_hal_iram.*(.rodata .rodata.*)
*components/hal/soc_hal.*(.rodata .rodata.*)
*components/hal/spi_flash_encrypt_hal_iram.*(.rodata .rodata.*)
*components/hal/spi_flash_hal_gpspi.*(.rodata .rodata.*)
*components/hal/spi_flash_hal_iram.*(.rodata .rodata.*)
*components/hal/spi_hal_iram.*(.rodata .rodata.*)
*components/hal/spi_slave_hal_iram.*(.rodata .rodata.*)
*components/hal/systimer_hal.*(.rodata .rodata.*)
*components/hal/twai_hal.*(.rodata .rodata.*)
*components/hal/uart_hal.*(.rodata .rodata.*)
*components/hal/wdt_hal_iram.*(.rodata .rodata.*)
*components/heap/heap_tlsf.*(.rodata .rodata.*)
*components/heap/multi_heap.*(.rodata .rodata.*)
*components/newlib/abort.*(.rodata .rodata.*)
*components/newlib/assert.*(.rodata .rodata.*)
*components/newlib/heap.*(.rodata .rodata.*)
*components/newlib/stdatomic.*(.rodata .rodata.*)
_nimble_data_start = ABSOLUTE(.);
*libnimble.a:(.data .data.*)
. = ALIGN(4);
_nimble_data_end = ABSOLUTE(.);
*libphy.a:(.rodata .rodata.*)
*components/soc/lldesc.*(.rodata .rodata.*)
*components/spi_flash/memspi_host_driver.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_chip_boya.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_chip_gd.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_chip_generic.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_chip_issi.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_chip_mxic.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_chip_mxic_opi.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_chip_th.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_chip_winbond.*(.rodata .rodata.*)
*components/spi_flash/*/spi_flash_rom_patch.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_timing_tuning.*(.rodata .rodata.*)
*components/spi_flash/*/spi_timing_config.*(.rodata .rodata.*)
_data_end = ABSOLUTE(.);
. = ALIGN(4);
} > dram0_0_seg
/**
* This section holds data that won't be initialised when startup.
* This section locates in External RAM region.
*/
.ext_ram_noinit (NOLOAD) :
{
_ext_ram_noinit_start = ABSOLUTE(.);
*(.ext_ram_noinit*)
. = ALIGN(4);
_ext_ram_noinit_end = ABSOLUTE(.);
} > extern_ram_seg
/*This section holds data that should not be initialized at power up.
The section located in Internal SRAM memory region. The macro _NOINIT
can be used as attribute to place data into this section.
See the esp_attr.h file for more information.
*/
.noinit (NOLOAD):
{
. = ALIGN(4);
_noinit_start = ABSOLUTE(.);
*(.noinit .noinit.*)
. = ALIGN(4) ;
_noinit_end = ABSOLUTE(.);
} > dram0_0_seg
/* external memory bss, from any global variable with EXT_RAM_ATTR attribute*/
.ext_ram.bss (NOLOAD) :
{
_ext_ram_bss_start = ABSOLUTE(.);
. = ALIGN(4);
_ext_ram_bss_end = ABSOLUTE(.);
} > extern_ram_seg
/* Shared RAM */
.dram0.bss (NOLOAD) :
{
. = ALIGN (8);
_bss_start = ABSOLUTE(.);
*(.bss .bss.*)
*(.ext_ram.bss .ext_ram.bss.*)
*(.dynbss .dynsbss .gnu.linkonce.b .gnu.linkonce.b.* .gnu.linkonce.sb .gnu.linkonce.sb.* .gnu.linkonce.sb2 .gnu.linkonce.sb2.* .sbss .sbss.* .sbss2 .sbss2.* .scommon .share.mem)
*(COMMON)
_bt_bss_start = ABSOLUTE(.);
*components/bt/*(.bss .bss.* COMMON)
. = ALIGN(4);
_bt_bss_end = ABSOLUTE(.);
_btdm_bss_start = ABSOLUTE(.);
*libbtdm_app.a:(.bss .bss.* COMMON)
. = ALIGN(4);
_btdm_bss_end = ABSOLUTE(.);
_nimble_bss_start = ABSOLUTE(.);
*libnimble.a:(.bss .bss.* COMMON)
. = ALIGN(4);
_nimble_bss_end = ABSOLUTE(.);
. = ALIGN (8);
_bss_end = ABSOLUTE(.);
} > dram0_0_seg
ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),
"DRAM segment data does not fit.")
/* Reserved ROM/ETS data start at 0x3ffe000. */
. = 0x3ffe0000;
_heap_top = ABSOLUTE(.);
_eheap = ABSOLUTE(.);
/* Reserved ROM/ETS data region for PRO CPU: 0x3ffe0000 ... 0x3ffe440 */
. = 0x3ffe0440;
_sheap2 = ABSOLUTE(.);
. = 0x3ffe4000;
_eheap2 = ABSOLUTE(.);
/* Reserved ROM/ETS data region for APP CPU: 0x3ffe4000 ... 0x3ffe4350 */
. = 0x3ffe4350;
_sheap3 = ABSOLUTE(.);
. = 0x40000000;
_eheap3 = ABSOLUTE(.);
.flash.appdesc : ALIGN(0x10)
{
_rodata_start = ABSOLUTE(.);
*(.rodata_desc .rodata_desc.*) /* Should be the first. App version info. DO NOT PUT ANYTHING BEFORE IT! */
*(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */
/* Create an empty gap within this section. Thanks to this, the end of this
* section will match .flah.rodata's begin address. Thus, both sections
* will be merged when creating the final bin image. */
. = ALIGN(ALIGNOF(.flash.rodata));
} >default_rodata_seg
.flash.rodata : ALIGN(0x10)
{
_flash_rodata_start = ABSOLUTE(.);
*(.rodata .rodata.*)
*(.rodata_wlog_error .rodata_wlog_error.*)
*(.rodata_wlog_info .rodata_wlog_info.*)
*(.rodata_wlog_warning .rodata_wlog_warning.*)
KEEP (*(SORT(.roxfa.*)))
*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
*(.xt_except_table)
*(.gcc_except_table .gcc_except_table.*)
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
. = (. + 3) & ~ 3;
__eh_frame = ABSOLUTE(.);
KEEP(*(.eh_frame))
. = (. + 7) & ~ 3;
/* C++ constructor and destructor tables
Make a point of not including anything from crtbegin.o or crtend.o, as IDF doesn't use toolchain crt
*/
__init_array_start = ABSOLUTE(.);
KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .ctors SORT(.ctors.*)))
__init_array_end = ABSOLUTE(.);
KEEP (*crtbegin.*(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
/* Addresses of memory regions reserved via
SOC_RESERVE_MEMORY_REGION() */
soc_reserved_memory_region_start = ABSOLUTE(.);
KEEP (*(.reserved_memory_address))
soc_reserved_memory_region_end = ABSOLUTE(.);
_rodata_end = ABSOLUTE(.);
/* Literals are also RO data. */
_lit4_start = ABSOLUTE(.);
*(*.lit4)
*(.lit4.*)
*(.gnu.linkonce.lit4.*)
_lit4_end = ABSOLUTE(.);
. = ALIGN(4);
_thread_local_start = ABSOLUTE(.);
*(.tdata)
*(.tdata.*)
*(.tbss)
*(.tbss.*)
_thread_local_end = ABSOLUTE(.);
. = ALIGN(4);
} >default_rodata_seg
_flash_rodata_align = ALIGNOF(.flash.rodata);
.flash.rodata_noload (NOLOAD) :
{
. = ALIGN (4);
*(.rodata_wlog_debug .rodata_wlog_debug.*)
*(.rodata_wlog_verbose .rodata_wlog_verbose.*)
} > default_rodata_seg
.flash.text :
{
_stext = .;
_text_start = ABSOLUTE(.);
*(.literal .literal.* .text .text.*)
*(.wifi0iram .wifi0iram.*)
*(.wifiorslpiram .wifiorslpiram.*)
*(.wifirxiram .wifirxiram.*)
*(.wifislpiram .wifislpiram.*)
*(.wifislprxiram .wifislprxiram.*)
*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
*(.fini.literal)
*(.fini)
*(.gnu.version)
/** CPU will try to prefetch up to 16 bytes of
* of instructions. This means that any configuration (e.g. MMU, PMS) must allow
* safe access to up to 16 bytes after the last real instruction, add
* dummy bytes to ensure this
*/
. += _esp_flash_mmap_prefetch_pad_size;
_text_end = ABSOLUTE(.);
_etext = .;
/* Similar to _iram_start, this symbol goes here so it is
resolved by addr2line in preference to the first symbol in
the flash.text segment.
*/
_flash_cache_start = ABSOLUTE(0);
} >default_code_seg
/* Marks the end of IRAM code segment */
.iram0.text_end (NOLOAD) :
{
. = ALIGN (4);
_iram_text_end = ABSOLUTE(.);
} > iram0_0_seg
.iram0.data :
{
. = ALIGN(4);
_iram_data_start = ABSOLUTE(.);
*(.iram.data .iram.data.*)
_coredump_iram_start = ABSOLUTE(.);
*(.iram.data.coredump .iram.data.coredump.*)
_coredump_iram_end = ABSOLUTE(.);
_iram_data_end = ABSOLUTE(.);
} > iram0_0_seg
.iram0.bss (NOLOAD) :
{
. = ALIGN(4);
_iram_bss_start = ABSOLUTE(.);
*(.iram.bss .iram.bss.*)
_iram_bss_end = ABSOLUTE(.);
. = ALIGN(4);
_iram_end = ABSOLUTE(.);
} > iram0_0_seg
/* Marks the end of data, bss and possibly rodata */
.dram0.heap_start (NOLOAD) :
{
. = ALIGN (8);
_heap_start = ABSOLUTE(.);
_sheap = ABSOLUTE(.);
} > dram0_0_seg
#ifdef MODULE_PERIPH_FLASHPAGE
.flash_writable (NOLOAD) : ALIGN(65536)
{
_fp_mem_start = . ;
KEEP(*(SORT(.flash_writable.*)))
_fp_mem_end = . ;
. = ALIGN(4096);
_end_fw = . ;
} > drom0_1_seg
#endif
}
ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),
"IRAM0 segment data does not fit.")
ASSERT(((_heap_start - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),
"DRAM segment data does not fit.")
. = ORIGIN(dram0_0_seg);
_cpu_ram_start = ABSOLUTE(.);
. = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);
_cpu_ram_end = ABSOLUTE(.);
/* ensure that RAM_START_ADDR and RAM_LEN as defined in RIOT's makefile
* match the parameters used in linker script */
ASSERT((ORIGIN(dram0_0_seg) == CPU_RAM_BASE),
"RAM_START_ADDR does not match DRAM start address")
ASSERT(((LENGTH(dram0_0_seg) - 0x200) == CPU_RAM_SIZE),
"RAM_LEN does not match DRAM size")

630
cpu/esp32/ld/esp32c3/sections.ld.in
View File

@ -1,630 +0,0 @@
/* Automatically generated file; DO NOT EDIT */
/* Espressif IoT Development Framework Linker Script */
/* Generated from: esp-idf/components/esp_system/ld/esp32c3/sections.ld.in */
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Default entry point */
ENTRY(call_start_cpu0);
SECTIONS
{
/**
* RTC fast memory holds RTC wake stub code,
* including from any source file named rtc_wake_stub*.c
*/
.rtc.text :
{
. = ALIGN(4);
_rtc_fast_start = ABSOLUTE(.);
*(.rtc.literal .rtc.text .rtc.text.*)
*rtc_wake_stub*.*(.literal .text .literal.* .text.*)
*(.rtc_text_end_test)
/* 16B padding for possible CPU prefetch and 4B alignment for PMS split lines */
. += _esp_memprot_prefetch_pad_size;
. = ALIGN(4);
_rtc_text_end = ABSOLUTE(.);
} > rtc_iram_seg
/**
* This section located in RTC FAST Memory area.
* It holds data marked with RTC_FAST_ATTR attribute.
* See the file "esp_attr.h" for more information.
*/
.rtc.force_fast :
{
. = ALIGN(4);
_rtc_force_fast_start = ABSOLUTE(.);
_coredump_rtc_fast_start = ABSOLUTE(.);
*(.rtc.fast.coredump .rtc.fast.coredump.*)
_coredump_rtc_fast_end = ABSOLUTE(.);
*(.rtc.force_fast .rtc.force_fast.*)
. = ALIGN(4) ;
_rtc_force_fast_end = ABSOLUTE(.);
} > rtc_data_seg
/**
* RTC data section holds RTC wake stub
* data/rodata, including from any source file
* named rtc_wake_stub*.c and the data marked with
* RTC_DATA_ATTR, RTC_RODATA_ATTR attributes.
*/
.rtc.data :
{
_rtc_data_start = ABSOLUTE(.);
_coredump_rtc_start = ABSOLUTE(.);
*(.rtc.coredump .rtc.coredump.*)
_coredump_rtc_end = ABSOLUTE(.);
*(.rtc.data .rtc.data.*)
*(.rtc.rodata .rtc.rodata.*)
*rtc_wake_stub*.*(.data .rodata .data.* .rodata.* .bss .bss.*)
_rtc_data_end = ABSOLUTE(.);
} > rtc_data_location
/* RTC bss, from any source file named rtc_wake_stub*.c */
.rtc.bss (NOLOAD) :
{
/* part that is initialized if not waking up from deep sleep */
_rtc_bss_start = ABSOLUTE(.);
*rtc_wake_stub*.*(.bss .bss.*)
*rtc_wake_stub*.*(COMMON)
_rtc_bss_end = ABSOLUTE(.);
/* part that saves some data for rtc periph module, this part is
only initialized at power on reset */
_rtc_bss_rtc_start = ABSOLUTE(.);
*(.rtc.bss .rtc.bss.*)
_rtc_bss_rtc_end = ABSOLUTE(.);
} > rtc_data_location
/**
* This section holds data that should not be initialized at power up
* and will be retained during deep sleep.
* User data marked with RTC_NOINIT_ATTR will be placed
* into this section. See the file "esp_attr.h" for more information.
*/
.rtc_noinit (NOLOAD):
{
. = ALIGN(4);
_rtc_noinit_start = ABSOLUTE(.);
*(.rtc_noinit .rtc_noinit.*)
. = ALIGN(4) ;
_rtc_noinit_end = ABSOLUTE(.);
} > rtc_data_location
/**
* This section located in RTC SLOW Memory area.
* It holds data marked with RTC_SLOW_ATTR attribute.
* See the file "esp_attr.h" for more information.
*/
.rtc.force_slow :
{
. = ALIGN(4);
_rtc_force_slow_start = ABSOLUTE(.);
*(.rtc.force_slow .rtc.force_slow.*)
. = ALIGN(4) ;
_rtc_force_slow_end = ABSOLUTE(.);
} > rtc_slow_seg
/* Get size of rtc slow data based on rtc_data_location alias */
_rtc_slow_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location))
? (_rtc_force_slow_end - _rtc_data_start)
: (_rtc_force_slow_end - _rtc_force_slow_start);
_rtc_fast_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location))
? (_rtc_force_fast_end - _rtc_fast_start)
: (_rtc_noinit_end - _rtc_fast_start);
ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)),
"RTC_SLOW segment data does not fit.")
ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)),
"RTC_FAST segment data does not fit.")
.iram0.text :
{
_iram_start = ABSOLUTE(.);
/* Vectors go to start of IRAM */
ASSERT(ABSOLUTE(.) % 0x100 == 0, "vector address must be 256 byte aligned");
KEEP(*(.exception_vectors.text));
. = ALIGN(4);
_invalid_pc_placeholder = ABSOLUTE(.);
/* Code marked as running out of IRAM */
_iram_text_start = ABSOLUTE(.);
*(.iram1 .iram1.*)
/* parts of RIOT that should run in IRAM */
*core/*(.literal .text .literal.* .text.*)
*esp_common_periph/flash.*(.literal .text .literal.* .text.*)
*esp_common/thread_arch.*(.literal .text .literal.* .text.*)
*esp_freertos_common/*(.literal .text .literal.* .text.*)
/* parts of ESP-IDF that should run in IRAM */
/* find components/ -type f -name linker.lf -exec grep "(noflash)" {} \; -print */
/* find components/ -type f -name linker.lf -exec grep "(noflash_text)" {} \; -print */
*components/app_trace/app_trace.*(.literal .literal.* .text .text.*)
*components/app_trace/app_trace_util.*(.literal .literal.* .text .text.*)
*components/esp_event/default_event_loop.*(.literal.esp_event_isr_post .text.esp_event_isr_post)
*components/esp_event/esp_event.*(.literal.esp_event_isr_post_to .text.esp_event_isr_post_to)
*components/esp_hw_support/cpu_util.*(.literal .literal.* .text .text.*)
*components/esp_hw_support/*/rtc_clk.*(.literal .literal.* .text .text.*)
*components/esp_hw_support/*/rtc_init.*(.literal.rtc_vddsdio_set_config .text.rtc_vddsdio_set_config)
*components/esp_hw_support/*/rtc_pm.*(.literal .literal.* .text .text.*)
*components/esp_hw_support/*/rtc_sleep.*(.literal .literal.* .text .text.*)
*components/esp_hw_support/*/rtc_time.*(.literal .literal.* .text .text.*)
*components/esp_hw_support/*/rtc_wdt.*(.literal .literal.* .text .text.*)
*components/esp_ringbuf/*(.literal .literal.* .text .text.*)
*components/esp_rom/esp_rom_spiflash.*(.literal .literal.* .text .text.*)
*components/esp_system/esp_err.*(.literal .literal.* .text .text.*)
*components/esp_system/esp_system.*(.literal.esp_system_abort .text.esp_system_abort)
*components/esp_system/ubsan.*(.literal .literal.* .text .text.*)
*libgcc.a:_divsf3.*(.literal .literal.* .text .text.*)
*libgcc.a:lib2funcs.*(.literal .literal.* .text .text.*)
*libgcc.a:save-restore.*(.literal .literal.* .text .text.*)
*libgcov.a:(.literal .literal.* .text .text.*)
*components/hal/cpu_hal.*(.literal .literal.* .text .text.*)
*components/hal/i2c_hal_iram.*(.literal .literal.* .text .text.*)
*components/hal/ledc_hal_iram.*(.literal .literal.* .text .text.*)
*components/hal/soc_hal.*(.literal .literal.* .text .text.*)
*components/hal/spi_flash_encrypt_hal_iram.*(.literal .literal.* .text .text.*)
*components/hal/spi_flash_hal_gpspi.*(.literal .literal.* .text .text.*)
*components/hal/spi_flash_hal_iram.*(.literal .literal.* .text .text.*)
*components/hal/spi_hal_iram.*(.literal .literal.* .text .text.*)
*components/hal/spi_slave_hal_iram.*(.literal .literal.* .text .text.*)
*components/hal/systimer_hal.*(.literal .literal.* .text .text.*)
*components/hal/twai_hal.*(.literal .literal.* .text .text.*)
*components/hal/uart_hal.*(.literal .literal.* .text .text.*)
*components/hal/wdt_hal_iram.*(.literal .literal.* .text .text.*)
*components/heap/heap_tlsf.*(.literal .literal.* .text .text.*)
*components/heap/multi_heap.*(.literal .literal.* .text .text.*)
*esp-idf/esp_idf_support.*(.literal.esp_log_write .text.esp_log_write)
*libnet80211.a:(.wifi0iram .wifi0iram.*)
*libnet80211.a:(.wifirxiram .wifirxiram.*)
*libnet80211.a:(.wifislprxiram .wifislprxiram.*)
*components/newlib/abort.*(.literal .literal.* .text .text.*)
*components/newlib/assert.*(.literal .literal.* .text .text.*)
*components/newlib/heap.*(.literal .literal.* .text .text.*)
*components/newlib/stdatomic.*(.literal .literal.* .text .text.*)
*libpp.a:(.wifi0iram .wifi0iram.*)
*libpp.a:(.wifiorslpiram .wifiorslpiram.*)
*libpp.a:(.wifirxiram .wifirxiram.*)
*libpp.a:(.wifislprxiram .wifislprxiram.*)
*librtc.a:(.literal .literal.* .text .text.*)
*components/soc/lldesc.*(.literal .literal.* .text .text.*)
*components/spi_flash/memspi_host_driver.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_chip_boya.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_chip_gd.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_chip_generic.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_chip_issi.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_chip_mxic.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_chip_mxic_opi.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_chip_th.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_chip_winbond.*(.literal .literal.* .text .text.*)
*components/spi_flash/*/spi_flash_rom_patch.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_timing_tuning.*(.literal .literal.* .text .text.*)
*components/spi_flash/*/spi_timing_config.*(.literal .literal.* .text .text.*)
*components/riscv/interrupt.*(.literal .literal.* .text .text.*)
*components/riscv/vectors.*(.literal .literal.* .text .text.*)
} > iram0_0_seg
/**
* This section is required to skip .iram0.text area because iram0_0_seg and
* dram0_0_seg reflect the same address space on different buses.
*/
.dram0.dummy (NOLOAD):
{
. = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;
} > dram0_0_seg
.dram0.data :
{
_data_start = ABSOLUTE(.);
*(.gnu.linkonce.d.*)
*(.data1)
__global_pointer$ = . + 0x800;
*(.sdata)
*(.sdata.*)
KEEP (*(SORT(.xfa.*)))
*(.gnu.linkonce.s.*)
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
*(.jcr)
_esp_system_init_fn_array_start = ABSOLUTE(.);
KEEP (*(SORT(.esp_system_init_fn) SORT(.esp_system_init_fn.*)))
_esp_system_init_fn_array_end = ABSOLUTE(.);
*(EXCLUDE_FILE(*components/bt/* *libbtdm_app.a) .data EXCLUDE_FILE(*components/bt/* *libbtdm_app.a) .data.*)
*(.dram1 .dram1.*)
_coredump_dram_start = ABSOLUTE(.);
*(.dram1.coredump .dram1.coredump.*)
_coredump_dram_end = ABSOLUTE(.);
*components/app_trace/app_trace.*(.rodata .rodata.*)
*components/app_trace/app_trace_util.*(.rodata .rodata.*)
_bt_data_start = ABSOLUTE(.);
*components/bt/*(.data .data.*)
. = ALIGN(4);
_bt_data_end = ABSOLUTE(.);
_btdm_data_start = ABSOLUTE(.);
*libbtdm_app.a:(.data .data.*)
. = ALIGN(4);
_btdm_data_end = ABSOLUTE(.);
/* find components/ -type f -name linker.lf -exec grep "(noflash)" {} \; -print */
*components/esp_hw_support/port/*/rtc_clk.*(.rodata .rodata.*)
*components/esp_rom/esp_rom_spiflash.*(.rodata .rodata.*)
*components/esp_system/esp_err.*(.rodata .rodata.*)
*components/esp_system/ubsan.*(.rodata .rodata.*)
*libgcc.a:_divsf3.*(.rodata .rodata.*)
*libgcc.a:save-restore.*(.rodata .rodata.*)
*libgcov.a:(.rodata .rodata.*)
*components/hal/cpu_hal.*(.rodata .rodata.*)
*components/hal/i2c_hal_iram.*(.rodata .rodata.*)
*components/hal/ledc_hal_iram.*(.rodata .rodata.*)
*components/hal/soc_hal.*(.rodata .rodata.*)
*components/hal/spi_flash_encrypt_hal_iram.*(.rodata .rodata.*)
*components/hal/spi_flash_hal_gpspi.*(.rodata .rodata.*)
*components/hal/spi_flash_hal_iram.*(.rodata .rodata.*)
*components/hal/spi_hal_iram.*(.rodata .rodata.*)
*components/hal/spi_slave_hal_iram.*(.rodata .rodata.*)
*components/hal/systimer_hal.*(.rodata .rodata.*)
*components/hal/twai_hal.*(.rodata .rodata.*)
*components/hal/uart_hal.*(.rodata .rodata.*)
*components/hal/wdt_hal_iram.*(.rodata .rodata.*)
*components/heap/heap_tlsf.*(.rodata .rodata.*)
*components/heap/multi_heap.*(.rodata .rodata.*)
*components/newlib/abort.*(.rodata .rodata.*)
*components/newlib/assert.*(.rodata .rodata.*)
*components/newlib/heap.*(.rodata .rodata.*)
*components/newlib/stdatomic.*(.rodata .rodata.*)
_nimble_data_start = ABSOLUTE(.);
*libnimble.a:(.data .data.*)
. = ALIGN(4);
_nimble_data_end = ABSOLUTE(.);
*libphy.a:(.rodata .rodata.*)
*components/soc/lldesc.*(.rodata .rodata.*)
*components/spi_flash/memspi_host_driver.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_chip_boya.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_chip_gd.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_chip_generic.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_chip_issi.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_chip_mxic.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_chip_mxic_opi.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_chip_th.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_chip_winbond.*(.rodata .rodata.*)
*components/spi_flash/*/spi_flash_rom_patch.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_timing_tuning.*(.rodata .rodata.*)
*components/spi_flash/*/spi_timing_config.*(.rodata .rodata.*)
_data_end = ABSOLUTE(.);
. = ALIGN(4);
} > dram0_0_seg
/**
* This section holds data that should not be initialized at power up.
* The section located in Internal SRAM memory region. The macro _NOINIT
* can be used as attribute to place data into this section.
* See the "esp_attr.h" file for more information.
*/
.noinit (NOLOAD):
{
. = ALIGN(4);
_noinit_start = ABSOLUTE(.);
*(.noinit .noinit.*)
. = ALIGN(4) ;
_noinit_end = ABSOLUTE(.);
} > dram0_0_seg
/* Shared RAM */
.dram0.bss (NOLOAD) :
{
. = ALIGN (8);
_bss_start = ABSOLUTE(.);
*(.bss .bss.*)
*(.ext_ram.bss .ext_ram.bss.*)
*(.dynbss .dynsbss .gnu.linkonce.b .gnu.linkonce.b.* .gnu.linkonce.sb .gnu.linkonce.sb.* .gnu.linkonce.sb2 .gnu.linkonce.sb2.* .sbss .sbss.* .sbss2 .sbss2.* .scommon .share.mem)
*(COMMON)
_bt_bss_start = ABSOLUTE(.);
*components/bt/*(.bss .bss.* COMMON)
. = ALIGN(4);
_bt_bss_end = ABSOLUTE(.);
_btdm_bss_start = ABSOLUTE(.);
*libbtdm_app.a:(.bss .bss.* COMMON)
. = ALIGN(4);
_btdm_bss_end = ABSOLUTE(.);
_nimble_bss_start = ABSOLUTE(.);
*libnimble.a:(.bss .bss.* COMMON)
. = ALIGN(4);
_nimble_bss_end = ABSOLUTE(.);
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.share.mem)
*(.gnu.linkonce.b.*)
. = ALIGN (8);
_bss_end = ABSOLUTE(.);
} > dram0_0_seg
ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.")
.flash.text :
{
_stext = .;
_instruction_reserved_start = ABSOLUTE(.);
_text_start = ABSOLUTE(.);
*(.literal .literal.* .text .text.*)
*(.wifi0iram .wifi0iram.*)
*(.wifiorslpiram .wifiorslpiram.*)
*(.wifirxiram .wifirxiram.*)
*(.wifislpiram .wifislpiram.*)
*(.wifislprxiram .wifislprxiram.*)
*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
*(.fini.literal)
*(.fini)
*(.gnu.version)
/** CPU will try to prefetch up to 16 bytes of
* of instructions. This means that any configuration (e.g. MMU, PMS) must allow
* safe access to up to 16 bytes after the last real instruction, add
* dummy bytes to ensure this
*/
. += _esp_flash_mmap_prefetch_pad_size;
_text_end = ABSOLUTE(.);
_instruction_reserved_end = ABSOLUTE(.);
_etext = .;
/**
* Similar to _iram_start, this symbol goes here so it is
* resolved by addr2line in preference to the first symbol in
* the flash.text segment.
*/
_flash_cache_start = ABSOLUTE(0);
} > default_code_seg
/**
* This dummy section represents the .flash.text section but in default_rodata_seg.
* Thus, it must have its alignement and (at least) its size.
*/
.flash_rodata_dummy (NOLOAD):
{
_flash_rodata_dummy_start = .;
/* Start at the same alignement constraint than .flash.text */
. = ALIGN(ALIGNOF(.flash.text));
/* Create an empty gap as big as .flash.text section */
. = . + SIZEOF(.flash.text);
/* Prepare the alignement of the section above. Few bytes (0x20) must be
* added for the mapping header. */
. = ALIGN(0x10000) + 0x20;
_rodata_reserved_start = .;
} > default_rodata_seg
.flash.appdesc : ALIGN(0x10)
{
_rodata_start = ABSOLUTE(.);
*(.rodata_desc .rodata_desc.*) /* Should be the first. App version info. DO NOT PUT ANYTHING BEFORE IT! */
*(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */
/* Create an empty gap within this section. Thanks to this, the end of this
* section will match .flash.rodata's begin address. Thus, both sections
* will be merged when creating the final bin image. */
. = ALIGN(ALIGNOF(.flash.rodata));
} >default_rodata_seg
.flash.rodata : ALIGN(0x10)
{
_flash_rodata_start = ABSOLUTE(.);
*(.rodata .rodata.*)
*(.rodata_wlog_error .rodata_wlog_error.*)
*(.rodata_wlog_info .rodata_wlog_info.*)
*(.rodata_wlog_warning .rodata_wlog_warning.*)
KEEP (*(SORT(.roxfa.*)))
*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
*(.xt_except_table)
*(.gcc_except_table .gcc_except_table.*)
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
. = (. + 7) & ~ 3;
/*
* C++ constructor and destructor tables
* Don't include anything from crtbegin.o or crtend.o, as IDF doesn't use toolchain crt.
*
* RISC-V gcc is configured with --enable-initfini-array so it emits an .init_array section instead.
* But the init_priority sections will be sorted for iteration in ascending order during startup.
* The rest of the init_array sections is sorted for iteration in descending order during startup, however.
* Hence a different section is generated for the init_priority functions which is iterated in
* ascending order during startup. The corresponding code can be found in startup.c.
*/
__init_priority_array_start = ABSOLUTE(.);
KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*))
__init_priority_array_end = ABSOLUTE(.);
__init_array_start = ABSOLUTE(.);
KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array))
__init_array_end = ABSOLUTE(.);
KEEP (*crtbegin.*(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
/* Addresses of memory regions reserved via SOC_RESERVE_MEMORY_REGION() */
soc_reserved_memory_region_start = ABSOLUTE(.);
KEEP (*(.reserved_memory_address))
soc_reserved_memory_region_end = ABSOLUTE(.);
_rodata_end = ABSOLUTE(.);
/* Literals are also RO data. */
_lit4_start = ABSOLUTE(.);
*(*.lit4)
*(.lit4.*)
*(.gnu.linkonce.lit4.*)
_lit4_end = ABSOLUTE(.);
. = ALIGN(4);
_thread_local_start = ABSOLUTE(.);
*(.tdata)
*(.tdata.*)
*(.tbss)
*(.tbss.*)
*(.srodata)
*(.srodata.*)
_thread_local_end = ABSOLUTE(.);
_rodata_reserved_end = ABSOLUTE(.);
. = ALIGN(ALIGNOF(.eh_frame));
} > default_rodata_seg
/* Keep this section shall be at least aligned on 4 */
.eh_frame : ALIGN(8)
{
__eh_frame = ABSOLUTE(.);
KEEP (*(.eh_frame))
__eh_frame_end = ABSOLUTE(.);
/* Guarantee that this section and the next one will be merged by making
* them adjacent. */
. = ALIGN(ALIGNOF(.eh_frame_hdr));
} > default_rodata_seg
/* To avoid any exception in C++ exception frame unwinding code, this section
* shall be aligned on 8. */
.eh_frame_hdr : ALIGN(8)
{
__eh_frame_hdr = ABSOLUTE(.);
KEEP (*(.eh_frame_hdr))
__eh_frame_hdr_end = ABSOLUTE(.);
} > default_rodata_seg
.flash.rodata_noload (NOLOAD) :
{
. = ALIGN (4);
*(.rodata_wlog_debug .rodata_wlog_debug.*)
*(.rodata_wlog_verbose .rodata_wlog_verbose.*)
} > default_rodata_seg
/* Marks the end of IRAM code segment */
.iram0.text_end (NOLOAD) :
{
/* iram_end_test section exists for use by Memprot unit tests only */
*(.iram_end_test)
/* ESP32-C3 memprot requires 16B padding for possible CPU prefetch and 512B alignment for PMS split lines */
. += _esp_memprot_prefetch_pad_size;
. = ALIGN(_esp_memprot_align_size);
_iram_text_end = ABSOLUTE(.);
} > iram0_0_seg
.iram0.data :
{
. = ALIGN(16);
_iram_data_start = ABSOLUTE(.);
*(.iram.data .iram.data.*)
_coredump_iram_start = ABSOLUTE(.);
*(.iram.data.coredump .iram.data.coredump.*)
_coredump_iram_end = ABSOLUTE(.);
_iram_data_end = ABSOLUTE(.);
} > iram0_0_seg
.iram0.bss (NOLOAD) :
{
. = ALIGN(16);
_iram_bss_start = ABSOLUTE(.);
*(.iram.bss .iram.bss.*)
_iram_bss_end = ABSOLUTE(.);
. = ALIGN(16);
_iram_end = ABSOLUTE(.);
} > iram0_0_seg
/* Marks the end of data, bss and possibly rodata */
.dram0.heap_start (NOLOAD) :
{
. = ALIGN (16);
_heap_start = ABSOLUTE(.);
_sheap = ABSOLUTE(.);
} > dram0_0_seg
_eheap = phy_param_rom;
#ifdef MODULE_PERIPH_FLASHPAGE
.flash_writable (NOLOAD) : ALIGN(65536)
{
_fp_mem_start = . ;
KEEP(*(SORT(.flash_writable.*)))
_fp_mem_end = . ;
. = ALIGN(4096);
_end_fw = . ;
} > drom0_1_seg
#endif
}
ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),
"IRAM0 segment data does not fit.")
ASSERT(((_heap_start - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),
"DRAM segment data does not fit.")
. = ORIGIN(dram0_0_seg);
_cpu_ram_start = ABSOLUTE(.);
. = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);
_cpu_ram_end = ABSOLUTE(.);
/* ensure that RAM_START_ADDR and RAM_LEN as defined in RIOT's makefile
* match the parameters used in linker script */
ASSERT((ORIGIN(dram0_0_seg) == CPU_RAM_BASE),
"RAM_START_ADDR does not match DRAM start address")
ASSERT((LENGTH(dram0_0_seg) == CPU_RAM_SIZE),
"RAM_LEN does not match DRAM size")

626
cpu/esp32/ld/esp32s2/sections.ld.in
View File

@ -1,626 +0,0 @@
/* Automatically generated file; DO NOT EDIT */
/* Espressif IoT Development Framework Linker Script */
/* Generated from: /home/gs/tmp/esp-idf-v4.4.1/components/esp_system/ld/esp32s2/sections.ld.in */
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Default entry point: */
ENTRY(call_start_cpu0);
SECTIONS
{
/* RTC fast memory holds RTC wake stub code,
including from any source file named rtc_wake_stub*.c
*/
.rtc.text :
{
_rtc_text_start = ABSOLUTE(.);
. = ALIGN(4);
_rtc_code_start = .;
*(.rtc.literal .rtc.text .rtc.text.*)
*rtc_wake_stub*.*(.literal .text .literal.* .text.*)
_rtc_code_end = .;
/* possibly align + add 16B for CPU dummy speculative instr. fetch */
. = ((_rtc_code_end - _rtc_code_start) == 0) ? ALIGN(0) : ALIGN(4) + 16;
_rtc_text_end = ABSOLUTE(.);
} > rtc_iram_seg
/*
This section is required to skip rtc.text area because rtc_iram_seg and
rtc_data_seg are reflect the same address space on different buses.
*/
.rtc.dummy :
{
_rtc_dummy_start = ABSOLUTE(.);
_rtc_fast_start = ABSOLUTE(.);
. = SIZEOF(.rtc.text);
_rtc_dummy_end = ABSOLUTE(.);
} > rtc_data_seg
/* This section located in RTC FAST Memory area.
It holds data marked with RTC_FAST_ATTR attribute.
See the file "esp_attr.h" for more information.
*/
.rtc.force_fast :
{
. = ALIGN(4);
_rtc_force_fast_start = ABSOLUTE(.);
_coredump_rtc_fast_start = ABSOLUTE(.);
*(.rtc.fast.coredump .rtc.fast.coredump.*)
_coredump_rtc_fast_end = ABSOLUTE(.);
*(.rtc.force_fast .rtc.force_fast.*)
. = ALIGN(4) ;
_rtc_force_fast_end = ABSOLUTE(.);
} > rtc_data_seg
/* RTC data section holds RTC wake stub
data/rodata, including from any source file
named rtc_wake_stub*.c and the data marked with
RTC_DATA_ATTR, RTC_RODATA_ATTR attributes.
The memory location of the data is dependent on
CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM option.
*/
.rtc.data :
{
_rtc_data_start = ABSOLUTE(.);
_coredump_rtc_start = ABSOLUTE(.);
*(.rtc.coredump .rtc.coredump.*)
_coredump_rtc_end = ABSOLUTE(.);
*(.rtc.data .rtc.data.*)
*(.rtc.rodata .rtc.rodata.*)
*rtc_wake_stub*.*(.data .rodata .data.* .rodata.* .bss .bss.*)
_rtc_data_end = ABSOLUTE(.);
} > rtc_data_location
/* RTC bss, from any source file named rtc_wake_stub*.c */
.rtc.bss (NOLOAD) :
{
/* part that is initialized if not waking up from deep sleep */
_rtc_bss_start = ABSOLUTE(.);
*rtc_wake_stub*.*(.bss .bss.*)
*rtc_wake_stub*.*(COMMON)
_rtc_bss_end = ABSOLUTE(.);
/* part that saves some data for rtc periph module, this part is
only initialized at power on reset */
_rtc_bss_rtc_start = ABSOLUTE(.);
*(.rtc.bss .rtc.bss.*)
_rtc_bss_rtc_end = ABSOLUTE(.);
} > rtc_data_location
/* This section holds data that should not be initialized at power up
and will be retained during deep sleep.
User data marked with RTC_NOINIT_ATTR will be placed
into this section. See the file "esp_attr.h" for more information.
The memory location of the data is dependent on
CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM option.
*/
.rtc_noinit (NOLOAD):
{
. = ALIGN(4);
_rtc_noinit_start = ABSOLUTE(.);
*(.rtc_noinit .rtc_noinit.*)
. = ALIGN(4) ;
_rtc_noinit_end = ABSOLUTE(.);
} > rtc_data_location
/* This section located in RTC SLOW Memory area.
It holds data marked with RTC_SLOW_ATTR attribute.
See the file "esp_attr.h" for more information.
*/
.rtc.force_slow :
{
. = ALIGN(4);
_rtc_force_slow_start = ABSOLUTE(.);
*(.rtc.force_slow .rtc.force_slow.*)
. = ALIGN(4) ;
_rtc_force_slow_end = ABSOLUTE(.);
} > rtc_slow_seg
/* Get size of rtc slow data based on rtc_data_location alias */
_rtc_slow_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location))
? (_rtc_force_slow_end - _rtc_data_start)
: (_rtc_force_slow_end - _rtc_force_slow_start);
_rtc_fast_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location))
? (_rtc_force_fast_end - _rtc_fast_start)
: (_rtc_noinit_end - _rtc_fast_start);
ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)),
"RTC_SLOW segment data does not fit.")
ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)),
"RTC_FAST segment data does not fit.")
/* Send .iram0 code to iram */
.iram0.vectors :
{
_iram_start = ABSOLUTE(.);
/* Vectors go to IRAM */
_vector_table = ABSOLUTE(.);
/* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */
. = 0x0;
KEEP(*(.WindowVectors.text));
. = 0x180;
KEEP(*(.Level2InterruptVector.text));
. = 0x1c0;
KEEP(*(.Level3InterruptVector.text));
. = 0x200;
KEEP(*(.Level4InterruptVector.text));
. = 0x240;
KEEP(*(.Level5InterruptVector.text));
. = 0x280;
KEEP(*(.DebugExceptionVector.text));
. = 0x2c0;
KEEP(*(.NMIExceptionVector.text));
. = 0x300;
KEEP(*(.KernelExceptionVector.text));
. = 0x340;
KEEP(*(.UserExceptionVector.text));
. = 0x3C0;
KEEP(*(.DoubleExceptionVector.text));
. = 0x400;
_invalid_pc_placeholder = ABSOLUTE(.);
*(.*Vector.literal)
*(.UserEnter.literal);
*(.UserEnter.text);
. = ALIGN (16);
*(.entry.text)
*(.init.literal)
*(.init)
_init_end = ABSOLUTE(.);
} > iram0_0_seg
.iram0.text :
{
/* Code marked as runnning out of IRAM */
_iram_text_start = ABSOLUTE(.);
*(.iram1 .iram1.*)
/* Xtensa basic functionality written in assembler should be placed in IRAM */
*xtensa/*(.literal .text .literal.* .text.*)
/* parts of RIOT that should run in IRAM */
*core/*(.literal .text .literal.* .text.*)
*esp_common_periph/flash.*(.literal .text .literal.* .text.*)
*esp_common/thread_arch.*(.literal .text .literal.* .text.*)
*esp_freertos_common/*(.literal .text .literal.* .text.*)
/* parts of ESP-IDF that should run in IRAM */
/* find components/ -type f -name linker.lf -exec grep "(noflash)" {} \; -print */
/* find components/ -type f -name linker.lf -exec grep "(noflash_text)" {} \; -print */
*components/app_trace/app_trace.*(.literal .literal.* .text .text.*)
*components/app_trace/app_trace_util.*(.literal .literal.* .text .text.*)
*components/esp_event/default_event_loop.*(.literal.esp_event_isr_post .text.esp_event_isr_post)
*components/esp_event/esp_event.*(.literal.esp_event_isr_post_to .text.esp_event_isr_post_to)
*components/esp_hw_support/cpu_util.*(.literal .literal.* .text .text.*)
*components/esp_hw_support/*regi2c_ctrl.*(.literal .literal.* .text .text.*)
*components/esp_hw_support/*/rtc_clk.*(.literal .literal.* .text .text.*)
*components/esp_hw_support/*/rtc_init.*(.literal.rtc_vddsdio_set_config .text.rtc_vddsdio_set_config)
*components/esp_hw_support/*/rtc_pm.*(.literal .literal.* .text .text.*)
*components/esp_hw_support/*/rtc_sleep.*(.literal .literal.* .text .text.*)
*components/esp_hw_support/*/rtc_time.*(.literal .literal.* .text .text.*)
*components/esp_hw_support/*/rtc_wdt.*(.literal .literal.* .text .text.*)
*components/esp_ringbuf/*(.literal .literal.* .text .text.*)
*components/esp_rom/esp_rom_spiflash.*(.literal .literal.* .text .text.*)
*components/esp_system/esp_err.*(.literal .literal.* .text .text.*)
*components/esp_system/esp_system.*(.literal.esp_system_abort .text.esp_system_abort)
*components/esp_system/ubsan.*(.literal .literal.* .text .text.*)
*libgcc.a:_divsf3.*(.literal .literal.* .text .text.*)
*libgcc.a:lib2funcs.*(.literal .literal.* .text .text.*)
*libgcc.a:save-restore.*(.literal .literal.* .text .text.*)
*libgcov.a:(.literal .literal.* .text .text.*)
*components/hal/cpu_hal.*(.literal .literal.* .text .text.*)
*components/hal/i2c_hal_iram.*(.literal .literal.* .text .text.*)
*components/hal/ledc_hal_iram.*(.literal .literal.* .text .text.*)
*components/hal/soc_hal.*(.literal .literal.* .text .text.*)
*components/hal/spi_flash_encrypt_hal_iram.*(.literal .literal.* .text .text.*)
*components/hal/spi_flash_hal_gpspi.*(.literal .literal.* .text .text.*)
*components/hal/spi_flash_hal_iram.*(.literal .literal.* .text .text.*)
*components/hal/spi_hal_iram.*(.literal .literal.* .text .text.*)
*components/hal/spi_slave_hal_iram.*(.literal .literal.* .text .text.*)
*components/hal/systimer_hal.*(.literal .literal.* .text .text.*)
*components/hal/twai_hal.*(.literal .literal.* .text .text.*)
*components/hal/uart_hal.*(.literal .literal.* .text .text.*)
*components/hal/wdt_hal_iram.*(.literal .literal.* .text .text.*)
*components/heap/heap_tlsf.*(.literal .literal.* .text .text.*)
*components/heap/multi_heap.*(.literal .literal.* .text .text.*)
*esp-idf/esp_idf_support.*(.literal.esp_log_write .text.esp_log_write)
*libnet80211.a:(.wifi0iram .wifi0iram.*)
*libnet80211.a:(.wifirxiram .wifirxiram.*)
*libnet80211.a:(.wifislprxiram .wifislprxiram.*)
*components/newlib/abort.*(.literal .literal.* .text .text.*)
*components/newlib/assert.*(.literal .literal.* .text .text.*)
*components/newlib/heap.*(.literal .literal.* .text .text.*)
*components/newlib/stdatomic.*(.literal .literal.* .text .text.*)
*libpp.a:(.wifi0iram .wifi0iram.*)
*libpp.a:(.wifiorslpiram .wifiorslpiram.*)
*libpp.a:(.wifirxiram .wifirxiram.*)
*libpp.a:(.wifislprxiram .wifislprxiram.*)
*librtc.a:(.literal .literal.* .text .text.*)
*components/soc/lldesc.*(.literal .literal.* .text .text.*)
*components/spi_flash/memspi_host_driver.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_chip_boya.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_chip_gd.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_chip_generic.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_chip_issi.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_chip_mxic.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_chip_mxic_opi.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_chip_th.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_chip_winbond.*(.literal .literal.* .text .text.*)
*components/spi_flash/*/spi_flash_rom_patch.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_timing_tuning.*(.literal .literal.* .text .text.*)
*components/spi_flash/*/spi_timing_config.*(.literal .literal.* .text .text.*)
*libxt_hal.a:(.literal .literal.* .text .text.*)
*libxtensa.a:eri.*(.literal .literal.* .text .text.*)
*libxtensa.a:xtensa_intr_asm.*(.literal .literal.* .text .text.*)
/* Added to maintain compability, there are no iram0 data section to put
* sections:iram_coredump entry defined in espcoredump's linker.lf file */
_coredump_iram_start = 0;
_coredump_iram_end = 0;
/* align + add 16B for CPU dummy speculative instr. fetch */
. = ALIGN(_esp_memprot_align_size) + _esp_memprot_prefetch_pad_size;
/* iram_end_test section exists for use by memprot unit tests only */
*(.iram_end_test)
_iram_text_end = ABSOLUTE(.);
_iram_end = ABSOLUTE(.);
} > iram0_0_seg
.dram0_reserved_for_iram (NOLOAD):
{
. = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;
} > dram0_0_seg
.dram0.data :
{
_data_start = ABSOLUTE(.);
*(.gnu.linkonce.d.*)
*(.data1)
*(.sdata)
*(.sdata.*)
KEEP (*(SORT(.xfa.*)))
*(.gnu.linkonce.s.*)
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
*(.jcr)
_esp_system_init_fn_array_start = ABSOLUTE(.);
KEEP (*(SORT(.esp_system_init_fn) SORT(.esp_system_init_fn.*)))
_esp_system_init_fn_array_end = ABSOLUTE(.);
*(EXCLUDE_FILE(*libbt.a *libbtdm_app.a *libnimble.a) .data EXCLUDE_FILE(*libbt.a *libbtdm_app.a *libnimble.a) .data.*)
*(.dram1 .dram1.*)
_coredump_dram_start = ABSOLUTE(.);
*(.dram2.coredump .dram2.coredump.*)
_coredump_dram_end = ABSOLUTE(.);
*libapp_trace.a:app_trace.*(.rodata .rodata.*)
*libapp_trace.a:app_trace_util.*(.rodata .rodata.*)
_bt_data_start = ABSOLUTE(.);
*libbt.a:(.data .data.*)
. = ALIGN(4);
_bt_data_end = ABSOLUTE(.);
_btdm_data_start = ABSOLUTE(.);
*libbtdm_app.a:(.data .data.*)
. = ALIGN(4);
_btdm_data_end = ABSOLUTE(.);
/* find components/ -type f -name linker.lf -exec grep "(noflash)" {} \; -print */
*components/esp_hw_support/*regi2c_ctrl.*(.rodata .rodata.*)
*components/esp_hw_support/port/*/rtc_clk.*(.rodata .rodata.*)
*components/esp_rom/esp_rom_spiflash.*(.rodata .rodata.*)
*components/esp_system/esp_err.*(.rodata .rodata.*)
*components/esp_system/ubsan.*(.rodata .rodata.*)
*libgcc.a:_divsf3.*(.rodata .rodata.*)
*libgcc.a:save-restore.*(.rodata .rodata.*)
*libgcov.a:(.rodata .rodata.*)
*components/hal/cpu_hal.*(.rodata .rodata.*)
*components/hal/i2c_hal_iram.*(.rodata .rodata.*)
*components/hal/ledc_hal_iram.*(.rodata .rodata.*)
*components/hal/soc_hal.*(.rodata .rodata.*)
*components/hal/spi_flash_encrypt_hal_iram.*(.rodata .rodata.*)
*components/hal/spi_flash_hal_gpspi.*(.rodata .rodata.*)
*components/hal/spi_flash_hal_iram.*(.rodata .rodata.*)
*components/hal/spi_hal_iram.*(.rodata .rodata.*)
*components/hal/spi_slave_hal_iram.*(.rodata .rodata.*)
*components/hal/systimer_hal.*(.rodata .rodata.*)
*components/hal/twai_hal.*(.rodata .rodata.*)
*components/hal/uart_hal.*(.rodata .rodata.*)
*components/hal/wdt_hal_iram.*(.rodata .rodata.*)
*components/heap/heap_tlsf.*(.rodata .rodata.*)
*components/heap/multi_heap.*(.rodata .rodata.*)
*components/newlib/abort.*(.rodata .rodata.*)
*components/newlib/assert.*(.rodata .rodata.*)
*components/newlib/heap.*(.rodata .rodata.*)
*components/newlib/stdatomic.*(.rodata .rodata.*)
_nimble_data_start = ABSOLUTE(.);
*libnimble.a:(.data .data.*)
. = ALIGN(4);
_nimble_data_end = ABSOLUTE(.);
*components/soc/lldesc.*(.rodata .rodata.*)
*components/spi_flash/memspi_host_driver.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_chip_boya.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_chip_gd.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_chip_generic.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_chip_issi.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_chip_mxic.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_chip_mxic_opi.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_chip_th.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_chip_winbond.*(.rodata .rodata.*)
*components/spi_flash/*/spi_flash_rom_patch.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_timing_tuning.*(.rodata .rodata.*)
*components/spi_flash/*/spi_timing_config.*(.rodata .rodata.*)
_data_end = ABSOLUTE(.);
. = ALIGN(4);
} > dram0_0_seg
/*This section holds data that should not be initialized at power up.
The section located in Internal SRAM memory region. The macro _NOINIT
can be used as attribute to place data into this section.
See the esp_attr.h file for more information.
*/
.noinit (NOLOAD):
{
. = ALIGN(4);
_noinit_start = ABSOLUTE(.);
*(.noinit .noinit.*)
. = ALIGN(4) ;
_noinit_end = ABSOLUTE(.);
} > dram0_0_seg
/* external memory bss, from any global variable with EXT_RAM_ATTR attribute*/
.ext_ram.bss (NOLOAD) :
{
_ext_ram_bss_start = ABSOLUTE(.);
. = ALIGN(4);
_ext_ram_bss_end = ABSOLUTE(.);
} > extern_ram_seg
/* Shared RAM */
.dram0.bss (NOLOAD) :
{
. = ALIGN (8);
_bss_start = ABSOLUTE(.);
*(.ext_ram.bss*)
*(.bss .bss.*)
*(.ext_ram.bss .ext_ram.bss.*)
*(.dynbss .dynsbss .gnu.linkonce.b .gnu.linkonce.b.* .gnu.linkonce.sb .gnu.linkonce.sb.* .gnu.linkonce.sb2 .gnu.linkonce.sb2.* .sbss .sbss.* .sbss2 .sbss2.* .scommon .share.mem)
*(COMMON)
_bt_bss_start = ABSOLUTE(.);
*libbt.a:(.bss .bss.* COMMON)
. = ALIGN(4);
_bt_bss_end = ABSOLUTE(.);
_btdm_bss_start = ABSOLUTE(.);
*libbtdm_app.a:(.bss .bss.* COMMON)
. = ALIGN(4);
_btdm_bss_end = ABSOLUTE(.);
_nimble_bss_start = ABSOLUTE(.);
*libnimble.a:(.bss .bss.* COMMON)
. = ALIGN(4);
_nimble_bss_end = ABSOLUTE(.);
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.share.mem)
*(.gnu.linkonce.b.*)
. = ALIGN (8);
_bss_end = ABSOLUTE(.);
} > dram0_0_seg
.flash.appdesc : ALIGN(0x10)
{
_rodata_reserved_start = ABSOLUTE(.);
_rodata_start = ABSOLUTE(.);
*(.rodata_desc .rodata_desc.*) /* Should be the first. App version info. DO NOT PUT ANYTHING BEFORE IT! */
*(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */
/* Create an empty gap within this section. Thanks to this, the end of this
* section will match .flah.rodata's begin address. Thus, both sections
* will be merged when creating the final bin image. */
. = ALIGN(ALIGNOF(.flash.rodata));
} >default_rodata_seg
.flash.rodata : ALIGN(0x10)
{
_flash_rodata_start = ABSOLUTE(.);
*(.rodata .rodata.*)
*(.rodata_wlog_error .rodata_wlog_error.*)
*(.rodata_wlog_info .rodata_wlog_info.*)
*(.rodata_wlog_warning .rodata_wlog_warning.*)
KEEP (*(SORT(.roxfa.*)))
*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
*(.xt_except_table)
*(.gcc_except_table .gcc_except_table.*)
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
. = (. + 3) & ~ 3;
__eh_frame = ABSOLUTE(.);
KEEP(*(.eh_frame))
. = (. + 7) & ~ 3;
/* C++ constructor and destructor tables
Make a point of not including anything from crtbegin.o or crtend.o, as IDF doesn't use toolchain crt
*/
__init_array_start = ABSOLUTE(.);
KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .ctors SORT(.ctors.*)))
__init_array_end = ABSOLUTE(.);
KEEP (*crtbegin.*(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
/* Addresses of memory regions reserved via
SOC_RESERVE_MEMORY_REGION() */
soc_reserved_memory_region_start = ABSOLUTE(.);
KEEP (*(.reserved_memory_address))
soc_reserved_memory_region_end = ABSOLUTE(.);
_rodata_end = ABSOLUTE(.);
/* Literals are also RO data. */
_lit4_start = ABSOLUTE(.);
*(*.lit4)
*(.lit4.*)
*(.gnu.linkonce.lit4.*)
_lit4_end = ABSOLUTE(.);
. = ALIGN(4);
_thread_local_start = ABSOLUTE(.);
*(.tdata)
*(.tdata.*)
*(.tbss)
*(.tbss.*)
_thread_local_end = ABSOLUTE(.);
_rodata_reserved_end = ABSOLUTE(.);
. = ALIGN(4);
} >default_rodata_seg
_flash_rodata_align = ALIGNOF(.flash.rodata);
.flash.rodata_noload (NOLOAD) :
{
. = ALIGN (4);
*(.rodata_wlog_debug .rodata_wlog_debug.*)
*(.rodata_wlog_verbose .rodata_wlog_verbose.*)
} > default_rodata_seg
.flash.text :
{
_stext = .;
_instruction_reserved_start = ABSOLUTE(.);
_text_start = ABSOLUTE(.);
*(.literal .literal.* .text .text.*)
*(.wifi0iram .wifi0iram.*)
*(.wifiorslpiram .wifiorslpiram.*)
*(.wifirxiram .wifirxiram.*)
*(.wifislpiram .wifislpiram.*)
*(.wifislprxiram .wifislprxiram.*)
*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
*(.fini.literal)
*(.fini)
*(.gnu.version)
/** CPU will try to prefetch up to 16 bytes of
* of instructions. This means that any configuration (e.g. MMU, PMS) must allow
* safe access to up to 16 bytes after the last real instruction, add
* dummy bytes to ensure this
*/
. += _esp_flash_mmap_prefetch_pad_size;
_text_end = ABSOLUTE(.);
_instruction_reserved_end = ABSOLUTE(.);
_etext = .;
/* Similar to _iram_start, this symbol goes here so it is
resolved by addr2line in preference to the first symbol in
the flash.text segment.
*/
_flash_cache_start = ABSOLUTE(0);
} >default_code_seg
/* Marks the end of IRAM code segment */
.iram0.text_end (NOLOAD) :
{
. = ALIGN (4);
_iram_end = ABSOLUTE(.);
} > iram0_0_seg
/* Marks the end of data, bss and possibly rodata */
.dram0.heap_start (NOLOAD) :
{
. = ALIGN (8);
_heap_start = ABSOLUTE(.);
_sheap = ABSOLUTE(.);
} > dram0_0_seg
. = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);
_eheap = ABSOLUTE(.);
. = _heap_end;
#ifdef MODULE_PERIPH_FLASHPAGE
.flash_writable (NOLOAD) : ALIGN(65536)
{
_fp_mem_start = . ;
KEEP(*(SORT(.flash_writable.*)))
_fp_mem_end = . ;
. = ALIGN(4096);
_end_fw = . ;
} > drom0_1_seg
#endif
}
ASSERT(((_iram_text_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),
"IRAM0 segment data does not fit.")
ASSERT(((_heap_start - _data_start) <= LENGTH(dram0_0_seg)),
"DRAM segment data does not fit.")
. = ORIGIN(dram0_0_seg);
_cpu_ram_start = ABSOLUTE(.);
. = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);
_cpu_ram_end = ABSOLUTE(.);
/* ensure that RAM_START_ADDR and RAM_LEN as defined in RIOT's makefile
* match the parameters used in linker script */
ASSERT((ORIGIN(dram0_0_seg) == CPU_RAM_BASE),
"RAM_START_ADDR does not match DRAM start address")
ASSERT((LENGTH(dram0_0_seg) == CPU_RAM_SIZE),
"RAM_LEN does not match DRAM size")

655
cpu/esp32/ld/esp32s3/sections.ld.in
View File

@ -1,655 +0,0 @@
/* Automatically generated file; DO NOT EDIT */
/* Espressif IoT Development Framework Linker Script */
/* Generated from: esp-idf/components/esp_system/ld/esp32s3/sections.ld.in */
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Default entry point */
ENTRY(call_start_cpu0);
_diram_i_start = 0x40378000;
SECTIONS
{
/**
* RTC fast memory holds RTC wake stub code,
* including from any source file named rtc_wake_stub*.c
*/
.rtc.text :
{
. = ALIGN(4);
_rtc_text_start = ABSOLUTE(.);
*(.rtc.entry.text)
*(.rtc.literal .rtc.text .rtc.text.*)
*rtc_wake_stub*.*(.literal .text .literal.* .text.*)
_rtc_text_end = ABSOLUTE(.);
} > rtc_iram_seg
/**
* This section is required to skip rtc.text area because rtc_iram_seg and
* rtc_data_seg are reflect the same address space on different buses.
*/
.rtc.dummy :
{
_rtc_dummy_start = ABSOLUTE(.);
_rtc_fast_start = ABSOLUTE(.);
. = SIZEOF(.rtc.text);
_rtc_dummy_end = ABSOLUTE(.);
} > rtc_data_seg
/**
* This section located in RTC FAST Memory area.
* It holds data marked with RTC_FAST_ATTR attribute.
* See the file "esp_attr.h" for more information.
*/
.rtc.force_fast :
{
. = ALIGN(4);
_rtc_force_fast_start = ABSOLUTE(.);
_coredump_rtc_fast_start = ABSOLUTE(.);
*(.rtc.fast.coredump .rtc.fast.coredump.*)
_coredump_rtc_fast_end = ABSOLUTE(.);
*(.rtc.force_fast .rtc.force_fast.*)
. = ALIGN(4) ;
_rtc_force_fast_end = ABSOLUTE(.);
} > rtc_data_seg
/**
* RTC data section holds RTC wake stub
* data/rodata, including from any source file
* named rtc_wake_stub*.c and the data marked with
* RTC_DATA_ATTR, RTC_RODATA_ATTR attributes.
* The memory location of the data is dependent on
* CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM option.
*/
.rtc.data :
{
_rtc_data_start = ABSOLUTE(.);
_coredump_rtc_start = ABSOLUTE(.);
*(.rtc.coredump .rtc.coredump.*)
_coredump_rtc_end = ABSOLUTE(.);
*(.rtc.data .rtc.data.*)
*(.rtc.rodata .rtc.rodata.*)
*rtc_wake_stub*.*(.data .rodata .data.* .rodata.* .bss .bss.*)
_rtc_data_end = ABSOLUTE(.);
} > rtc_data_location
/* RTC bss, from any source file named rtc_wake_stub*.c */
.rtc.bss (NOLOAD) :
{
/* part that is initialized if not waking up from deep sleep */
_rtc_bss_start = ABSOLUTE(.);
*rtc_wake_stub*.*(.bss .bss.*)
*rtc_wake_stub*.*(COMMON)
_rtc_bss_end = ABSOLUTE(.);
/* part that saves some data for rtc periph module, this part is
only initialized at power on reset */
_rtc_bss_rtc_start = ABSOLUTE(.);
*(.rtc.bss .rtc.bss.*)
_rtc_bss_rtc_end = ABSOLUTE(.);
} > rtc_data_location
/**
* This section holds data that should not be initialized at power up
* and will be retained during deep sleep.
* User data marked with RTC_NOINIT_ATTR will be placed
* into this section. See the file "esp_attr.h" for more information.
* The memory location of the data is dependent on CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM option.
*/
.rtc_noinit (NOLOAD):
{
. = ALIGN(4);
_rtc_noinit_start = ABSOLUTE(.);
*(.rtc_noinit .rtc_noinit.*)
. = ALIGN(4) ;
_rtc_noinit_end = ABSOLUTE(.);
} > rtc_data_location
/**
* This section located in RTC SLOW Memory area.
* It holds data marked with RTC_SLOW_ATTR attribute.
* See the file "esp_attr.h" for more information.
*/
.rtc.force_slow :
{
. = ALIGN(4);
_rtc_force_slow_start = ABSOLUTE(.);
*(.rtc.force_slow .rtc.force_slow.*)
. = ALIGN(4) ;
_rtc_force_slow_end = ABSOLUTE(.);
} > rtc_slow_seg
/* Get size of rtc slow data based on rtc_data_location alias */
_rtc_slow_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location))
? (_rtc_force_slow_end - _rtc_data_start)
: (_rtc_force_slow_end - _rtc_force_slow_start);
_rtc_fast_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location))
? (_rtc_force_fast_end - _rtc_fast_start)
: (_rtc_noinit_end - _rtc_fast_start);
ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)),
"RTC_SLOW segment data does not fit.")
ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)),
"RTC_FAST segment data does not fit.")
/* Send .iram0 code to iram */
.iram0.vectors :
{
_iram_start = ABSOLUTE(.);
/* Vectors go to IRAM */
_vector_table = ABSOLUTE(.);
. = 0x0;
KEEP(*(.WindowVectors.text));
. = 0x180;
KEEP(*(.Level2InterruptVector.text));
. = 0x1c0;
KEEP(*(.Level3InterruptVector.text));
. = 0x200;
KEEP(*(.Level4InterruptVector.text));
. = 0x240;
KEEP(*(.Level5InterruptVector.text));
. = 0x280;
KEEP(*(.DebugExceptionVector.text));
. = 0x2c0;
KEEP(*(.NMIExceptionVector.text));
. = 0x300;
KEEP(*(.KernelExceptionVector.text));
. = 0x340;
KEEP(*(.UserExceptionVector.text));
. = 0x3C0;
KEEP(*(.DoubleExceptionVector.text));
. = 0x400;
_invalid_pc_placeholder = ABSOLUTE(.);
*(.*Vector.literal)
*(.UserEnter.literal);
*(.UserEnter.text);
. = ALIGN (16);
*(.entry.text)
*(.init.literal)
*(.init)
_init_end = ABSOLUTE(.);
} > iram0_0_seg
.iram0.text :
{
/* Code marked as running out of IRAM */
_iram_text_start = ABSOLUTE(.);
*(.iram1 .iram1.*)
/* Xtensa basic functionality written in assembler should be placed in IRAM */
*xtensa/*(.literal .text .literal.* .text.*)
/* parts of RIOT that should run in IRAM */
*core/*(.literal .text .literal.* .text.*)
*esp_common_periph/flash.*(.literal .text .literal.* .text.*)
*esp_common/thread_arch.*(.literal .text .literal.* .text.*)
*esp_freertos_common/*(.literal .text .literal.* .text.*)
/* parts of ESP-IDF that should run in IRAM */
/* find components/ -type f -name linker.lf -exec grep "(noflash)" {} \; -print */
/* find components/ -type f -name linker.lf -exec grep "(noflash_text)" {} \; -print */
*components/app_trace/app_trace.*(.literal .literal.* .text .text.*)
*components/app_trace/app_trace_util.*(.literal .literal.* .text .text.*)
*components/esp_event/default_event_loop.*(.literal.esp_event_isr_post .text.esp_event_isr_post)
*components/esp_event/esp_event.*(.literal.esp_event_isr_post_to .text.esp_event_isr_post_to)
*components/esp_hw_support/cpu_util.*(.literal .literal.* .text .text.*)
*components/esp_hw_support/*/rtc_clk.*(.literal .literal.* .text .text.*)
*components/esp_hw_support/*/rtc_init.*(.literal.rtc_vddsdio_set_config .text.rtc_vddsdio_set_config)
*components/esp_hw_support/*/rtc_pm.*(.literal .literal.* .text .text.*)
*components/esp_hw_support/*/rtc_sleep.*(.literal .literal.* .text .text.*)
*components/esp_hw_support/*/rtc_time.*(.literal .literal.* .text .text.*)
*components/esp_hw_support/*/rtc_wdt.*(.literal .literal.* .text .text.*)
*components/esp_hw_support/*/spiram_psram.*(.literal .literal.* .text .text.*)
*components/esp_hw_support/*/opiram_psram.*(.literal .literal.* .text .text.*)
*components/esp_ringbuf/*(.literal .literal.* .text .text.*)
*components/esp_rom/esp_rom_spiflash.*(.literal .literal.* .text .text.*)
*components/esp_system/esp_err.*(.literal .literal.* .text .text.*)
*components/esp_system/esp_system.*(.literal.esp_system_abort .text.esp_system_abort)
*components/esp_system/ubsan.*(.literal .literal.* .text .text.*)
*libgcc.a:_divsf3.*(.literal .literal.* .text .text.*)
*libgcc.a:lib2funcs.*(.literal .literal.* .text .text.*)
*libgcc.a:save-restore.*(.literal .literal.* .text .text.*)
*libgcov.a:(.literal .literal.* .text .text.*)
*components/hal/cpu_hal.*(.literal .literal.* .text .text.*)
*components/hal/i2c_hal_iram.*(.literal .literal.* .text .text.*)
*components/hal/ledc_hal_iram.*(.literal .literal.* .text .text.*)
*components/hal/soc_hal.*(.literal .literal.* .text .text.*)
*components/hal/spi_flash_encrypt_hal_iram.*(.literal .literal.* .text .text.*)
*components/hal/spi_flash_hal_gpspi.*(.literal .literal.* .text .text.*)
*components/hal/spi_flash_hal_iram.*(.literal .literal.* .text .text.*)
*components/hal/spi_hal_iram.*(.literal .literal.* .text .text.*)
*components/hal/spi_slave_hal_iram.*(.literal .literal.* .text .text.*)
*components/hal/systimer_hal.*(.literal .literal.* .text .text.*)
*components/hal/twai_hal.*(.literal .literal.* .text .text.*)
*components/hal/uart_hal.*(.literal .literal.* .text .text.*)
*components/hal/wdt_hal_iram.*(.literal .literal.* .text .text.*)
*components/heap/heap_tlsf.*(.literal .literal.* .text .text.*)
*components/heap/multi_heap.*(.literal .literal.* .text .text.*)
*esp-idf/esp_idf_support.*(.literal.esp_log_write .text.esp_log_write)
*libnet80211.a:(.wifi0iram .wifi0iram.*)
*libnet80211.a:(.wifirxiram .wifirxiram.*)
*libnet80211.a:(.wifislprxiram .wifislprxiram.*)
*components/newlib/abort.*(.literal .literal.* .text .text.*)
*components/newlib/assert.*(.literal .literal.* .text .text.*)
*components/newlib/heap.*(.literal .literal.* .text .text.*)
*components/newlib/stdatomic.*(.literal .literal.* .text .text.*)
*libpp.a:(.wifi0iram .wifi0iram.*)
*libpp.a:(.wifiorslpiram .wifiorslpiram.*)
*libpp.a:(.wifirxiram .wifirxiram.*)
*libpp.a:(.wifislprxiram .wifislprxiram.*)
*librtc.a:(.literal .literal.* .text .text.*)
*components/soc/lldesc.*(.literal .literal.* .text .text.*)
*components/spi_flash/memspi_host_driver.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_chip_boya.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_chip_gd.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_chip_generic.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_chip_issi.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_chip_mxic.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_chip_mxic_opi.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_chip_th.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_chip_winbond.*(.literal .literal.* .text .text.*)
*components/spi_flash/*/spi_flash_rom_patch.*(.literal .literal.* .text .text.*)
*components/spi_flash/spi_flash_timing_tuning.*(.literal .literal.* .text .text.*)
*components/spi_flash/*/spi_timing_config.*(.literal .literal.* .text .text.*)
*libxt_hal.a:(.literal .literal.* .text .text.*)
*libxtensa.a:eri.*(.literal .literal.* .text .text.*)
*libxtensa.a:xtensa_intr_asm.*(.literal .literal.* .text .text.*)
} > iram0_0_seg
/**
* This section is required to skip .iram0.text area because iram0_0_seg and
* dram0_0_seg reflect the same address space on different buses.
*/
.dram0.dummy (NOLOAD):
{
. = ORIGIN(dram0_0_seg) + MAX(_iram_end - _diram_i_start, 0);
} > dram0_0_seg
.dram0.data :
{
_data_start = ABSOLUTE(.);
*(.gnu.linkonce.d.*)
*(.data1)
*(.sdata)
*(.sdata.*)
KEEP (*(SORT(.xfa.*)))
*(.gnu.linkonce.s.*)
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
*(.jcr)
_esp_system_init_fn_array_start = ABSOLUTE(.);
KEEP (*(SORT(.esp_system_init_fn) SORT(.esp_system_init_fn.*)))
_esp_system_init_fn_array_end = ABSOLUTE(.);
*(EXCLUDE_FILE(*components/bt/* *libbtdm_app.a) .data EXCLUDE_FILE(*components/bt/* *libbtdm_app.a) .data.*)
*(.dram1 .dram1.*)
_coredump_dram_start = ABSOLUTE(.);
*(.dram1.coredump .dram1.coredump.*)
_coredump_dram_end = ABSOLUTE(.);
*libapp_trace.a:app_trace.*(.rodata .rodata.*)
*libapp_trace.a:app_trace_util.*(.rodata .rodata.*)
_bt_data_start = ABSOLUTE(.);
*components/bt/*(.data .data.*)
. = ALIGN(4);
_bt_data_end = ABSOLUTE(.);
_btdm_data_start = ABSOLUTE(.);
*libbtdm_app.a:(.data .data.*)
. = ALIGN(4);
_btdm_data_end = ABSOLUTE(.);
/* find components/ -type f -name linker.lf -exec grep "(noflash)" {} \; -print */
*components/esp_hw_support/port/*/rtc_clk.*(.rodata .rodata.*)
*components/esp_rom/esp_rom_spiflash.*(.rodata .rodata.*)
*components/esp_system/esp_err.*(.rodata .rodata.*)
*components/esp_system/ubsan.*(.rodata .rodata.*)
*libgcc.a:_divsf3.*(.rodata .rodata.*)
*libgcc.a:save-restore.*(.rodata .rodata.*)
*libgcov.a:(.rodata .rodata.*)
*components/hal/cpu_hal.*(.rodata .rodata.*)
*components/hal/i2c_hal_iram.*(.rodata .rodata.*)
*components/hal/ledc_hal_iram.*(.rodata .rodata.*)
*components/hal/soc_hal.*(.rodata .rodata.*)
*components/hal/spi_flash_encrypt_hal_iram.*(.rodata .rodata.*)
*components/hal/spi_flash_hal_gpspi.*(.rodata .rodata.*)
*components/hal/spi_flash_hal_iram.*(.rodata .rodata.*)
*components/hal/spi_hal_iram.*(.rodata .rodata.*)
*components/hal/spi_slave_hal_iram.*(.rodata .rodata.*)
*components/hal/systimer_hal.*(.rodata .rodata.*)
*components/hal/twai_hal.*(.rodata .rodata.*)
*components/hal/uart_hal.*(.rodata .rodata.*)
*components/hal/wdt_hal_iram.*(.rodata .rodata.*)
*components/heap/heap_tlsf.*(.rodata .rodata.*)
*components/heap/multi_heap.*(.rodata .rodata.*)
*components/newlib/abort.*(.rodata .rodata.*)
*components/newlib/assert.*(.rodata .rodata.*)
*components/newlib/heap.*(.rodata .rodata.*)
*components/newlib/stdatomic.*(.rodata .rodata.*)
_nimble_data_start = ABSOLUTE(.);
*libnimble.a:(.data .data.*)
. = ALIGN(4);
_nimble_data_end = ABSOLUTE(.);
*libphy.a:(.rodata .rodata.*)
*components/soc/lldesc.*(.rodata .rodata.*)
*components/spi_flash/memspi_host_driver.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_chip_boya.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_chip_gd.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_chip_generic.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_chip_issi.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_chip_mxic.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_chip_mxic_opi.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_chip_th.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_chip_winbond.*(.rodata .rodata.*)
*components/spi_flash/*/spi_flash_rom_patch.*(.rodata .rodata.*)
*components/spi_flash/spi_flash_timing_tuning.*(.rodata .rodata.*)
*components/spi_flash/*/spi_timing_config.*(.rodata .rodata.*)
_data_end = ABSOLUTE(.);
. = ALIGN(4);
} > dram0_0_seg
/**
* This section holds data that should not be initialized at power up.
* The section located in Internal SRAM memory region. The macro _NOINIT
* can be used as attribute to place data into this section.
* See the "esp_attr.h" file for more information.
*/
.noinit (NOLOAD):
{
. = ALIGN(4);
_noinit_start = ABSOLUTE(.);
*(.noinit .noinit.*)
. = ALIGN(4) ;
_noinit_end = ABSOLUTE(.);
} > dram0_0_seg
/* Shared RAM */
.dram0.bss (NOLOAD) :
{
. = ALIGN (8);
_bss_start = ABSOLUTE(.);
*(.ext_ram.bss*)
*(.bss .bss.*)
*(.ext_ram.bss .ext_ram.bss.*)
*(.dynbss .dynsbss .gnu.linkonce.b .gnu.linkonce.b.* .gnu.linkonce.sb .gnu.linkonce.sb.* .gnu.linkonce.sb2 .gnu.linkonce.sb2.* .sbss .sbss.* .sbss2 .sbss2.* .scommon .share.mem)
*(COMMON)
_bt_bss_start = ABSOLUTE(.);
*components/bt/*(.bss .bss.* COMMON)
. = ALIGN(4);
_bt_bss_end = ABSOLUTE(.);
_btdm_bss_start = ABSOLUTE(.);
*libbtdm_app.a:(.bss .bss.* COMMON)
. = ALIGN(4);
_btdm_bss_end = ABSOLUTE(.);
_nimble_bss_start = ABSOLUTE(.);
*libnimble.a:(.bss .bss.* COMMON)
. = ALIGN(4);
_nimble_bss_end = ABSOLUTE(.);
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.share.mem)
*(.gnu.linkonce.b.*)
. = ALIGN (8);
_bss_end = ABSOLUTE(.);
} > dram0_0_seg
ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.")
.flash.text :
{
_stext = .;
_instruction_reserved_start = ABSOLUTE(.);
_text_start = ABSOLUTE(.);
*(.literal .literal.* .text .text.*)
*(.wifi0iram .wifi0iram.*)
*(.wifiorslpiram .wifiorslpiram.*)
*(.wifirxiram .wifirxiram.*)
*(.wifislpiram .wifislpiram.*)
*(.wifislprxiram .wifislprxiram.*)
*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
*(.fini.literal)
*(.fini)
*(.gnu.version)
/** CPU will try to prefetch up to 16 bytes of
* of instructions. This means that any configuration (e.g. MMU, PMS) must allow
* safe access to up to 16 bytes after the last real instruction, add
* dummy bytes to ensure this
*/
. += _esp_flash_mmap_prefetch_pad_size;
_text_end = ABSOLUTE(.);
_instruction_reserved_end = ABSOLUTE(.);
_etext = .;
/**
* Similar to _iram_start, this symbol goes here so it is
* resolved by addr2line in preference to the first symbol in
* the flash.text segment.
*/
_flash_cache_start = ABSOLUTE(0);
} > default_code_seg
/**
* This dummy section represents the .flash.text section but in default_rodata_seg.
* Thus, it must have its alignement and (at least) its size.
*/
.flash_rodata_dummy (NOLOAD):
{
_flash_rodata_dummy_start = .;
/* Start at the same alignement constraint than .flash.text */
. = ALIGN(ALIGNOF(.flash.text));
/* Create an empty gap as big as .flash.text section */
. = . + SIZEOF(.flash.text);
/* Prepare the alignement of the section above. Few bytes (0x20) must be
* added for the mapping header. */
. = ALIGN(0x10000) + 0x20;
_rodata_reserved_start = .;
} > default_rodata_seg
.flash.appdesc : ALIGN(0x10)
{
_rodata_start = ABSOLUTE(.);
*(.rodata_desc .rodata_desc.*) /* Should be the first. App version info. DO NOT PUT ANYTHING BEFORE IT! */
*(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */
/* Create an empty gap within this section. Thanks to this, the end of this
* section will match .flah.rodata's begin address. Thus, both sections
* will be merged when creating the final bin image. */
. = ALIGN(ALIGNOF(.flash.rodata));
} >default_rodata_seg
.flash.rodata : ALIGN(0x10)
{
_flash_rodata_start = ABSOLUTE(.);
*(.rodata .rodata.*)
*(.rodata_wlog_error .rodata_wlog_error.*)
*(.rodata_wlog_info .rodata_wlog_info.*)
*(.rodata_wlog_warning .rodata_wlog_warning.*)
KEEP (*(SORT(.roxfa.*)))
*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
*(.xt_except_table)
*(.gcc_except_table .gcc_except_table.*)
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
. = (. + 3) & ~ 3;
__eh_frame = ABSOLUTE(.);
KEEP(*(.eh_frame))
. = (. + 7) & ~ 3;
/* C++ constructor and destructor tables */
/* Don't include anything from crtbegin.o or crtend.o, as IDF doesn't use toolchain crt */
__init_array_start = ABSOLUTE(.);
KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .ctors SORT(.ctors.*)))
__init_array_end = ABSOLUTE(.);
KEEP (*crtbegin.*(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
/* Addresses of memory regions reserved via SOC_RESERVE_MEMORY_REGION() */
soc_reserved_memory_region_start = ABSOLUTE(.);
KEEP (*(.reserved_memory_address))
soc_reserved_memory_region_end = ABSOLUTE(.);
_rodata_end = ABSOLUTE(.);
/* Literals are also RO data. */
_lit4_start = ABSOLUTE(.);
*(*.lit4)
*(.lit4.*)
*(.gnu.linkonce.lit4.*)
_lit4_end = ABSOLUTE(.);
. = ALIGN(4);
_thread_local_start = ABSOLUTE(.);
*(.tdata)
*(.tdata.*)
*(.tbss)
*(.tbss.*)
_thread_local_end = ABSOLUTE(.);
_rodata_reserved_end = ABSOLUTE(.);
. = ALIGN(4);
} > default_rodata_seg
_flash_rodata_align = ALIGNOF(.flash.rodata);
.flash.rodata_noload (NOLOAD) :
{
. = ALIGN (4);
*(.rodata_wlog_debug .rodata_wlog_debug.*)
*(.rodata_wlog_verbose .rodata_wlog_verbose.*)
} > default_rodata_seg
/* Marks the end of IRAM code segment */
.iram0.text_end (NOLOAD) :
{
/* ESP32-S3 memprot requires 16B padding for possible CPU prefetch and 256B alignment for PMS split lines */
. += _esp_memprot_prefetch_pad_size;
. = ALIGN(_esp_memprot_align_size);
/* iram_end_test section exists for use by memprot unit tests only */
*(.iram_end_test)
_iram_text_end = ABSOLUTE(.);
} > iram0_0_seg
.iram0.data :
{
. = ALIGN(4);
_iram_data_start = ABSOLUTE(.);
*(.iram.data .iram.data.*)
_coredump_iram_start = ABSOLUTE(.);
*(.iram.data.coredump .iram.data.coredump.*)
_coredump_iram_end = ABSOLUTE(.);
_iram_data_end = ABSOLUTE(.);
} > iram0_0_seg
.iram0.bss (NOLOAD) :
{
. = ALIGN(4);
_iram_bss_start = ABSOLUTE(.);
*(.iram.bss .iram.bss.*)
_iram_bss_end = ABSOLUTE(.);
. = ALIGN(4);
_iram_end = ABSOLUTE(.);
} > iram0_0_seg
/* Marks the end of data, bss and possibly rodata */
.dram0.heap_start (NOLOAD) :
{
. = ALIGN (8);
_heap_start = ABSOLUTE(.);
_sheap = ABSOLUTE(.);
} > dram0_0_seg
. = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);
_eheap = ABSOLUTE(.);
. = _heap_end;
#ifdef MODULE_PERIPH_FLASHPAGE
.flash_writable (NOLOAD) : ALIGN(65536)
{
_fp_mem_start = . ;
KEEP(*(SORT(.flash_writable.*)))
_fp_mem_end = . ;
. = ALIGN(4096);
_end_fw = . ;
} > drom0_1_seg
#endif
}
ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),
"IRAM0 segment data does not fit.")
ASSERT(((_heap_start - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),
"DRAM segment data does not fit.")
. = ORIGIN(dram0_0_seg);
_cpu_ram_start = ABSOLUTE(.);
. = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);
_cpu_ram_end = ABSOLUTE(.);
/* ensure that RAM_START_ADDR and RAM_LEN as defined in RIOT's makefile
* match the parameters used in linker script */
ASSERT((ORIGIN(dram0_0_seg) == CPU_RAM_BASE),
"RAM_START_ADDR does not match DRAM start address")
ASSERT((LENGTH(dram0_0_seg) == CPU_RAM_SIZE),
"RAM_LEN does not match DRAM size")

24
cpu/esp32/ld/ld.common
View File

@ -1,24 +0,0 @@
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
/* CPU instruction prefetch padding size for flash mmap scenario */
_esp_flash_mmap_prefetch_pad_size = 16;
/* CPU instruction prefetch padding size for memory protection scenario */
#ifdef CONFIG_ESP_SYSTEM_MEMPROT_CPU_PREFETCH_PAD_SIZE
_esp_memprot_prefetch_pad_size = CONFIG_ESP_SYSTEM_MEMPROT_CPU_PREFETCH_PAD_SIZE;
#else
_esp_memprot_prefetch_pad_size = 0;
#endif
/* Memory alignment size for PMS */
#ifdef CONFIG_ESP_SYSTEM_MEMPROT_MEM_ALIGN_SIZE
_esp_memprot_align_size = CONFIG_ESP_SYSTEM_MEMPROT_MEM_ALIGN_SIZE;
#else
_esp_memprot_align_size = 0;
#endif

370
cpu/esp32/periph/adc.c
View File

@ -27,6 +27,7 @@
*/
#include <assert.h>
#include <errno.h>
#include "board.h"
#include "periph/adc.h"
@ -36,92 +37,76 @@
#include "esp_common.h"
#include "gpio_arch.h"
#include "driver/adc.h"
#include "esp_adc/adc_oneshot.h"
#include "esp_private/adc_share_hw_ctrl.h"
#include "hal/adc_hal_common.h"
#define ENABLE_DEBUG 0
#include "debug.h"
/* forward declarations of internal functions */
static bool _adc_conf_check(void);
static void _adc1_ctrl_init(void);
static void _adc2_ctrl_init(void);
/* external variable declarations */
extern const gpio_t _gpio_rtcio_map[];
extern const int _adc_vrange_min_max[];
/*
* Structure for mapping RIOT's ADC resolutions to ESP-IDF resolutions
* of the according ESP32x SoC.
*/
typedef struct {
adc_bits_width_t res; /* used ESP-IDF resolution */
unsigned shift; /* bit shift number for results */
adc_bitwidth_t hw_res; /* used ESP-IDF resolution */
unsigned shift; /* bit shift number for results */
} _adc_esp_res_map_t;
#define ADC_BITWIDTH_MAX ((adc_bitwidth_t)255)
/*
* Table for resolution mapping
* With the exception of the ESP32, all ESP32x SoCs only support one resolution.
* Therefore, we only use this one resolution and shift the results accordingly.
*/
_adc_esp_res_map_t _adc_esp_res_map[] = {
#if defined(CPU_FAM_ESP32)
{ .res = ADC_WIDTH_BIT_9, .shift = 3 }, /* ADC_RES_6BIT */
{ .res = ADC_WIDTH_BIT_9, .shift = 1 }, /* ADC_RES_8BIT */
{ .res = ADC_WIDTH_BIT_10, .shift = 0 }, /* ADC_RES_10BIT */
{ .res = ADC_WIDTH_BIT_12, .shift = 0 }, /* ADC_RES_12BIT */
{ .res = ADC_WIDTH_MAX }, /* ADC_RES_14BIT */
{ .res = ADC_WIDTH_MAX }, /* ADC_RES_16BIT */
#elif SOC_ADC_MAX_BITWIDTH == 12
{ .res = ADC_WIDTH_BIT_12, .shift = 6 }, /* ADC_RES_6BIT */
{ .res = ADC_WIDTH_BIT_12, .shift = 4 }, /* ADC_RES_8BIT */
{ .res = ADC_WIDTH_BIT_12, .shift = 2 }, /* ADC_RES_10BIT */
{ .res = ADC_WIDTH_BIT_12, .shift = 0 }, /* ADC_RES_12BIT */
{ .res = ADC_WIDTH_MAX }, /* ADC_RES_14BIT */
{ .res = ADC_WIDTH_MAX }, /* ADC_RES_16BIT */
#elif SOC_ADC_MAX_BITWIDTH == 13
{ .res = ADC_WIDTH_BIT_13, .shift = 7 }, /* ADC_RES_6BIT */
{ .res = ADC_WIDTH_BIT_13, .shift = 5 }, /* ADC_RES_8BIT */
{ .res = ADC_WIDTH_BIT_13, .shift = 3 }, /* ADC_RES_10BIT */
{ .res = ADC_WIDTH_BIT_13, .shift = 1 }, /* ADC_RES_12BIT */
{ .res = ADC_WIDTH_MAX }, /* ADC_RES_14BIT */
{ .res = ADC_WIDTH_MAX }, /* ADC_RES_16BIT */
static const _adc_esp_res_map_t _adc_esp_res_map[] = {
#if SOC_ADC_RTC_MAX_BITWIDTH == 12
{ .hw_res = ADC_BITWIDTH_12, .shift = 6 }, /* ADC_RES_6BIT */
{ .hw_res = ADC_BITWIDTH_12, .shift = 4 }, /* ADC_RES_8BIT */
{ .hw_res = ADC_BITWIDTH_12, .shift = 2 }, /* ADC_RES_10BIT */
{ .hw_res = ADC_BITWIDTH_12, .shift = 0 }, /* ADC_RES_12BIT */
{ .hw_res = ADC_BITWIDTH_MAX }, /* ADC_RES_14BIT */
{ .hw_res = ADC_BITWIDTH_MAX }, /* ADC_RES_16BIT */
#elif SOC_ADC_RTC_MAX_BITWIDTH == 13
{ .hw_res = ADC_BITWIDTH_13, .shift = 7 }, /* ADC_RES_6BIT */
{ .hw_res = ADC_BITWIDTH_13, .shift = 5 }, /* ADC_RES_8BIT */
{ .hw_res = ADC_BITWIDTH_13, .shift = 3 }, /* ADC_RES_10BIT */
{ .hw_res = ADC_BITWIDTH_13, .shift = 1 }, /* ADC_RES_12BIT */
{ .hw_res = ADC_BITWIDTH_MAX }, /* ADC_RES_14BIT */
{ .hw_res = ADC_BITWIDTH_MAX }, /* ADC_RES_16BIT */
#endif
};
static bool _adc_module_initialized = false;
static adc_oneshot_unit_handle_t _adc_handle[SOC_ADC_PERIPH_NUM] = { };
static inline void _adc1_ctrl_init(void)
{
/* nothing to do for the moment */
}
static adc_oneshot_chan_cfg_t _adc_channel_cfg[ADC_NUMOF] = { };
static adc_cali_handle_t _adc_channel_cali[ADC_NUMOF] = { };
static const _adc_esp_res_map_t *_adc_channel_res[ADC_NUMOF] = { };
static inline void _adc2_ctrl_init(void)
{
/* nothing to do for the moment */
}
static bool _adc_driver_initialized = false;
/* forward declarations of internal functions */
static void _adc_driver_init(void);
static void _adc_channel_config(adc_t line, adc_bitwidth_t width, adc_atten_t att);
static void _adc_ctrl_init(adc_unit_t unit);
int adc_init(adc_t line)
{
DEBUG("[adc] line=%u\n", line);
DEBUG("[adc] %s: line=%u\n", __func__, line);
if (line >= ADC_NUMOF) {
return -1;
}
assert(line < ADC_NUMOF);
if (!_adc_module_initialized) {
/* do some configuration checks */
if (!_adc_conf_check()) {
return -1;
}
_adc_module_initialized = true;
}
/* initialize the ADC driver if needed including configuration sanity checks */
_adc_driver_init();
/* get the RTCIO pin number for the given GPIO defined as ADC channel */
uint8_t rtcio = _gpio_rtcio_map[adc_channels[line]];
/* check whether the GPIO is avalid ADC channel pin */
if (rtcio == RTCIO_NA) {
return -1;
}
/* check whether the pin is not used for other purposes */
if (gpio_get_pin_usage(_adc_hw[rtcio].gpio) != _GPIO) {
LOG_TAG_ERROR("adc", "GPIO%d is used for %s and cannot be used as "
@ -130,27 +115,8 @@ int adc_init(adc_t line)
return -1;
}
if (_adc_hw[rtcio].adc_ctrl == ADC_UNIT_1) {
/* ensure compatibility of given adc_channel_t with adc1_channel_t */
assert(_adc_hw[rtcio].adc_channel < (adc_channel_t)ADC1_CHANNEL_MAX);
/* initialize the ADC1 unit if needed */
_adc1_ctrl_init();
/* set the attenuation and configure its associated GPIO pin mux */
adc1_config_channel_atten((adc1_channel_t)_adc_hw[rtcio].adc_channel,
ADC_ATTEN_DB_11);
}
else if (_adc_hw[rtcio].adc_ctrl == ADC_UNIT_2) {
/* ensure compatibility of given adc_channel_t with adc2_channel_t */
assert(_adc_hw[rtcio].adc_channel < (adc_channel_t)ADC2_CHANNEL_MAX);
/* initialize the ADC2 unit if needed */
_adc2_ctrl_init();
/* set the attenuation and configure its associated GPIO pin mux */
adc2_config_channel_atten((adc2_channel_t)_adc_hw[rtcio].adc_channel,
ADC_ATTEN_DB_11);
}
else {
return -1;
}
/* initialize the corresponding ADC unit if needed */
_adc_ctrl_init(_adc_hw[rtcio].adc_ctrl);
/* set pin usage type */
gpio_set_pin_usage(_adc_hw[rtcio].gpio, _ADC);
@ -160,31 +126,29 @@ int adc_init(adc_t line)
int32_t adc_sample(adc_t line, adc_res_t res)
{
DEBUG("[adc] line=%u res=%u\n", line, res);
DEBUG("[adc] %s: line=%u res=%u\n", __func__, line, res);
if (_adc_esp_res_map[res].res == ADC_WIDTH_MAX) {
assert(_adc_driver_initialized);
assert(line < ADC_NUMOF);
if (_adc_esp_res_map[res].hw_res == ADC_BITWIDTH_MAX) {
return -1;
}
uint8_t rtcio = _gpio_rtcio_map[adc_channels[line]];
int raw;
assert(rtcio != RTCIO_NA);
if (_adc_hw[rtcio].adc_ctrl == ADC_UNIT_1) {
adc1_config_width(_adc_esp_res_map[res].res);
/* ensure compatibility of given adc_channel_t with adc1_channel_t */
assert(_adc_hw[rtcio].adc_channel < (adc_channel_t)ADC1_CHANNEL_MAX);
raw = adc1_get_raw((adc1_channel_t)_adc_hw[rtcio].adc_channel);
if (raw < 0) {
return -1;
}
if (_adc_channel_res[line] != &_adc_esp_res_map[res]) {
/* reconfigure the channel if the resolution is changed */
_adc_channel_res[line] = &_adc_esp_res_map[res];
_adc_channel_config(line, _adc_esp_res_map[res].hw_res,
_adc_channel_cfg[line].atten);
}
else if (_adc_hw[rtcio].adc_ctrl == ADC_UNIT_2) {
/* ensure compatibility of given adc_channel_t with adc2_channel_t */
assert(_adc_hw[rtcio].adc_channel < (adc_channel_t)ADC2_CHANNEL_MAX);
if (adc2_get_raw((adc2_channel_t)_adc_hw[rtcio].adc_channel,
_adc_esp_res_map[res].res, &raw) < 0) {
return -1;
}
int raw = 0;
if (adc_oneshot_read(_adc_handle[_adc_hw[rtcio].adc_ctrl],
_adc_hw[rtcio].adc_channel, &raw) != ESP_OK) {
return -1;
}
return raw >> _adc_esp_res_map[res].shift;
@ -192,73 +156,177 @@ int32_t adc_sample(adc_t line, adc_res_t res)
int adc_set_attenuation(adc_t line, adc_atten_t atten)
{
DEBUG("[adc] line=%u atten=%u\n", line, atten);
DEBUG("[adc] %s: line=%u atten=%u\n", __func__, line, atten);
assert(_adc_driver_initialized);
assert(line < ADC_NUMOF);
assert(atten < SOC_ADC_ATTEN_NUM);
_adc_channel_config(line, _adc_channel_cfg[line].bitwidth, atten);
return 0;
}
int adc_raw_to_voltage(adc_t line, int raw, int *voltage)
{
DEBUG("[adc] %s: line=%u\n", __func__, line);
assert(line < ADC_NUMOF);
assert(voltage);
assert(_adc_channel_res[line]);
/* scale the raw value to the resolution used internally */
raw = raw << _adc_channel_res[line]->shift;
if (_adc_channel_cali[line]) {
adc_cali_raw_to_voltage(_adc_channel_cali[line], raw, voltage);
return 0;
}
else {
/* default values for the case the calibration does not work */
int min = _adc_vrange_min_max[(_adc_channel_cfg[line].atten << 1)];
int max = _adc_vrange_min_max[(_adc_channel_cfg[line].atten << 1) + 1];
*voltage = raw * (max - min) / 4096 + min;
return -EINVAL;
}
}
__attribute__((__deprecated__))
int adc_line_vref_to_gpio(adc_t line, gpio_t gpio)
{
LOG_TAG_ERROR("adc", "%s is no longer supported\n", __func__);
assert(0);
return 0;
}
static void _adc_driver_init(void)
{
if (_adc_driver_initialized) {
return;
}
/* do some configuration checks */
for (unsigned i = 0; i < ADC_NUMOF; i++) {
uint8_t rtcio = _gpio_rtcio_map[adc_channels[i]];
/* check whether the GPIO is a valid ADC channel pin */
if (rtcio == RTCIO_NA) {
LOG_TAG_ERROR("adc", "GPIO%d cannot be configured as ADC line\n",
adc_channels[i]);
assert(0);
}
if (_adc_hw[rtcio].adc_ctrl >= SOC_ADC_PERIPH_NUM) {
LOG_TAG_ERROR("adc", "Invalid ADC unit %u for ADC line %u\n",
_adc_hw[rtcio].adc_ctrl, adc_channels[i]);
assert(0);
}
if (_adc_hw[rtcio].adc_channel >= ADC_CHANNEL_MAX(_adc_hw[rtcio].adc_ctrl)) {
LOG_TAG_ERROR("adc", "Invalid ADC channel %u for ADC line %u\n",
_adc_hw[rtcio].adc_channel, adc_channels[i]);
assert(0);
}
#if CPU_FAM_ESP32C3
/* According to the ESP32-C3 Errata Sheet ADC2 does not work correctly. To
* use ADC2 and GPIO5 as ADC channel, CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3
* has to be set (default). */
if (_adc_hw[rtcio].adc_ctrl == ADC_UNIT_2) {
if (!IS_ACTIVE(CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3)) {
LOG_TAG_ERROR("adc", "ADC2 cannot be used on ESP32-C3 if "
"CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3 "
"is not set (ADC line %u)\n", i);
assert(0);
}
/* throw at least a warning */
LOG_TAG_WARNING("adc", "ADC line %u on ADC2 may not work correctly "
"on ESP32-C3, see errata sheet\n", i);
}
#endif
}
/* set the default bitwidth and the attenuation for all channels to 12 dB */
for (unsigned i = 0; i < ADC_NUMOF; i++) {
_adc_channel_cfg[i].bitwidth = ADC_BITWIDTH_DEFAULT;
_adc_channel_cfg[i].atten = ADC_ATTEN_DB_12;
}
_adc_driver_initialized = true;
}
static void _adc_ctrl_init(adc_unit_t unit)
{
DEBUG("[adc] %s: unit=%u\n", __func__, unit);
assert(unit < SOC_ADC_PERIPH_NUM);
if (_adc_handle[unit] != NULL) {
/* unit is already initialized */
return;
}
adc_oneshot_unit_init_cfg_t unit_cfg = {
.unit_id = unit,
.ulp_mode = ADC_ULP_MODE_DISABLE,
};
if (adc_oneshot_new_unit(&unit_cfg, &_adc_handle[unit]) != ESP_OK) {
LOG_TAG_ERROR("adc", "Could not initialize ADC unit %u\n", unit);
}
}
static void _adc_channel_config(adc_t line, adc_bitwidth_t width, adc_atten_t att)
{
DEBUG("[adc] %s: line=%u width=%d atten=%u\n", __func__, line, width, att);
uint8_t rtcio = _gpio_rtcio_map[adc_channels[line]];
assert(rtcio != RTCIO_NA);
_adc_channel_cfg[line].bitwidth = width;
_adc_channel_cfg[line].atten = att;
if (_adc_hw[rtcio].adc_ctrl == ADC_UNIT_1) {
/* ensure compatibility of given adc_channel_t with adc1_channel_t */
assert(_adc_hw[rtcio].adc_channel < (adc_channel_t)ADC1_CHANNEL_MAX);
return adc1_config_channel_atten((adc1_channel_t)_adc_hw[rtcio].adc_channel, atten);
}
else if (_adc_hw[rtcio].adc_ctrl == ADC_UNIT_2) {
/* ensure compatibility of given adc_channel_t with adc2_channel_t */
assert(_adc_hw[rtcio].adc_channel < (adc_channel_t)ADC2_CHANNEL_MAX);
return adc2_config_channel_atten((adc2_channel_t)_adc_hw[rtcio].adc_channel, atten);
if (adc_oneshot_config_channel(_adc_handle[_adc_hw[rtcio].adc_ctrl],
_adc_hw[rtcio].adc_channel,
&_adc_channel_cfg[line]) != ESP_OK) {
LOG_TAG_ERROR("adc", "Could not config ADC line %u\n", line);
return;
}
return -1;
}
int adc_line_vref_to_gpio(adc_t line, gpio_t gpio)
{
uint8_t rtcio_vref = _gpio_rtcio_map[adc_channels[line]];
uint8_t rtcio_out = _gpio_rtcio_map[gpio];
/* both the ADC line and the GPIO for the output must be ADC channels */
assert(rtcio_vref != RTCIO_NA);
assert(rtcio_out != RTCIO_NA);
/* avoid compilation problems with NDEBUG defined */
(void)rtcio_out;
/* the GPIO for the output must be a channel of ADC2 */
assert(_adc_hw[rtcio_out].adc_ctrl == ADC_UNIT_2);
/* given ADC line has to be a channel of ADC2 */
assert(_adc_hw[rtcio_vref].adc_ctrl == ADC_UNIT_2);
esp_err_t res = ESP_OK;
if (_adc_hw[rtcio_vref].adc_ctrl == ADC_UNIT_1) {
res = adc_vref_to_gpio(ADC_UNIT_1, gpio);
}
else if (_adc_hw[rtcio_vref].adc_ctrl == ADC_UNIT_2) {
res = adc_vref_to_gpio(ADC_UNIT_2, gpio);
if (_adc_channel_cali[line]) {
/* delete allocated calibration scheme if necessary */
#if ADC_CALI_SCHEME_CURVE_FITTING_SUPPORTED
adc_cali_delete_scheme_curve_fitting(_adc_channel_cali[line]);
#elif ADC_CALI_SCHEME_LINE_FITTING_SUPPORTED
adc_cali_delete_scheme_line_fitting(_adc_channel_cali[line]);
#endif
_adc_channel_cali[line] = NULL;
}
#if ADC_CALI_SCHEME_CURVE_FITTING_SUPPORTED
adc_cali_curve_fitting_config_t cfg = {
.unit_id = _adc_hw[rtcio].adc_ctrl,
.chan = _adc_hw[rtcio].adc_channel,
.atten = _adc_channel_cfg[line].atten,
.bitwidth = _adc_channel_cfg[line].bitwidth,
};
int res = adc_cali_create_scheme_curve_fitting(&cfg, &_adc_channel_cali[line]);
if (res != ESP_OK) {
LOG_TAG_ERROR("adc", "Could not route Vref of ADC line %d to GPIO%d\n",
line, gpio);
return -1;
DEBUG("[adc] %s: init calibration scheme failed %d\n", __func__, res);
return;
}
else {
LOG_TAG_ERROR("adc", "Vref of ADC%d can now be measured at GPIO %d\n",
_adc_hw[rtcio_vref].adc_ctrl, gpio);
return 0;
#elif ADC_CALI_SCHEME_LINE_FITTING_SUPPORTED
adc_cali_line_fitting_config_t cfg = {
.unit_id = _adc_hw[rtcio].adc_ctrl,
.atten = _adc_channel_cfg[line].atten,
.bitwidth = _adc_channel_cfg[line].bitwidth,
#if CONFIG_IDF_TARGET_ESP32
.default_vref = 1100,
#endif
};
int res = adc_cali_create_scheme_line_fitting(&cfg, &_adc_channel_cali[line]);
if (res != ESP_OK) {
DEBUG("[adc] %s: init calibration scheme failed %d\n", __func__, res);
return;
}
}
static bool _adc_conf_check(void)
{
for (unsigned i = 0; i < ADC_NUMOF; i++) {
if (_gpio_rtcio_map[adc_channels[i]] == RTCIO_NA) {
LOG_TAG_ERROR("adc", "GPIO%d cannot be used as ADC line\n",
adc_channels[i]);
return false;
}
}
return true;
#endif
}
void adc_print_config(void)

16
cpu/esp32/periph/adc_arch_esp32.c
View File

@ -107,7 +107,23 @@ const gpio_t _gpio_rtcio_map[] = {
RTCIO_GPIO(3), /* GPIO39 SENSOR_VN */
};
/**
* @brief Default voltage range of ADC results for different attenuations
*
* These values are used by function adc_get_vrange_min_max if software
* calibration doesn't work for any reason and the voltage range can't be
* determined by software.
*/
const int _adc_vrange_min_max[] = {
0, 950, /* min, max @ ADC_ATTEN_DB_0 */
0, 1250, /* min, max @ ADC_ATTEN_DB_2_5 */
0, 1750, /* min, max @ ADC_ATTEN_DB_6 */
0, 2450, /* min, max @ ADC_ATTEN_DB_12 */
};
_Static_assert(ARRAY_SIZE(_adc_hw) == SOC_RTCIO_PIN_COUNT,
"size of _adc_hw does not match SOC_RTCIO_PIN_COUNT");
_Static_assert(ARRAY_SIZE(_gpio_rtcio_map) == SOC_GPIO_PIN_COUNT,
"size of _gpio_rtcio_map does not match SOC_GPIO_PIN_COUNT");
_Static_assert(ARRAY_SIZE(_adc_vrange_min_max) == (SOC_ADC_ATTEN_NUM * 2),
"size of _adc_vrange_min_max does not match SOC_ADC_ATTEN_NUM");

19
cpu/esp32/periph/adc_arch_esp32c3.c
View File

@ -71,5 +71,24 @@ const gpio_t _gpio_rtcio_map[] = {
RTCIO_NA, /* GPIO21 */
};
/**
* @brief Default voltage range of ADC results for different attenuations
*
* These values are used by function adc_get_vrange_min_max if software
* calibration doesn't work for any reason and the voltage range can't be
* determined by software.
*
* Table 5-6 in [ESP32-C3 Datasheet]
* (https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf).
*/
const int _adc_vrange_min_max[] = {
0, 750, /* min, max @ ADC_ATTEN_DB_0 */
0, 1050, /* min, max @ ADC_ATTEN_DB_2_5 */
0, 1300, /* min, max @ ADC_ATTEN_DB_6 */
0, 2500, /* min, max @ ADC_ATTEN_DB_12 */
};
_Static_assert(ARRAY_SIZE(_gpio_rtcio_map) == SOC_GPIO_PIN_COUNT,
"size of _gpio_rtcio_map does not match SOC_GPIO_PIN_COUNT");
_Static_assert(ARRAY_SIZE(_adc_vrange_min_max) == (SOC_ADC_ATTEN_NUM * 2),
"size of _adc_vrange_min_max does not match SOC_ADC_ATTEN_NUM");

20
cpu/esp32/periph/adc_arch_esp32s2.c
View File

@ -38,7 +38,7 @@
*/
const _adc_hw_desc_t _adc_hw[] = {
/* rtcio, gpio, adc_ctrl, adc_channel, pad_name */
{ RTCIO_GPIO(0), GPIO0, ADC_UNIT_MAX, ADC_CHANNEL_MAX, "GPIO0" },
{ RTCIO_GPIO(0), GPIO0, ADC_UNIT_INV, ADC_CHANNEL_INV, "GPIO0" },
{ RTCIO_GPIO(1), ADC1_CHANNEL_0_GPIO_NUM, ADC_UNIT_1, ADC_CHANNEL_0, "TOUCH1" },
{ RTCIO_GPIO(2), ADC1_CHANNEL_1_GPIO_NUM, ADC_UNIT_1, ADC_CHANNEL_1, "TOUCH2" },
{ RTCIO_GPIO(3), ADC1_CHANNEL_2_GPIO_NUM, ADC_UNIT_1, ADC_CHANNEL_2, "TOUCH3" },
@ -59,7 +59,7 @@ const _adc_hw_desc_t _adc_hw[] = {
{ RTCIO_GPIO(18), ADC2_CHANNEL_7_GPIO_NUM, ADC_UNIT_2, ADC_CHANNEL_7, "DAC2" },
{ RTCIO_GPIO(19), ADC2_CHANNEL_8_GPIO_NUM, ADC_UNIT_2, ADC_CHANNEL_8, "USB_D-" },
{ RTCIO_GPIO(20), ADC2_CHANNEL_9_GPIO_NUM, ADC_UNIT_2, ADC_CHANNEL_9, "USB_D+" },
{ RTCIO_GPIO(21), GPIO21, ADC_UNIT_MAX, ADC_CHANNEL_MAX, "GPIO21" },
{ RTCIO_GPIO(21), GPIO21, ADC_UNIT_INV, ADC_CHANNEL_INV, "GPIO21" },
};
/**
@ -118,7 +118,23 @@ const gpio_t _gpio_rtcio_map[] = {
RTCIO_NA, /* GPIO46 */
};
/**
* @brief Default voltage range of ADC results for different attenuations
*
* These values are used by function adc_get_vrange_min_max if software
* calibration doesn't work for any reason and the voltage range can't be
* determined by software.
*/
const int _adc_vrange_min_max[] = {
0, 750, /* min, max @ ADC_ATTEN_DB_0 */
0, 1050, /* min, max @ ADC_ATTEN_DB_2_5 */
0, 1300, /* min, max @ ADC_ATTEN_DB_6 */
0, 2500, /* min, max @ ADC_ATTEN_DB_12 */
};
_Static_assert(ARRAY_SIZE(_adc_hw) == SOC_RTCIO_PIN_COUNT,
"size of _adc_hw does not match SOC_RTCIO_PIN_COUNT");
_Static_assert(ARRAY_SIZE(_gpio_rtcio_map) == SOC_GPIO_PIN_COUNT,
"size of _gpio_rtcio_map does not match SOC_GPIO_PIN_COUNT");
_Static_assert(ARRAY_SIZE(_adc_vrange_min_max) == (SOC_ADC_ATTEN_NUM * 2),
"size of _adc_vrange_min_max does not match SOC_ADC_ATTEN_NUM");

25
cpu/esp32/periph/adc_arch_esp32s3.c
View File

@ -37,8 +37,8 @@
* RTCIO GPIO number.
*/
const _adc_hw_desc_t _adc_hw[] = {
/* rtcio, gpio, adc_ctrl, adc_channel, pad_name */
{ RTCIO_GPIO(0), GPIO0, ADC_UNIT_MAX, ADC_CHANNEL_MAX, "GPIO0" },
/* rtcio, gpio, adc_ctrl, adc_channel, pad_name */
{ RTCIO_GPIO(0), GPIO0, ADC_UNIT_INV, ADC_CHANNEL_INV, "GPIO0" },
{ RTCIO_GPIO(1), ADC1_CHANNEL_0_GPIO_NUM, ADC_UNIT_1, ADC_CHANNEL_0, "TOUCH1" },
{ RTCIO_GPIO(2), ADC1_CHANNEL_1_GPIO_NUM, ADC_UNIT_1, ADC_CHANNEL_1, "TOUCH2" },
{ RTCIO_GPIO(3), ADC1_CHANNEL_2_GPIO_NUM, ADC_UNIT_1, ADC_CHANNEL_2, "TOUCH3" },
@ -59,7 +59,7 @@ const _adc_hw_desc_t _adc_hw[] = {
{ RTCIO_GPIO(18), ADC2_CHANNEL_7_GPIO_NUM, ADC_UNIT_2, ADC_CHANNEL_7, "GPIO18" },
{ RTCIO_GPIO(19), ADC2_CHANNEL_8_GPIO_NUM, ADC_UNIT_2, ADC_CHANNEL_8, "USB_D-" },
{ RTCIO_GPIO(20), ADC2_CHANNEL_9_GPIO_NUM, ADC_UNIT_2, ADC_CHANNEL_9, "USB_D+" },
{ RTCIO_GPIO(21), GPIO21, ADC_UNIT_MAX, ADC_CHANNEL_MAX, "GPIO21" },
{ RTCIO_GPIO(21), GPIO21, ADC_UNIT_INV, ADC_CHANNEL_INV, "GPIO21" },
};
/**
@ -120,7 +120,26 @@ const gpio_t _gpio_rtcio_map[] = {
RTCIO_NA, /* GPIO48 */
};
/**
* @brief Default voltage range of ADC results for different attenuations
*
* These values are used by function adc_get_vrange_min_max if software
* calibration doesn't work for any reason and the voltage range can't be
* determined by software.
*
* Table 5-5 in [ESP32-S3 Datasheet]
* (https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf).
*/
const int _adc_vrange_min_max[] = {
0, 850, /* min, max @ ADC_ATTEN_DB_0 */
0, 1100, /* min, max @ ADC_ATTEN_DB_2_5 */
0, 1600, /* min, max @ ADC_ATTEN_DB_6 */
0, 2900, /* min, max @ ADC_ATTEN_DB_12 */
};
_Static_assert(ARRAY_SIZE(_adc_hw) == SOC_RTCIO_PIN_COUNT,
"size of _adc_hw does not match SOC_RTCIO_PIN_COUNT");
_Static_assert(ARRAY_SIZE(_gpio_rtcio_map) == SOC_GPIO_PIN_COUNT,
"size of _gpio_rtcio_map does not match SOC_GPIO_PIN_COUNT");
_Static_assert(ARRAY_SIZE(_adc_vrange_min_max) == (SOC_ADC_ATTEN_NUM * 2),
"size of _adc_vrange_min_max does not match SOC_ADC_ATTEN_NUM");

19
cpu/esp32/periph/can.c
View File

@ -25,13 +25,14 @@
#include "gpio_arch.h"
#include "irq_arch.h"
#include "driver/periph_ctrl.h"
#include "esp_clk_tree.h"
#include "esp_cpu.h"
#include "esp_private/periph_ctrl.h"
#include "esp_rom_gpio.h"
#include "hal/interrupt_controller_types.h"
#include "hal/interrupt_controller_ll.h"
#include "hal/twai_hal.h"
#include "log.h"
#include "rom/ets_sys.h"
#include "soc/clk_tree_defs.h"
#include "soc/gpio_sig_map.h"
#define ENABLE_DEBUG 0
@ -592,11 +593,17 @@ static void _esp_can_power_up(can_t *dev)
periph_module_reset(PERIPH_TWAI_MODULE);
periph_module_enable(PERIPH_TWAI_MODULE);
twai_hal_config_t config = { .controller_id = 0 };
esp_clk_tree_src_get_freq_hz((soc_module_clk_t)TWAI_CLK_SRC_DEFAULT,
ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED,
&config.clock_source_hz);
/* initialize the HAL context, on return the CAN controller is in listen
* only mode but not yet started, the error counters are reset and
* pending interrupts cleared */
if (!twai_hal_init(&hw)) {
if (!twai_hal_init(&hw, &config)) {
assert(false);
}
@ -608,8 +615,8 @@ static void _esp_can_power_up(can_t *dev)
/* route CAN interrupt source to CPU interrupt and enable it */
intr_matrix_set(PRO_CPU_NUM, ETS_TWAI_INTR_SOURCE, CPU_INUM_CAN);
intr_cntrl_ll_set_int_handler(CPU_INUM_CAN, _esp_can_intr_handler, (void*)(uintptr_t)dev);
intr_cntrl_ll_enable_interrupts(BIT(CPU_INUM_CAN));
esp_cpu_intr_set_handler(CPU_INUM_CAN, _esp_can_intr_handler, (void*)(uintptr_t)dev);
esp_cpu_intr_enable(BIT(CPU_INUM_CAN));
/* initialize used GPIOs */
_esp_can_init_pins();

13
cpu/esp32/periph/dac.c
View File

@ -23,12 +23,15 @@
#include "periph/dac.h"
#include "esp_common.h"
#include "driver/dac_common.h"
#include "hal/dac_ll.h"
#include "soc/dac_periph.h"
#define ENABLE_DEBUG 0
#include "debug.h"
/* for source code compatibility */
#define DAC_CHANNEL_MAX SOC_DAC_CHAN_NUM
/* forward declarations of internal functions */
static bool _dac_conf_check(void);
static bool _dac_module_initialized = false;
@ -61,27 +64,27 @@ void dac_set(dac_t line, uint16_t value)
{
assert(line < DAC_NUMOF);
assert(_dac_channels[line] != DAC_CHANNEL_MAX);
dac_output_voltage(_dac_channels[line], value >> (16 - SOC_DAC_RESOLUTION));
dac_ll_update_output_value(_dac_channels[line], value >> (16 - SOC_DAC_RESOLUTION));
}
void dac_poweroff(dac_t line)
{
assert(line < DAC_NUMOF);
assert(_dac_channels[line] != DAC_CHANNEL_MAX);
dac_output_disable(_dac_channels[line]);
dac_ll_power_down(_dac_channels[line]);
}
void dac_poweron(dac_t line)
{
assert(line < DAC_NUMOF);
assert(_dac_channels[line] != DAC_CHANNEL_MAX);
dac_output_enable(_dac_channels[line]);
dac_ll_power_on(_dac_channels[line]);
}
static bool _dac_conf_check(void)
{
for (unsigned i = 0; i < DAC_NUMOF; i++) {
for (unsigned j = 0; i < SOC_DAC_PERIPH_NUM; j++) {
for (unsigned j = 0; i < SOC_DAC_CHAN_NUM; j++) {
if (dac_channels[i] == dac_periph_signal.dac_channel_io_num[j]) {
_dac_channels[i] = j;
break;

102
cpu/esp32/periph/flashpage.c
View File

@ -27,12 +27,16 @@
#include "irq.h"
#include "log.h"
#include "esp_flash_partitions.h"
#include "esp_spi_flash.h"
#include "esp_private/cache_utils.h"
#include "esp_flash.h"
#include "esp_flash_internal.h"
#include "hal/cache_hal.h"
#include "hal/mmu_hal.h"
#include "rom/cache.h"
#include "rom/spi_flash.h"
#include "soc/mmu.h"
#include "soc/soc.h"
#include "soc/ext_mem_defs.h"
#include "spi_flash_mmap.h"
#define ENABLE_DEBUG 0
#include "debug.h"
@ -42,16 +46,35 @@
#define ESP_PART_ENTRY_SIZE 0x20
#define ESP_PART_ENTRY_MAGIC ESP_PARTITION_MAGIC
extern uint8_t _fp_mmu_start;
extern uint8_t _fp_mmu_end;
extern uint8_t _fp_mem_start; /* start address in CPU address space */
extern uint8_t _fp_mem_end;
extern uint8_t _end_fw;
static uint32_t _fp_flash_start; /* start address in flash */
void IRAM_ATTR esp_sync_cache(uint32_t target_addr, size_t len)
{
DEBUG("%s sync cache from @0x%08"PRIx32" for %u\n",
__func__, target_addr, len);
for (uint32_t addr = target_addr; addr < (target_addr + len);
addr += SPI_FLASH_MMU_PAGE_SIZE) {
#if defined(CPU_FAM_ESP32)
extern void cache_sync(void);
cache_sync();
#else
cache_hal_invalidate_addr((uint32_t)addr, SPI_FLASH_MMU_PAGE_SIZE);
#endif
}
}
void IRAM_ATTR esp_flashpage_init(void)
{
/* CONFIG_ESP_FLASHPAGE_CAPACITY has to be a multiple of SPI_FLASH_MMU_PAGE_SIZE */
assert((CONFIG_ESP_FLASHPAGE_CAPACITY % SPI_FLASH_MMU_PAGE_SIZE) == 0);
assert((FLASHPAGE_ADDR_START % SPI_FLASH_MMU_PAGE_SIZE) == 0);
DEBUG("%s pages in CPU address space @0x%08"PRIx32"...0x%08"PRIx32"\n", __func__,
CPU_FLASH_BASE, CPU_FLASH_BASE + CONFIG_ESP_FLASHPAGE_CAPACITY - 1);
@ -65,47 +88,43 @@ void IRAM_ATTR esp_flashpage_init(void)
uint32_t p_numof = CONFIG_ESP_FLASHPAGE_CAPACITY / SPI_FLASH_MMU_PAGE_SIZE;
uint32_t p_addr = FLASHPAGE_ADDR_START;
#if CPU_FAM_ESP32S2
/* ESP32-S2 requires special handling to enable the MMU pages in Cache
* explicitly */
uint32_t autoload = Cache_Suspend_ICache();
Cache_Invalidate_ICache_All();
int res = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, (uint32_t)&_fp_mem_start,
p_addr, 64, p_numof, 0);
Cache_Resume_ICache(autoload);
DEBUG("%s DCache MMU set paddr=%08"PRIx32" vaddr=%08"PRIx32" size=%d n=%"PRIu32"\n",
__func__, p_addr, (uint32_t)&_fp_mem_start, CONFIG_ESP_FLASHPAGE_CAPACITY,
p_numof);
if (res != ESP_OK) {
LOG_TAG_ERROR("flashpage",
"Could not map MMU pages in DCache, error: %d\n", res);
}
#else
uint32_t p_mmu = ((uint32_t)&_fp_mem_start - SOC_DROM_LOW) / SPI_FLASH_MMU_PAGE_SIZE;
uint32_t p_mmu = ((uint32_t)&_fp_mmu_start - SOC_DROM_LOW) / SPI_FLASH_MMU_PAGE_SIZE;
while (p_numof--) {
uint32_t p_flash = p_addr / SPI_FLASH_MMU_PAGE_SIZE;
uint32_t mmu_addr = SOC_DROM_LOW + (p_mmu * SPI_FLASH_MMU_PAGE_SIZE);
DEBUG("%s map MMU page %"PRIu32" @0x%08"PRIx32" to "
"flash page %"PRIu32" @0x%08"PRIx32"\n", __func__,
p_mmu, (p_mmu * SPI_FLASH_MMU_PAGE_SIZE) + SOC_DROM_LOW,
p_mmu, mmu_addr,
p_flash, p_flash * SPI_FLASH_MMU_PAGE_SIZE);
SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE[p_mmu] = SOC_MMU_PAGE_IN_FLASH(p_flash);
spi_flash_mmap_handle_t t_handle;
const void *t_mem;
esp_err_t res;
res = spi_flash_mmap(p_addr, SPI_FLASH_MMU_PAGE_SIZE, SPI_FLASH_MMAP_DATA,
&t_mem, &t_handle);
assert((uint32_t)t_mem == mmu_addr);
DEBUG("%s map MMU page %"PRIu32" @0x%08"PRIx32" to "
"flash page %"PRIu32" @0x%08"PRIx32" %s\n", __func__,
p_mmu, (uint32_t)t_mem,
p_flash, p_flash * SPI_FLASH_MMU_PAGE_SIZE,
res == ESP_OK ? "OK" : "NOK");
p_addr += SPI_FLASH_MMU_PAGE_SIZE;
p_mmu++;
}
#endif
irq_restore(state);
if (IS_ACTIVE(ENABLE_DEBUG)) {
if (ENABLE_DEBUG) {
spi_flash_mmap_dump();
}
}
void flashpage_erase(unsigned page)
void IRAM_ATTR flashpage_erase(unsigned page)
{
assert(page < FLASHPAGE_NUMOF);
@ -113,14 +132,20 @@ void flashpage_erase(unsigned page)
DEBUG("%s erase page in flash @0x%08"PRIx32"\n", __func__, flash_addr);
int res = spi_flash_erase_range(flash_addr, FLASHPAGE_SIZE);
uint32_t state = irq_disable();
int res = esp_flash_erase_region(esp_flash_default_chip, flash_addr, FLASHPAGE_SIZE);
esp_sync_cache((uint32_t)&_fp_mmu_start + (page * FLASHPAGE_SIZE), FLASHPAGE_SIZE);
irq_restore(state);
if (res != ESP_OK) {
LOG_TAG_ERROR("flashpage", "Could not erase page %u, error %d\n",
page, res);
}
}
void flashpage_write(void *target_addr, const void *data, size_t len)
void IRAM_ATTR flashpage_write(void *target_addr, const void *data, size_t len)
{
DEBUG("%s write %u byte from @%p to @%p\n",
__func__, len, data, target_addr);
@ -135,12 +160,18 @@ void flashpage_write(void *target_addr, const void *data, size_t len)
assert(((unsigned)target_addr + len) <=
(CPU_FLASH_BASE + (FLASHPAGE_SIZE * FLASHPAGE_NUMOF)));
uint32_t flash_addr = ((uint32_t)target_addr - (uint32_t)&_fp_mem_start) + _fp_flash_start;
uint32_t flash_addr = ((uint32_t)target_addr - (uint32_t)&_fp_mmu_start) + _fp_flash_start;
DEBUG("%s write to CPU address @%p (flash @0x%08"PRIx32")\n",
__func__, target_addr, flash_addr);
int res = spi_flash_write(flash_addr, data, len);
uint32_t state = irq_disable();
int res = esp_flash_write(esp_flash_default_chip, data, flash_addr, len);
esp_sync_cache((uint32_t)target_addr, len);
irq_restore(state);
if (res != ESP_OK) {
LOG_TAG_ERROR("flashpage", "Could not write to CPU address @%p "
"(flash @0x%08"PRIx32"), error %d\n",
@ -148,14 +179,13 @@ void flashpage_write(void *target_addr, const void *data, size_t len)
}
}
unsigned flashpage_first_free(void)
unsigned IRAM_ATTR flashpage_first_free(void)
{
/* _end_fw is page aligned */
return flashpage_page(&_end_fw);
}
unsigned flashpage_last_free(void)
unsigned IRAM_ATTR flashpage_last_free(void)
{
// return flashpage_page((const void *)SOC_DROM_HIGH) - 1;
return flashpage_page((void *)(CPU_FLASH_BASE + CONFIG_ESP_FLASHPAGE_CAPACITY)) - 1;
}

151
cpu/esp32/periph/gpio.c
View File

@ -27,8 +27,10 @@
#include "periph/gpio_ll_arch.h"
#endif
#include "driver/rtc_io.h"
#include "esp/common_macros.h"
#include "esp_intr_alloc.h"
#include "driver/rtc_io.h"
#include "hal/gpio_hal.h"
#include "hal/gpio_types.h"
#include "hal/rtc_io_types.h"
@ -44,10 +46,9 @@
#include "xtensa/xtensa_api.h"
#endif
#include "esp_idf_api/gpio.h"
#include "adc_arch.h"
#include "bitarithm.h"
#include "bitfield.h"
#include "board.h"
#include "esp_common.h"
#include "esp_sleep.h"
#include "gpio_arch.h"
@ -58,23 +59,42 @@
#include "debug.h"
#if SOC_PM_SUPPORT_EXT_WAKEUP
#if CPU_FAM_ESP32
#define ESP_PM_WUP_PINS_ANY_HIGH ESP_EXT1_WAKEUP_ANY_HIGH
#define ESP_PM_WUP_PINS_ALL_LOW ESP_EXT1_WAKEUP_ALL_LOW
#define ESP_PM_WUP_PINS_ANY_LOW -1
#endif
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
#define ESP_PM_WUP_PINS_ALL_LOW ESP_EXT1_WAKEUP_ALL_LOW
#else /* CPU_FAM_ESP32 */
#define ESP_PM_WUP_PINS_ANY_HIGH ESP_EXT1_WAKEUP_ANY_HIGH
#define ESP_PM_WUP_PINS_ANY_LOW ESP_EXT1_WAKEUP_ANY_LOW
#define ESP_PM_WUP_PINS_ALL_LOW -1
#endif /* CPU_FAM_ESP32 */
#elif SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
#define ESP_PM_WUP_PINS_ANY_HIGH ESP_GPIO_WAKEUP_GPIO_HIGH
#define ESP_PM_WUP_PINS_ANY_LOW ESP_GPIO_WAKEUP_GPIO_LOW
#define ESP_PM_WUP_PINS_ALL_LOW -1
#else
#define ESP_PM_WUP_PINS_ANY_HIGH -1
#define ESP_PM_WUP_PINS_ANY_LOW -1
#define ESP_PM_WUP_PINS_ALL_LOW -1
#endif
#if CPU_FAM_ESP32
#if ESP_PM_WUP_LEVEL == ESP_PM_WUP_PINS_ANY_LOW
#error "ESP_PM_WUP_PINS_ANY_LOW is not allowed as ESP_PM_WUP_LEVEL."
#endif
#else
#if ESP_PM_WUP_LEVEL == ESP_PM_WUP_PINS_ALL_LOW
#error "ESP_PM_WUP_PINS_ALL_LOW is not allowed as ESP_PM_WUP_LEVEL."
#endif
#endif
#ifndef ESP_PM_WUP_LEVEL
#define ESP_PM_WUP_LEVEL ESP_PM_WUP_PINS_ANY_HIGH
#endif
#if ESP_PM_WUP_LEVEL == -1
#error "ESP32x SoC does not support this ESP_PM_WUP_LEVEL"
#error "ESP32x variant does not support this ESP_PM_WUP_LEVEL"
#endif
#define GPIO_PRO_CPU_INTR_ENA (BIT(2))
@ -234,12 +254,23 @@ int gpio_init(gpio_t pin, gpio_mode_t mode)
cfg.intr_type = GPIO_INTR_DISABLE;
#ifdef ESP_PM_WUP_PINS
/* for saving the pullup/pulldown settings of wakeup pins in deep sleep mode */
/* for saving the pullup/pulldown settings of wakeup pins in deep sleep mode */
_gpio_pin_pu[pin] = cfg.pull_up_en;
_gpio_pin_pd[pin] = cfg.pull_down_en;
#if SOC_RTCIO_HOLD_SUPPORTED
/* disable the RTCIO hold function for the case we come from deep sleep */
rtc_gpio_hold_dis(pin);
#endif /* SOC_RTCIO_HOLD_SUPPORTED */
#endif /* ESP_PM_WUP_PINS */
#ifdef ESP_PM_GPIO_HOLD
#if SOC_RTCIO_HOLD_SUPPORTED
/* disable the RTCIO hold function for the case we come from deep sleep */
rtc_gpio_force_hold_dis_all();
#endif
#endif
return (esp_idf_gpio_config(&cfg) == ESP_OK) ? 0 : -1;
return (gpio_config(&cfg) == ESP_OK) ? 0 : -1;
}
#if MODULE_PERIPH_GPIO_IRQ
@ -283,18 +314,18 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
/* install GPIO ISR of ESP-IDF if not yet done */
if (!gpio_isr_service_installed &&
esp_idf_gpio_install_isr_service(ESP_INTR_FLAG_LEVEL1) != ESP_OK) {
gpio_install_isr_service(ESP_INTR_FLAG_LEVEL1) != ESP_OK) {
return -1;
}
gpio_isr_service_installed = true;
/* set the interrupt type for the pin */
if (esp_idf_gpio_set_intr_type(pin, type) != ESP_OK) {
if (gpio_set_intr_type(pin, type) != ESP_OK) {
return -1;
}
/* unmask and clear pending interrupts for the pin */
if (esp_idf_gpio_isr_handler_add(pin, cb, arg) != ESP_OK) {
if (gpio_isr_handler_add(pin, cb, arg) != ESP_OK) {
return -1;
}
@ -308,7 +339,7 @@ void gpio_irq_enable(gpio_t pin)
DEBUG("%s: gpio=%d\n", __func__, pin);
assert(pin < GPIO_PIN_NUMOF);
if (esp_idf_gpio_intr_enable(pin) == ESP_OK) {
if (gpio_intr_enable(pin) == ESP_OK) {
gpio_int_enabled_table[pin] = true;
}
}
@ -318,7 +349,7 @@ void gpio_irq_disable(gpio_t pin)
DEBUG("%s: gpio=%d\n", __func__, pin);
assert(pin < GPIO_PIN_NUMOF);
if (esp_idf_gpio_intr_disable(pin) == ESP_OK) {
if (gpio_intr_disable(pin) == ESP_OK) {
gpio_int_enabled_table[pin] = false;
}
}
@ -473,12 +504,16 @@ void gpio_pm_sleep_enter(unsigned mode)
{
if (mode == ESP_PM_DEEP_SLEEP) {
#ifdef ESP_PM_GPIO_HOLD
/*
* Activate the power domain for RTC peripherals when
* ESP_PM_GPIO_HOLD is defined for deep sleep mode.
*/
esp_idf_gpio_deep_sleep_hold();
esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON);
#if SOC_RTCIO_HOLD_SUPPORTED
rtc_gpio_force_hold_en_all();
#if CPU_FAM_ESP32
/* isolating GPIO12 from external circuits is especially recommended for
* ESP32-WROVER that have an external pullup on GPIO12 */
rtc_gpio_isolate(GPIO_NUM_12);
#endif
#else
# error "ESP32x variant does not support hold feature in deep sleep";
#endif
#endif
#ifdef ESP_PM_WUP_PINS
@ -491,6 +526,37 @@ void gpio_pm_sleep_enter(unsigned mode)
for (unsigned i = 0; i < ARRAY_SIZE(wup_pins); i++) {
wup_pin_mask |= 1ULL << wup_pins[i];
/* ensure that valid GPIOs are used as wake-up source */
#if SOC_PM_SUPPORT_EXT1_WAKEUP
if (rtc_io_num_map[wup_pins[i]] < 0) {
LOG_ERROR("GPIO%u is not a valid wake-up source, valid GPIOs are:",
wup_pins[i]);
for (unsigned j = 0; j < SOC_GPIO_PIN_COUNT; j++) {
if (rtc_io_num_map[j] != -1) {
printf(" GPIO%u", j);
}
}
printf("\n");
assert(false);
}
#elif SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
if (((1ULL << wup_pins[i]) & SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK) == 0) {
LOG_ERROR("GPIO%u is not a valid wake-up source, valid GPIOs are:",
wup_pins[i]);
unsigned valid_num = bitarithm_bits_set(SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK);
uint32_t valid_mask = SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK;
for (unsigned j = 0; j < valid_num ; j++) {
if (valid_mask & 1) {
printf(" GPIO%u ", j);
}
valid_mask = valid_mask >> 1;
}
printf("\n");
assert(false);
}
#endif
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
/* If internal pullups/pulldowns are used, they have to be
activated also in deep sleep mode in RTC power domain */
@ -499,33 +565,40 @@ void gpio_pm_sleep_enter(unsigned mode)
assert(rtc_io_num_map[wup_pins[i]] >= 0);
if (_gpio_pin_pu[wup_pins[i]]) {
pu_pd_used = true;
esp_idf_rtc_gpio_pullup_en(wup_pins[i]);
rtc_gpio_pullup_en(wup_pins[i]);
rtc_gpio_pulldown_dis(wup_pins[i]);
}
else {
esp_idf_rtc_gpio_pullup_dis(wup_pins[i]);
}
if (_gpio_pin_pd[wup_pins[i]]) {
else if (_gpio_pin_pd[wup_pins[i]]) {
pu_pd_used = true;
esp_idf_rtc_gpio_pulldown_en(wup_pins[i]);
}
else {
esp_idf_rtc_gpio_pulldown_dis(wup_pins[i]);
rtc_gpio_pullup_dis(wup_pins[i]);
rtc_gpio_pulldown_en(wup_pins[i]);
}
if (pu_pd_used) {
#if SOC_PM_SUPPORT_RTC_PERIPH_PD
/* If internal pullups/pulldowns are used, the RTC power domain
* must remain active in deep sleep mode */
* must remain active in deep sleep mode if supported */
esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON);
#endif
}
#endif /* SOC_RTCIO_INPUT_OUTPUT_SUPPORTED */
#elif SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP && SOC_DEEP_SLEEP_SUPPORTED
if (_gpio_pin_pu[wup_pins[i]]) {
gpio_pullup_en(wup_pins[i]);
gpio_pulldown_dis(wup_pins[i]);
}
else if (_gpio_pin_pd[wup_pins[i]]) {
gpio_pullup_dis(wup_pins[i]);
gpio_pulldown_en(wup_pins[i]);
}
#endif
}
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
#if SOC_PM_SUPPORT_EXT1_WAKEUP
/* ESP_PM_WUP_PINS_ALL_LOW or ESP_PM_WUP_PINS_ANY_HIGH */
esp_sleep_enable_ext1_wakeup_io(wup_pin_mask, ESP_PM_WUP_LEVEL);
#elif SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP && SOC_DEEP_SLEEP_SUPPORTED
/* ESP_PM_WUP_PINS_ANY_LOW or ESP_PM_WUP_PINS_ANY_HIGH */
esp_deep_sleep_enable_gpio_wakeup(wup_pin_mask, ESP_PM_WUP_LEVEL);
#elif SOC_PM_SUPPORT_EXT_WAKEUP
/* ESP_PM_WUP_PINS_ALL_LOW or ESP_PM_WUP_PINS_ANY_HIGH */
esp_sleep_enable_ext1_wakeup(wup_pin_mask, ESP_PM_WUP_LEVEL);
#else
#error "ESP32x SoC variant doesn't allow to define GPIOs for wake-up from deep sleep"
#error "ESP32x variant doesn't allow to define GPIOs for wake-up from deep sleep"
#endif
#endif /* ESP_PM_WUP_PINS */
}
@ -537,12 +610,12 @@ void gpio_pm_sleep_enter(unsigned mode)
switch (gpio_int_saved_type[i]) {
case GPIO_LOW:
case GPIO_FALLING:
esp_idf_gpio_wakeup_enable(i, GPIO_INTR_LOW_LEVEL);
gpio_wakeup_enable(i, GPIO_INTR_LOW_LEVEL);
DEBUG("%s gpio=%u GPIO_LOW\n", __func__, i);
break;
case GPIO_HIGH:
case GPIO_RISING:
esp_idf_gpio_wakeup_enable(i, GPIO_INTR_HIGH_LEVEL);
gpio_wakeup_enable(i, GPIO_INTR_HIGH_LEVEL);
DEBUG("%s gpio=%u GPIO_HIGH\n", __func__, i);
break;
case GPIO_BOTH:

11
cpu/esp32/periph/gpio_ll.c
View File

@ -28,14 +28,13 @@
#include "irq.h"
#include "periph/gpio_ll.h"
#include "driver/gpio.h"
#include "esp/common_macros.h"
#include "hal/gpio_hal.h"
#include "hal/gpio_types.h"
#include "gpio_ll_arch.h"
#include "soc/gpio_struct.h"
#include "esp_idf_api/gpio.h"
#ifdef MODULE_FMT
# include "fmt.h"
#else
@ -110,7 +109,7 @@ int gpio_ll_init(gpio_port_t port, uint8_t pin, gpio_conf_t conf)
}
#ifdef ESP_PM_WUP_PINS
/* for saving the pullup/pulldown settings of wakeup pins in deep sleep mode */
/* for saving the pullup/pulldown settings of wakeup pins in deep sleep mode */
_gpio_pin_pu[pin] = cfg.pull_up_en;
_gpio_pin_pd[pin] = cfg.pull_down_en;
#endif
@ -118,13 +117,13 @@ int gpio_ll_init(gpio_port_t port, uint8_t pin, gpio_conf_t conf)
if (conf.state == GPIO_DISCONNECT) {
/* reset the pin to disconnects any other peripheral output configured
via GPIO Matrix, the pin is reconfigured according to given conf */
esp_idf_gpio_reset_pin(gpio);
gpio_reset_pin(gpio);
}
/* since we can't read back the configuration, we have to save it */
_gpio_conf[gpio] = conf;
if (esp_idf_gpio_config(&cfg) != ESP_OK) {
if (gpio_config(&cfg) != ESP_OK) {
return -ENOTSUP;
}
@ -147,7 +146,7 @@ int gpio_ll_init(gpio_port_t port, uint8_t pin, gpio_conf_t conf)
strength = GPIO_DRIVE_CAP_DEFAULT;
}
if ((cfg.pin_bit_mask & SOC_GPIO_VALID_OUTPUT_GPIO_MASK) &&
(esp_idf_gpio_set_drive_capability(gpio, strength) != ESP_OK)) {
(gpio_set_drive_capability(gpio, strength) != ESP_OK)) {
return -ENOTSUP;
}

15
cpu/esp32/periph/gpio_ll_irq.c
View File

@ -27,6 +27,7 @@
#include "log.h"
#include "periph/gpio_ll_irq.h"
#include "driver/gpio.h"
#include "esp/common_macros.h"
#include "esp_intr_alloc.h"
#include "hal/gpio_hal.h"
@ -37,8 +38,6 @@
#include "xtensa/xtensa_api.h"
#endif
#include "esp_idf_api/gpio.h"
#include "irq_arch.h"
#if MODULE_PERIPH_GPIO_IRQ
@ -68,7 +67,7 @@ int gpio_ll_irq(gpio_port_t port, uint8_t pin, gpio_irq_trig_t trig,
/* install GPIO ISR of ESP-IDF if not yet done */
if (!gpio_isr_service_installed &&
esp_idf_gpio_install_isr_service(ESP_INTR_FLAG_LEVEL1) != ESP_OK) {
gpio_install_isr_service(ESP_INTR_FLAG_LEVEL1) != ESP_OK) {
return -1;
}
gpio_isr_service_installed = true;
@ -94,12 +93,12 @@ int gpio_ll_irq(gpio_port_t port, uint8_t pin, gpio_irq_trig_t trig,
default:
type = GPIO_INTR_DISABLE;
}
if (esp_idf_gpio_set_intr_type(gpio, type) != ESP_OK) {
if (gpio_set_intr_type(gpio, type) != ESP_OK) {
return -1;
}
/* add interrupt handler for the pin */
if (esp_idf_gpio_isr_handler_add(gpio, cb, arg) != ESP_OK) {
if (gpio_isr_handler_add(gpio, cb, arg) != ESP_OK) {
return -1;
}
@ -118,7 +117,7 @@ void gpio_ll_irq_mask(gpio_port_t port, uint8_t pin)
DEBUG("%s gpio=%u port=%u pin=%u\n",
__func__, gpio, (unsigned)gpio_port_num(port), pin);
if (esp_idf_gpio_intr_disable(gpio) == ESP_OK) {
if (gpio_intr_disable(gpio) == ESP_OK) {
gpio_int_enabled_table[gpio] = false;
}
}
@ -130,7 +129,7 @@ void gpio_ll_irq_unmask(gpio_port_t port, uint8_t pin)
DEBUG("%s gpio=%u port=%u pin=%u\n",
__func__, gpio, port, pin);
if (esp_idf_gpio_intr_enable(gpio) == ESP_OK) {
if (gpio_intr_enable(gpio) == ESP_OK) {
gpio_int_enabled_table[gpio] = true;
}
}
@ -151,7 +150,7 @@ void gpio_ll_irq_unmask_and_clear(gpio_port_t port, uint8_t pin)
*status_w1tc = BIT(pin);
if (esp_idf_gpio_intr_enable(gpio) == ESP_OK) {
if (gpio_intr_enable(gpio) == ESP_OK) {
gpio_int_enabled_table[gpio] = true;
}
}

36
cpu/esp32/periph/hwrng.c
View File

@ -25,25 +25,15 @@
#include "bootloader_random.h"
#include "esp_random.h"
#include "soc/wdev_reg.h"
#define RNG_DATA_REG (*(volatile uint32_t *)RNG_DATA_REG_ADDR)
void hwrng_init(void)
{
if (!IS_USED(MODULE_WIFI_ANY)) {
/*
* The hardware RNG generates random numbers uses the noise in the
* RF system of the WiFi or the BT interface as entropy source.
* If both are disabled, the random number generator just returns
* pseudo-random numbers.
* However, the bootloader use an internal non-RF entropy source,
* the internal reference voltage noise. This can be re-enabled
* after startup as entropy source for applications that don't
* use the WiFi or the BT interface.
*/
bootloader_random_enable();
}
/* If the ADC SAR is used, the Bootloader RNG must not be enabled before
* the random numbers are actually required. The reason is that the
* Bootloader RNG uses the noise of the ADC SAR reference voltage as
* a non-RF entropy source. The calibration of the ADC SAR does not
* work correctly in this case. Therefore, the Bootloader RNG is only
* enabled if random numbers are really required. */
}
/**
@ -56,10 +46,22 @@ void hwrng_init(void)
*/
void hwrng_read(void *buf, unsigned int num)
{
if (!IS_USED(MODULE_ESP_WIFI_ANY) && !IS_USED(MODULE_ESP_BLE)) {
/* enable the Bootloader RNG if WiFi and BT are not used */
bootloader_random_enable();
}
esp_fill_random(buf, num);
if (!IS_USED(MODULE_ESP_WIFI_ANY) && !IS_USED(MODULE_ESP_BLE)) {
/* disable the Bootloader RNG to ensure that ADC SAR calibration works */
bootloader_random_disable();
}
}
uint32_t hwrand(void)
{
return esp_random();
uint32_t rand;
hwrng_read(&rand, 4);
return rand;
}

272
cpu/esp32/periph/i2c_hw.c
View File

@ -40,19 +40,27 @@
#include "mutex.h"
#include "periph_conf.h"
#include "periph/i2c.h"
#include "time_units.h"
#include "ztimer.h"
#include "esp_attr.h"
#include "driver/i2c.h"
#include "esp_clk_tree.h"
#include "esp_cpu.h"
#include "esp_driver_i2c/i2c_private.h"
#include "esp_rom_gpio.h"
#include "esp_rom_sys.h"
#include "hal/i2c_hal.h"
#include "hal/interrupt_controller_types.h"
#include "hal/interrupt_controller_ll.h"
#include "rom/ets_sys.h"
#include "soc/clk_tree_defs.h"
#include "soc/i2c_reg.h"
#define ENABLE_DEBUG 0
#include "debug.h"
/* typical values according to the ESP-IDF doc */
#define I2C_GLITCH_IGNORE_CNT (7)
#define I2C_CLR_BUS_TIMEOUT_MS (50)
/* Ensure that the I2Cn_* symbols define I2C_DEV(n) */
#if !defined(I2C0_SPEED) && defined(I2C1_SPEED)
#error "I2C_DEV(1) is used but I2C_DEV(0) is not defined"
@ -97,9 +105,6 @@ static _i2c_bus_t _i2c_bus[I2C_NUMOF] = {
#endif
};
/* functions used from ESP-IDF driver that are not exposed in API */
extern esp_err_t i2c_hw_fsm_reset(i2c_port_t i2c_num);
/* forward declaration of internal functions */
static void _i2c_start_cmd(i2c_t dev);
static void _i2c_stop_cmd(i2c_t dev);
@ -110,6 +115,11 @@ static void _i2c_transfer(i2c_t dev);
static void _i2c_intr_handler(void *arg);
static int _i2c_status_to_errno(i2c_t dev);
static void _i2c_configure_gpios(i2c_t dev);
static void _i2c_reset_and_configure(i2c_t dev);
static void _i2c_reset_fsm(i2c_t dev);
static void _i2c_clear_bus(i2c_t dev);
void i2c_init(i2c_t dev)
{
_Static_assert(I2C_NUMOF <= I2C_NUMOF_MAX, "Too many I2C devices defined");
@ -140,66 +150,43 @@ void i2c_init(i2c_t dev)
i2c_acquire(dev);
i2c_config_t cfg = {};
cfg.mode = I2C_MODE_MASTER;
cfg.sda_io_num = i2c_config[dev].sda;
cfg.scl_io_num = i2c_config[dev].scl;
cfg.sda_pullup_en = i2c_config[dev].sda_pullup;
cfg.scl_pullup_en = i2c_config[dev].scl_pullup;
#if defined(SOC_I2C_SUPPORT_RTC) && !defined(CPU_FAM_ESP32S3)
cfg.clk_flags = I2C_SCLK_SRC_FLAG_LIGHT_SLEEP;
#endif
uint32_t clk_speed;
switch (i2c_config[dev].speed) {
case I2C_SPEED_LOW:
cfg.master.clk_speed = 10 * KHZ(1);
clk_speed = 10 * KHZ(1);
break;
case I2C_SPEED_NORMAL:
cfg.master.clk_speed = 100 * KHZ(1);
clk_speed = 100 * KHZ(1);
break;
case I2C_SPEED_FAST:
cfg.master.clk_speed = 400 * KHZ(1);
clk_speed = 400 * KHZ(1);
break;
case I2C_SPEED_FAST_PLUS:
cfg.master.clk_speed = 1000 * KHZ(1);
clk_speed = 1000 * KHZ(1);
break;
case I2C_SPEED_HIGH:
cfg.master.clk_speed = 3400 * KHZ(1);
clk_speed = 3400 * KHZ(1);
break;
default:
LOG_TAG_ERROR("i2c", "Invalid speed value in %s\n", __func__);
assert(0);
}
_i2c_bus[dev].clk_freq = cfg.master.clk_speed;
_i2c_bus[dev].clk_freq = clk_speed;
/* configures the GPIOs, sets the bus timing and enables the periphery */
i2c_param_config(dev, &cfg);
/* configures the GPIOs */
_i2c_configure_gpios(dev);
#if defined(SOC_I2C_SUPPORT_APB)
/* If I2C clock is derived from APB clock, the bus timing parameters
* have to be corrected if the APB clock is less than 80 MHz */
extern uint32_t rtc_clk_apb_freq_get(void);
uint32_t apb_clk = rtc_clk_apb_freq_get();
if (apb_clk < MHZ(80)) {
i2c_clk_cal_t clk_cfg;
i2c_ll_cal_bus_clk(apb_clk, cfg.master.clk_speed, &clk_cfg);
i2c_ll_set_bus_timing(_i2c_hw[dev].dev, &clk_cfg);
}
#endif
/* store the usage type in GPIO table */
gpio_set_pin_usage(i2c_config[dev].scl, _I2C);
gpio_set_pin_usage(i2c_config[dev].sda, _I2C);
/* enable clocks, set the bus timing and enable the periphery */
_i2c_reset_and_configure(dev);
/* route all I2C interrupt sources to same the CPU interrupt */
intr_matrix_set(PRO_CPU_NUM, i2c_periph_signal[dev].irq, CPU_INUM_I2C);
/* set interrupt handler and enable the CPU interrupt */
intr_cntrl_ll_set_int_handler(CPU_INUM_I2C, _i2c_intr_handler, NULL);
intr_cntrl_ll_enable_interrupts(BIT(CPU_INUM_I2C));
esp_cpu_intr_set_handler(CPU_INUM_I2C, _i2c_intr_handler, NULL);
esp_cpu_intr_enable(BIT(CPU_INUM_I2C));
i2c_release(dev);
}
@ -235,8 +222,8 @@ int i2c_read_bytes(i2c_t dev, uint16_t addr, void *data, size_t len, uint8_t fla
_i2c_bus[dev].cmd = 0;
/* reset TX/RX FIFO queue */
i2c_hal_txfifo_rst(&_i2c_hw[dev]);
i2c_hal_rxfifo_rst(&_i2c_hw[dev]);
i2c_ll_txfifo_rst(_i2c_hw[dev].dev);
i2c_ll_rxfifo_rst(_i2c_hw[dev].dev);
/* if I2C_NOSTART is not set, START condition and ADDR is used */
if (!(flags & I2C_NOSTART)) {
@ -276,10 +263,10 @@ int i2c_read_bytes(i2c_t dev, uint16_t addr, void *data, size_t len, uint8_t fla
}
/* if transfer was successful, fetch the data from I2C RAM */
i2c_hal_read_rxfifo(&_i2c_hw[dev], data + off, len);
i2c_ll_read_rxfifo(_i2c_hw[dev].dev, data + off, len);
/* reset RX FIFO queue */
i2c_hal_rxfifo_rst(&_i2c_hw[dev]);
i2c_ll_rxfifo_rst(_i2c_hw[dev].dev);
len -= SOC_I2C_FIFO_LEN;
off += SOC_I2C_FIFO_LEN;
@ -307,7 +294,7 @@ int i2c_read_bytes(i2c_t dev, uint16_t addr, void *data, size_t len, uint8_t fla
}
/* fetch the data from RX FIFO */
i2c_hal_read_rxfifo(&_i2c_hw[dev], data + off, len);
i2c_ll_read_rxfifo(_i2c_hw[dev].dev, data + off, len);
/* return 0 on success */
return 0;
@ -328,7 +315,7 @@ int i2c_write_bytes(i2c_t dev, uint16_t addr, const void *data, size_t len, uint
_i2c_bus[dev].cmd = 0;
/* reset TX FIFO queue */
i2c_hal_txfifo_rst(&_i2c_hw[dev]);
i2c_ll_txfifo_rst(_i2c_hw[dev].dev);
/* if I2C_NOSTART is not set, START condition and ADDR is used */
if (!(flags & I2C_NOSTART)) {
@ -358,7 +345,7 @@ int i2c_write_bytes(i2c_t dev, uint16_t addr, const void *data, size_t len, uint
uint32_t tx_fifo_free;
/* get available TX FIFO space */
i2c_hal_get_txfifo_cnt(&_i2c_hw[dev], &tx_fifo_free);
i2c_ll_get_txfifo_len(_i2c_hw[dev].dev, &tx_fifo_free);
/* if len > SOC_I2C_FIFO_LEN write SOC_I2C_FIFO_LEN bytes at a time */
while (len > tx_fifo_free) {
@ -377,10 +364,10 @@ int i2c_write_bytes(i2c_t dev, uint16_t addr, const void *data, size_t len, uint
off += tx_fifo_free;
/* reset TX FIFO queue */
i2c_hal_txfifo_rst(&_i2c_hw[dev]);
i2c_ll_txfifo_rst(_i2c_hw[dev].dev);
/* update available TX FIFO space */
i2c_hal_get_txfifo_cnt(&_i2c_hw[dev], &tx_fifo_free);
i2c_ll_get_txfifo_len(_i2c_hw[dev].dev, &tx_fifo_free);
}
/* write remaining data bytes command */
@ -439,7 +426,7 @@ static int _i2c_status_to_errno(i2c_t dev)
*/
uint32_t cnt;
i2c_hal_get_txfifo_cnt(&_i2c_hw[dev], &cnt);
i2c_ll_get_txfifo_len(_i2c_hw[dev].dev, &cnt);
return ((SOC_I2C_FIFO_LEN - cnt) >= _i2c_bus[dev].len) ? -ENXIO : -EIO;
}
else {
@ -455,7 +442,7 @@ static int _i2c_status_to_errno(i2c_t dev)
if (_i2c_bus[dev].status & I2C_TIME_OUT_INT_ENA_M) {
LOG_TAG_DEBUG("i2c", "bus timeout dev=%u\n", dev);
i2c_hw_fsm_reset(dev);
_i2c_reset_fsm(dev);
return -ETIMEDOUT;
}
@ -467,8 +454,8 @@ static void _i2c_start_cmd(i2c_t dev)
DEBUG ("%s\n", __func__);
/* place START condition command in command queue */
i2c_hw_cmd_t cmd = { .op_code = I2C_LL_CMD_RESTART };
i2c_hal_write_cmd_reg(&_i2c_hw[dev], cmd, _i2c_bus[dev].cmd);
i2c_ll_hw_cmd_t cmd = { .op_code = I2C_LL_CMD_RESTART };
i2c_ll_master_write_cmd_reg(_i2c_hw[dev].dev, cmd, _i2c_bus[dev].cmd);
/* increment the command counter */
_i2c_bus[dev].cmd++;
@ -479,8 +466,8 @@ static void _i2c_stop_cmd(i2c_t dev)
DEBUG ("%s\n", __func__);
/* place STOP condition command in command queue */
i2c_hw_cmd_t cmd = { .op_code = I2C_LL_CMD_STOP };
i2c_hal_write_cmd_reg(&_i2c_hw[dev], cmd, _i2c_bus[dev].cmd);
i2c_ll_hw_cmd_t cmd = { .op_code = I2C_LL_CMD_STOP };
i2c_ll_master_write_cmd_reg(_i2c_hw[dev].dev, cmd, _i2c_bus[dev].cmd);
/* increment the command counter */
_i2c_bus[dev].cmd++;
@ -491,8 +478,8 @@ static void _i2c_end_cmd(i2c_t dev)
DEBUG ("%s\n", __func__);
/* place END command for continues data transmission in command queue */
i2c_hw_cmd_t cmd = { .op_code = I2C_LL_CMD_END };
i2c_hal_write_cmd_reg(&_i2c_hw[dev], cmd, _i2c_bus[dev].cmd);
i2c_ll_hw_cmd_t cmd = { .op_code = I2C_LL_CMD_END };
i2c_ll_master_write_cmd_reg(_i2c_hw[dev].dev, cmd, _i2c_bus[dev].cmd);
/* increment the command counter */
_i2c_bus[dev].cmd++;
@ -509,15 +496,15 @@ static void _i2c_write_cmd(i2c_t dev, const uint8_t* data, uint8_t len)
}
/* store the data in TX FIFO */
i2c_hal_write_txfifo(&_i2c_hw[dev], (uint8_t *)data, len);
i2c_ll_write_txfifo(_i2c_hw[dev].dev, (uint8_t *)data, len);
/* place WRITE command for multiple bytes in command queue */
i2c_hw_cmd_t cmd = { .op_code = I2C_LL_CMD_WRITE,
.byte_num = len,
.ack_en = 1,
.ack_exp = 0,
.ack_val = 0 };
i2c_hal_write_cmd_reg(&_i2c_hw[dev], cmd, _i2c_bus[dev].cmd);
i2c_ll_hw_cmd_t cmd = { .op_code = I2C_LL_CMD_WRITE,
.byte_num = len,
.ack_en = 1,
.ack_exp = 0,
.ack_val = 0 };
i2c_ll_master_write_cmd_reg(_i2c_hw[dev].dev, cmd, _i2c_bus[dev].cmd);
/* increment the command counter */
_i2c_bus[dev].cmd++;
@ -536,24 +523,24 @@ static void _i2c_read_cmd(i2c_t dev, uint8_t len, bool last)
if (len > 1)
{
/* place READ command for len-1 bytes with positive ack in command queue*/
i2c_hw_cmd_t cmd = { .op_code = I2C_LL_CMD_READ,
.byte_num = len-1,
.ack_en = 0,
.ack_exp = 0,
.ack_val = 0 };
i2c_hal_write_cmd_reg(&_i2c_hw[dev], cmd, _i2c_bus[dev].cmd);
i2c_ll_hw_cmd_t cmd = { .op_code = I2C_LL_CMD_READ,
.byte_num = len-1,
.ack_en = 0,
.ack_exp = 0,
.ack_val = 0 };
i2c_ll_master_write_cmd_reg(_i2c_hw[dev].dev, cmd, _i2c_bus[dev].cmd);
/* increment the command counter */
_i2c_bus[dev].cmd++;
}
/* place READ command for last byte with negative ack in last segment in command queue*/
i2c_hw_cmd_t cmd = { .op_code = I2C_LL_CMD_READ,
.byte_num = 1,
.ack_en = 0,
.ack_exp = 0,
.ack_val = last ? 1 : 0 };
i2c_hal_write_cmd_reg(&_i2c_hw[dev], cmd, _i2c_bus[dev].cmd);
i2c_ll_hw_cmd_t cmd = { .op_code = I2C_LL_CMD_READ,
.byte_num = 1,
.ack_en = 0,
.ack_exp = 0,
.ack_val = last ? 1 : 0 };
i2c_ll_master_write_cmd_reg(_i2c_hw[dev].dev, cmd, _i2c_bus[dev].cmd);
/* increment the command counter */
_i2c_bus[dev].cmd++;
@ -571,7 +558,7 @@ void _i2c_transfer_timeout(void *arg)
i2c_t dev = (i2c_t)(uintptr_t)arg;
/* reset the hardware if I2C got stuck */
i2c_hw_fsm_reset(dev);
_i2c_reset_fsm(dev);
/* set result to timeout */
_i2c_bus[dev].status = I2C_TIME_OUT_INT_ENA_M;
@ -586,8 +573,8 @@ static void _i2c_transfer(i2c_t dev)
DEBUG("%s cmd=%d\n", __func__, _i2c_bus[dev].cmd);
/* disable and enable all transmission interrupts and clear current status */
i2c_hal_clr_intsts_mask(&_i2c_hw[dev], I2C_LL_MASTER_INT);
i2c_hal_enable_intr_mask(&_i2c_hw[dev], I2C_LL_MASTER_INT);
i2c_ll_clear_intr_mask(_i2c_hw[dev].dev, I2C_LL_MASTER_INT);
i2c_ll_enable_intr_mask(_i2c_hw[dev].dev, I2C_LL_MASTER_INT);
/* set a timer for the case the I2C hardware gets stuck */
#if defined(MODULE_ZTIMER_MSEC)
@ -600,8 +587,8 @@ static void _i2c_transfer(i2c_t dev)
/* start the execution of commands in command pipeline */
_i2c_bus[dev].status = 0;
i2c_hal_update_config(&_i2c_hw[dev]);
i2c_hal_trans_start(&_i2c_hw[dev]);
i2c_ll_update(_i2c_hw[dev].dev);
i2c_ll_start_trans(_i2c_hw[dev].dev);
/* wait for transfer results and remove timeout timer*/
mutex_lock(&_i2c_bus[dev].cmd_lock);
@ -627,13 +614,14 @@ static void IRAM_ATTR _i2c_intr_handler(void *arg)
/* all I2C peripheral interrupt sources are routed to the same interrupt,
so we have to use the status register to distinguish interruptees */
for (unsigned dev = 0; dev < I2C_NUMOF; dev++) {
uint32_t mask = i2c_ll_get_intsts_mask(_i2c_hw[dev].dev);
uint32_t mask;
i2c_ll_get_intr_mask(_i2c_hw[dev].dev, &mask);
/* test for transfer related interrupts */
if (mask) {
_i2c_bus[dev].status = mask;
/* disable all interrupts and clear pending interrupts */
i2c_hal_clr_intsts_mask(&_i2c_hw[dev], I2C_LL_MASTER_INT);
i2c_hal_disable_intr_mask(&_i2c_hw[dev], I2C_LL_MASTER_INT);
i2c_ll_clear_intr_mask(_i2c_hw[dev].dev, I2C_LL_MASTER_INT);
i2c_ll_enable_intr_mask(_i2c_hw[dev].dev, I2C_LL_MASTER_INT);
/* wake up the thread that is waiting for the results */
mutex_unlock(&_i2c_bus[dev].cmd_lock);
@ -655,3 +643,115 @@ void i2c_print_config(void)
LOG_TAG_INFO("i2c", "no I2C devices\n");
}
}
static void _i2c_configure_gpios(i2c_t dev)
{
gpio_init(i2c_config[dev].scl, i2c_config[dev].scl_pullup ? GPIO_IN_OD_PU : GPIO_IN_OD_PU);
gpio_set(i2c_config[dev].scl);
esp_rom_gpio_connect_out_signal(i2c_config[dev].scl, i2c_periph_signal[dev].scl_out_sig, 0, 0);
esp_rom_gpio_connect_in_signal(i2c_config[dev].scl, i2c_periph_signal[dev].scl_in_sig, 0);
gpio_init(i2c_config[dev].sda, i2c_config[dev].sda_pullup ? GPIO_IN_OD_PU : GPIO_IN_OD_PU);
gpio_set(i2c_config[dev].sda);
esp_rom_gpio_connect_out_signal(i2c_config[dev].sda, i2c_periph_signal[dev].sda_out_sig, 0, 0);
esp_rom_gpio_connect_in_signal(i2c_config[dev].sda, i2c_periph_signal[dev].sda_in_sig, 0);
/* store the usage type in GPIO table */
gpio_set_pin_usage(i2c_config[dev].scl, _I2C);
gpio_set_pin_usage(i2c_config[dev].sda, _I2C);
}
static void _i2c_reset_and_configure(i2c_t dev)
{
i2c_ll_enable_controller_clock(_i2c_hw[dev].dev, true);
I2C_RCC_ATOMIC() {
i2c_ll_enable_bus_clock(dev, true);
i2c_ll_reset_register(dev);
}
i2c_ll_master_init(_i2c_hw[dev].dev);
i2c_ll_set_data_mode(_i2c_hw[dev].dev, I2C_DATA_MODE_MSB_FIRST, I2C_DATA_MODE_MSB_FIRST);
i2c_ll_txfifo_rst(_i2c_hw[dev].dev);
i2c_ll_rxfifo_rst(_i2c_hw[dev].dev);
soc_module_clk_t clk_src = (soc_module_clk_t)I2C_CLK_SRC_DEFAULT;
uint32_t clk_src_hz;
esp_clk_tree_src_get_freq_hz(clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, &clk_src_hz);
i2c_hal_clk_config_t clk_cfg;
i2c_ll_master_cal_bus_clk(clk_src_hz, _i2c_bus[dev].clk_freq, &clk_cfg);
i2c_ll_master_set_bus_timing(_i2c_hw[dev].dev, &clk_cfg);
i2c_ll_master_set_filter(_i2c_hw[dev].dev, I2C_GLITCH_IGNORE_CNT);
i2c_ll_set_source_clk(_i2c_hw[dev].dev, (soc_periph_i2c_clk_src_t)clk_src);
i2c_ll_update(_i2c_hw[dev].dev);
/* clear pending interrupts */
i2c_ll_clear_intr_mask(_i2c_hw[dev].dev, I2C_LL_MASTER_EVENT_INTR);
}
static void _i2c_reset_fsm(i2c_t dev)
{
#if SOC_I2C_SUPPORT_HW_FSM_RST
i2c_ll_master_fsm_rst(_i2c_hw[dev].dev);
_i2c_clear_bus(dev);
#else
_i2c_clear_bus(dev);
_i2c_reset_and_configure(dev);
#endif
}
static void _i2c_clear_bus(i2c_t dev)
{
#if SOC_I2C_SUPPORT_HW_CLR_BUS
i2c_ll_master_clr_bus(_i2c_hw[dev].dev, I2C_LL_RESET_SLV_SCL_PULSE_NUM_DEFAULT, true);
uint32_t timeout = system_get_time_ms() + I2C_CLR_BUS_TIMEOUT_MS;
while (i2c_ll_master_is_bus_clear_done(_i2c_hw[dev].dev) &&
(timeout > system_get_time_ms())) { }
if (timeout < system_get_time_ms()) {
LOG_TAG_ERROR("i2c", "clear bus failed\n");
}
i2c_ll_master_clr_bus(_i2c_hw[dev].dev, 0, false);
i2c_ll_update(_i2c_hw[dev].dev);
#else
gpio_set_pin_usage(i2c_config[dev].scl, _GPIO);
gpio_set_pin_usage(i2c_config[dev].sda, _GPIO);
gpio_init(i2c_config[dev].scl, i2c_config[dev].scl_pullup ? GPIO_IN_OD_PU : GPIO_IN_OD_PU);
gpio_init(i2c_config[dev].sda, i2c_config[dev].sda_pullup ? GPIO_IN_OD_PU : GPIO_IN_OD_PU);
gpio_set(i2c_config[dev].scl);
gpio_set(i2c_config[dev].sda);
/*
* If SDA is low it is driven by the slave, wait until SDA goes high, at
* maximum 9 clock cycles in standard mode at 100 kHz including the ACK bit.
*/
uint32_t half_cycle = 5;
int count = 9;
while (!gpio_read(i2c_config[dev].sda) && count--) {
gpio_clear(i2c_config[dev].scl);
esp_rom_delay_us(half_cycle);
gpio_set(i2c_config[dev].scl);
esp_rom_delay_us(half_cycle);
}
/* generate a STOP condition */
gpio_clear(i2c_config[dev].scl);
esp_rom_delay_us(half_cycle);
gpio_clear(i2c_config[dev].sda);
esp_rom_delay_us(half_cycle);
gpio_set(i2c_config[dev].scl);
esp_rom_delay_us(half_cycle);
gpio_set(i2c_config[dev].sda);
/* reconfigure gpios */
_i2c_configure_gpios(dev);
#endif
}

30
cpu/esp32/periph/pm.c
View File

@ -30,14 +30,14 @@
#include "periph/uart.h"
/* ESP-IDF headers */
#include "driver/gpio.h"
#include "driver/uart.h"
#include "esp_sleep.h"
#include "rom/rtc.h"
#include "rom/uart.h"
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "esp_idf_api/uart.h"
#define ENABLE_DEBUG 0
#include "debug.h"
@ -85,8 +85,10 @@ static inline void pm_set_lowest_normal(void)
void IRAM_ATTR pm_off(void)
{
/* disable remaining power domains */
#if ESP_PD_DOMAIN_RTC_SLOW_MEM && ESP_PD_DOMAIN_RTC_FAST_MEM
esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_SLOW_MEM, ESP_PD_OPTION_OFF);
esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_FAST_MEM, ESP_PD_OPTION_OFF);
#endif
/* enter hibernate mode without any enabled wake-up sources */
esp_sleep_disable_wakeup_source(ESP_SLEEP_WAKEUP_ALL);
@ -137,6 +139,7 @@ void pm_set(unsigned mode)
/* flush stdout */
fflush(stdout);
#if SOC_PM_SUPPORT_RTC_SLOW_MEM_PD
/* Labels for RTC slow memory that are defined in the linker script */
extern int _rtc_bss_rtc_start;
extern int _rtc_bss_rtc_end;
@ -151,6 +154,7 @@ void pm_set(unsigned mode)
if (&_rtc_bss_rtc_end > &_rtc_bss_rtc_start) {
esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_SLOW_MEM, ESP_PD_OPTION_ON);
}
#endif
/* first disable all wake-up sources */
esp_sleep_disable_wakeup_source(ESP_SLEEP_WAKEUP_ALL);
@ -161,15 +165,31 @@ void pm_set(unsigned mode)
/* Prepare GPIOs as wakeup source */
gpio_pm_sleep_enter(mode);
extern esp_err_t esp_sleep_enable_uart_wakeup(int uart);
#if (ESP_PM_WUP_UART0 > 2)
esp_idf_uart_set_wakeup_threshold(UART_DEV(0), ESP_PM_WUP_UART0);
_Static_assert(UART_NUMOF > 0, "UART_DEV(0) is not defined");
#if CPU_FAM_ESP32
/* For ESP32, UART RxD has to be configured for direct IO using IOMUX */
const uart_periph_sig_t *sig = &uart_periph_signal[UART_DEV(0)].pins[SOC_UART_RX_PIN_IDX];
gpio_iomux_out(UART0_RXD, sig->iomux_func, false);
gpio_iomux_in(UART0_RXD, sig->signal);
#endif
uart_set_wakeup_threshold(UART_DEV(0), ESP_PM_WUP_UART0);
esp_sleep_enable_uart_wakeup(0);
#endif
#if (ESP_PM_WUP_UART1 > 2)
esp_idf_uart_set_wakeup_threshold(UART_DEV(1), ESP_PM_WUP_UART1);
_Static_assert(UART_NUMOF > 1, "UART_DEV(1) is not defined");
#if CPU_FAM_ESP32
/* For ESP32, UART RxD has to be configured for direct IO using IOMUX */
const uart_periph_sig_t *sig = &uart_periph_signal[UART_DEV(0)].pins[SOC_UART_RX_PIN_IDX];
gpio_iomux_out(UART1_RXD, sig->iomux_func, false);
gpio_iomux_in(UART1_RXD, sig->signal);
#endif
uart_set_wakeup_threshold(UART_DEV(1), ESP_PM_WUP_UART1);
esp_sleep_enable_uart_wakeup(1);
#endif
#if MODULE_STDIO_UART
uart_wait_tx_idle_polling(CONFIG_ESP_CONSOLE_UART_NUM);
#endif
if (mode == ESP_PM_DEEP_SLEEP) {
esp_deep_sleep_start();

16
cpu/esp32/periph/pwm.c
View File

@ -28,8 +28,9 @@
#include "periph/pwm.h"
#include "periph/gpio.h"
#include "driver/periph_ctrl.h"
#include "esp_cpu.h"
#include "esp_common.h"
#include "esp_private/periph_ctrl.h"
#include "esp_rom_gpio.h"
#include "hal/ledc_hal.h"
#include "soc/ledc_struct.h"
@ -53,7 +54,7 @@
#define SOC_LEDC_CLK_DIV_INT_BIT_NUM 10 /* integral part of CLK divider */
#define SOC_LEDC_CLK_DIV_FRAC_BIT_NUM 8 /* fractional part of CLK divider */
#define PWM_HW_RES_MAX ((uint32_t)1 << SOC_LEDC_TIMER_BIT_WIDE_NUM)
#define PWM_HW_RES_MAX ((uint32_t)1 << SOC_LEDC_TIMER_BIT_WIDTH)
#define PWM_HW_RES_MIN ((uint32_t)1 << 1)
#define _DEV _pwm_dev[pwm] /* shortcut for PWM device descriptor */
@ -121,7 +122,7 @@ uint32_t pwm_init(pwm_t pwm, pwm_mode_t mode, uint32_t freq, uint16_t res)
* next power of two, which covers the desired resolution
*/
ledc_timer_bit_t hw_res_bit = bitarithm_msb(res - 1);
if (hw_res_bit < SOC_LEDC_TIMER_BIT_WIDE_NUM) {
if (hw_res_bit < SOC_LEDC_TIMER_BIT_WIDTH) {
hw_res_bit++;
}
@ -129,7 +130,7 @@ uint32_t pwm_init(pwm_t pwm, pwm_mode_t mode, uint32_t freq, uint16_t res)
uint32_t hw_ticks_max = rtc_clk_apb_freq_get();
uint32_t hw_ticks_min = hw_ticks_max / (1 << SOC_LEDC_CLK_DIV_INT_BIT_NUM);
uint32_t hw_freq_min = hw_ticks_min / (1 << SOC_LEDC_TIMER_BIT_WIDE_NUM) + 1;
uint32_t hw_freq_min = hw_ticks_min / (1 << SOC_LEDC_TIMER_BIT_WIDTH) + 1;
if (freq < hw_freq_min) {
LOG_TAG_ERROR("pwm", "Frequency of %"PRIu32" Hz is too less, minimum "
@ -255,7 +256,9 @@ void pwm_poweron(pwm_t pwm)
periph_module_enable(_CFG.module);
ledc_hal_init(&_DEV.hw, _CFG.group);
ledc_hal_set_slow_clk_sel(&_DEV.hw, LEDC_SLOW_CLK_APB);
#if SOC_LEDC_HAS_TIMER_SPECIFIC_MUX
ledc_hal_set_clock_source(&_DEV.hw, _CFG.timer, LEDC_APB_CLK);
#endif
/* update the timer according to determined parameters */
ledc_hal_set_clock_divider(&_DEV.hw, _CFG.timer, _DEV.hw_clk_div);
@ -266,10 +269,7 @@ void pwm_poweron(pwm_t pwm)
critical_enter();
for (unsigned i = 0; i < _CFG.ch_numof; i++) {
/* static configuration of the channel, no fading */
ledc_hal_set_duty_direction(&_DEV.hw, _DEV.ch[i].ch, 1);
ledc_hal_set_duty_num(&_DEV.hw, _DEV.ch[i].ch, 1);
ledc_hal_set_duty_cycle(&_DEV.hw, _DEV.ch[i].ch, 1);
ledc_hal_set_duty_scale(&_DEV.hw, _DEV.ch[i].ch, 0);
ledc_hal_set_fade_param(&_DEV.hw, _DEV.ch[i].ch, 0, 1, 1, 0, 1);
ledc_hal_set_fade_end_intr(&_DEV.hw, _DEV.ch[i].ch, 0);
/* bind the channel to the timer and disable the output for now */

43
cpu/esp32/periph/rtt.c
View File

@ -59,6 +59,7 @@ extern uint32_t rtc_clk_slow_freq_get_hz(void);
void rtt_restore_counter(bool sys_time);
static void _rtt_update_hw_alarm(void);
static void _rtt_isr(void *arg);
static inline uint32_t _rtt_get_counter(void);
/* forward declarations of driver functions */
uint64_t _rtc_get_counter(void);
@ -82,10 +83,10 @@ void rtt_init(void)
}
}
DEBUG("%s rtt_offset=%" PRIu32 " @rtc=%" PRIu64
" rtc_active=%d @sys_time=%" PRIi64 "\n", __func__,
_rtt_offset, _rtc_get_counter(),
(_rtt_hw == &_rtt_hw_sys_driver) ? 1 : 0, system_get_time_64());
DEBUG("%s rtt_offset=%" PRIu32 " @rtc=%" PRIu32
" rtc_active=%d @sys_time=%" PRIu32 "\n", __func__,
_rtt_offset, (uint32_t)_rtc_get_counter(),
(_rtt_hw == &_rtt_hw_sys_driver) ? 1 : 0, (uint32_t)system_get_time_64());
/* init the hardware counter if necessary */
_rtt_hw->init();
@ -132,8 +133,8 @@ void rtt_clear_overflow_cb(void)
uint32_t rtt_get_counter(void)
{
/* we use only the lower 32 bit of the 48-bit RTC counter */
uint32_t counter = _rtt_hw->get_counter() + _rtt_offset;
DEBUG("%s counter=%" PRIu32 " @sys_time=%" PRIu32" \n",
uint32_t counter = _rtt_get_counter();
DEBUG("%s counter=%" PRIu32 " @sys_time=%" PRIu32 "\n",
__func__, counter, system_get_time());
return counter;
}
@ -143,20 +144,22 @@ void rtt_set_counter(uint32_t counter)
uint32_t _rtt_current = _rtt_hw->get_counter();
_rtt_offset = counter - _rtt_current;
DEBUG("%s set=%" PRIu32 " rtt_offset=%" PRIu32 " @rtt=%" PRIu32 "\n",
__func__, counter, _rtt_offset, _rtt_current);
DEBUG("%s set=%" PRIu32 " rtt_offset=%" PRIu32 " @rtt=%" PRIu32
" @sys_time=%" PRIu32 "\n",
__func__, counter, _rtt_offset, _rtt_current, system_get_time());
_rtt_update_hw_alarm();
}
void rtt_set_alarm(uint32_t alarm, rtt_cb_t cb, void *arg)
{
uint32_t counter = rtt_get_counter();
uint32_t counter = _rtt_get_counter();
rtt_counter.alarm = alarm;
rtt_counter.alarm_cb = cb;
rtt_counter.alarm_arg = arg;
DEBUG("%s alarm=%" PRIu32 " @rtt=%" PRIu32 "\n", __func__, alarm, counter);
DEBUG("%s alarm=%" PRIu32 " @rtt=%" PRIu32 " @sys_time=%" PRIu32 "\n",
__func__, alarm, counter, system_get_time());
_rtt_update_hw_alarm();
}
@ -168,7 +171,8 @@ void rtt_clear_alarm(void)
rtt_counter.alarm_cb = NULL;
rtt_counter.alarm_arg = NULL;
DEBUG("%s @rtt=%" PRIu32 "\n", __func__, (uint32_t)_rtt_hw->get_counter());
DEBUG("%s @rtt=%" PRIu32 " @sys_time=%" PRIu32 "\n",
__func__, (uint32_t)_rtt_hw->get_counter(), system_get_time());
_rtt_update_hw_alarm();
}
@ -196,11 +200,11 @@ uint64_t rtt_pm_sleep_enter(unsigned mode)
return 0;
}
uint32_t counter = rtt_get_counter();
uint32_t counter = _rtt_get_counter();
uint64_t t_diff = RTT_TICKS_TO_US(rtt_counter.alarm_active - counter);
DEBUG("%s rtt_alarm=%" PRIu32 " @rtt=%" PRIu32 " t_diff=%llu\n", __func__,
rtt_counter.alarm_active, counter, t_diff);
DEBUG("%s rtt_alarm=%" PRIu32 " @rtt=%" PRIu32 " t_diff=%" PRIu32 "\n", __func__,
rtt_counter.alarm_active, counter, (uint32_t)t_diff);
if (t_diff) {
rtt_counter.wakeup = true;
@ -222,9 +226,14 @@ void rtt_pm_sleep_exit(uint32_t cause)
}
}
static inline uint32_t _rtt_get_counter(void)
{
return _rtt_hw->get_counter() + _rtt_offset;
}
static void _rtt_update_hw_alarm(void)
{
if (rtt_counter.alarm_cb && ((rtt_counter.alarm > rtt_get_counter()) ||
if (rtt_counter.alarm_cb && ((rtt_counter.alarm > _rtt_get_counter()) ||
(rtt_counter.overflow_cb == NULL))) {
/* alarm is the next event if either the alarm is greater than the
current counter value or the overflow callback is not set. */
@ -253,7 +262,7 @@ static void IRAM_ATTR _rtt_isr(void *arg)
if (rtt_counter.wakeup) {
rtt_counter.wakeup = false;
DEBUG("%s wakeup alarm alarm=%" PRIu32 " rtt_alarm=%" PRIu32 " @rtt=%" PRIu32 "\n",
__func__, alarm, rtt_counter.alarm_active, rtt_get_counter());
__func__, alarm, rtt_counter.alarm_active, _rtt_get_counter());
}
if ((alarm == rtt_counter.alarm) && rtt_counter.alarm_cb) {
@ -278,7 +287,7 @@ static void IRAM_ATTR _rtt_isr(void *arg)
}
}
DEBUG("%s next rtt=%" PRIu32 "\n", __func__, rtt_counter.alarm_active);
DEBUG("%s next rtt=%" PRIu32 "\n", __func__, rtt_counter.alarm_active);
}
uint32_t _rtt_hw_to_rtt_counter(uint32_t hw_counter)

27
cpu/esp32/periph/rtt_hw_rtc.c
View File

@ -32,9 +32,8 @@
/* ESP-IDF headers */
#include "esp_attr.h"
#include "esp_cpu.h"
#include "esp_sleep.h"
#include "hal/interrupt_controller_types.h"
#include "hal/interrupt_controller_ll.h"
#include "rom/ets_sys.h"
#include "soc/periph_defs.h"
#include "soc/rtc_cntl_struct.h"
@ -70,7 +69,7 @@ uint64_t _rtc_counter_to_us(uint64_t raw)
{
const uint32_t cal = esp_clk_slowclk_cal_get();
return ((((raw >> 32) * cal) << (32 - RTC_CLK_CAL_FRACT)) + /* high part */
(((raw & 0xffffffff) * cal) >> RTC_CLK_CAL_FRACT)); /* low part */
(((raw & UINT32_MAX) * cal) >> RTC_CLK_CAL_FRACT)); /* low part */
}
static void _rtc_init(void)
@ -83,15 +82,15 @@ static void _rtc_poweron(void)
intr_matrix_set(PRO_CPU_NUM, ETS_RTC_CORE_INTR_SOURCE, CPU_INUM_RTT);
/* set interrupt handler and enable the CPU interrupt */
intr_cntrl_ll_set_int_handler(CPU_INUM_RTT, _rtc_isr, NULL);
intr_cntrl_ll_enable_interrupts(BIT(CPU_INUM_RTT));
esp_cpu_intr_set_handler(CPU_INUM_RTT, _rtc_isr, NULL);
esp_cpu_intr_enable(BIT(CPU_INUM_RTT));
}
static void _rtc_poweroff(void)
{
/* reset interrupt handler and disable the CPU interrupt */
intr_cntrl_ll_disable_interrupts(BIT(CPU_INUM_RTT));
intr_cntrl_ll_set_int_handler(CPU_INUM_RTT, NULL, NULL);
esp_cpu_intr_disable(BIT(CPU_INUM_RTT));
esp_cpu_intr_set_handler(CPU_INUM_RTT, NULL, NULL);
}
uint64_t _rtc_get_counter(void)
@ -123,8 +122,8 @@ static void _rtc_set_alarm(uint32_t alarm, rtt_cb_t cb, void *arg)
uint64_t rtc_alarm = (rtc_counter + rtt_diff) & RTT_HW_COUNTER_MAX;
DEBUG("%s alarm=%" PRIu32 " rtt_diff=%" PRIu32
" rtc_alarm=%" PRIu64 " @rtc=%" PRIu64 "\n",
__func__, alarm, rtt_diff, rtc_alarm, rtc_counter);
" rtc_alarm=%" PRIu32 " @rtc=%" PRIu32 "\n",
__func__, alarm, rtt_diff, (uint32_t)rtc_alarm, (uint32_t)rtc_counter);
/* save the alarm configuration for interrupt handling */
_rtc_alarm.alarm_set = alarm;
@ -132,18 +131,18 @@ static void _rtc_set_alarm(uint32_t alarm, rtt_cb_t cb, void *arg)
_rtc_alarm.alarm_arg = arg;
/* set the timer value */
RTCCNTL.slp_timer0 = rtc_alarm & 0xffffffff;
RTCCNTL.slp_timer0 = rtc_alarm & UINT32_MAX;
RTCCNTL.slp_timer1.slp_val_hi = rtc_alarm >> 32;
DEBUG("%s %08x%08x \n", __func__,
(unsigned)RTCCNTL.slp_timer1.slp_val_hi, (unsigned)RTCCNTL.slp_timer0);
/* enable RTC timer alarm */
RTCCNTL.slp_timer1.main_timer_alarm_en = 1;
/* clear and enable RTC timer interrupt */
RTCCNTL.int_clr.rtc_main_timer = 1;
RTCCNTL.int_ena.rtc_main_timer = 1;
/* enable RTC timer alarm */
RTCCNTL.slp_timer1.main_timer_alarm_en = 1;
}
static void _rtc_clear_alarm(void)
@ -176,8 +175,8 @@ static void IRAM _rtc_isr(void *arg)
RTCCNTL.slp_timer1.main_timer_alarm_en = 0;
/* clear the bit in interrupt enable and status register */
RTCCNTL.int_clr.rtc_main_timer = 0;
RTCCNTL.int_ena.rtc_main_timer = 0;
RTCCNTL.int_clr.rtc_main_timer = 1;
/* save the lower 32 bit of the current counter value */
uint32_t counter = _rtc_get_counter();

66
cpu/esp32/periph/rtt_hw_sys.c
View File

@ -31,12 +31,13 @@
/* ESP-IDF headers */
#include "esp_attr.h"
#include "esp_cpu.h"
#include "esp_sleep.h"
#include "hal/interrupt_controller_types.h"
#include "hal/interrupt_controller_ll.h"
#include "hal/timer_hal.h"
#include "hal/timer_ll.h"
#include "rom/ets_sys.h"
#include "soc/periph_defs.h"
#include "soc/soc.h"
#include "soc/timer_group_struct.h"
#if __xtensa__
@ -46,8 +47,6 @@
#define ENABLE_DEBUG 0
#include "debug.h"
#define TIMER_SYSTEM_INT_MASK BIT(TIMER_SYSTEM_INDEX)
#define SYS_US_TO_TICKS(us) ((((uint64_t)us) << 15) / US_PER_SEC)
#define SYS_TICKS_TO_US(cnt) (((uint64_t)cnt * US_PER_SEC) >> 15)
@ -85,15 +84,15 @@ static void _sys_poweron(void)
intr_matrix_set(PRO_CPU_NUM, TIMER_SYSTEM_INT_SRC, CPU_INUM_RTT);
/* set interrupt handler and enable the CPU interrupt */
intr_cntrl_ll_set_int_handler(CPU_INUM_RTT, _sys_isr, NULL);
intr_cntrl_ll_enable_interrupts(BIT(CPU_INUM_RTT));
esp_cpu_intr_set_handler(CPU_INUM_RTT, _sys_isr, NULL);
esp_cpu_intr_enable(BIT(CPU_INUM_RTT));
}
static void _sys_poweroff(void)
{
/* reset interrupt handler and disable the CPU interrupt */
intr_cntrl_ll_disable_interrupts(BIT(CPU_INUM_RTT));
intr_cntrl_ll_set_int_handler(CPU_INUM_RTT, NULL, NULL);
esp_cpu_intr_disable(BIT(CPU_INUM_RTT));
esp_cpu_intr_set_handler(CPU_INUM_RTT, NULL, NULL);
}
static uint64_t _sys_get_counter(void)
@ -117,33 +116,34 @@ static void _sys_set_alarm(uint32_t alarm, rtt_cb_t cb, void *arg)
uint64_t _sys_alarm_time = _sys_time + _sys_diff;
DEBUG("%s alarm=%" PRIu32 " rtt_diff=%" PRIu32 " "
"sys_diff=%" PRIu64 " sys_alarm=%" PRIu64 " @sys_time=%" PRIu64 "\n", __func__,
alarm, rtt_diff, _sys_diff, _sys_alarm_time, _sys_time);
"sys_diff=%" PRIu32 " sys_alarm=%" PRIu32 " @sys_time=%" PRIu32 "\n", __func__,
alarm, rtt_diff, (uint32_t)_sys_diff, (uint32_t)_sys_alarm_time, (uint32_t)_sys_time);
/* save the alarm configuration for interrupt handling */
_sys_alarm.alarm_set = alarm;
_sys_alarm.alarm_cb = cb;
_sys_alarm.alarm_arg = arg;
/* set the timer value */
timer_hal_set_alarm_value(&sys_timer, _sys_alarm_time);
/* set the timer alarm value */
timer_ll_enable_alarm(sys_timer.dev, sys_timer.timer_id, false);
timer_ll_set_alarm_value(sys_timer.dev, sys_timer.timer_id, _sys_alarm_time);
/* clear the bit in status and set the bit in interrupt enable */
timer_hal_clear_intr_status(&sys_timer);
timer_hal_intr_enable(&sys_timer);
timer_ll_clear_intr_status(sys_timer.dev, TIMER_LL_EVENT_ALARM(sys_timer.timer_id));
timer_ll_enable_intr(sys_timer.dev, TIMER_LL_EVENT_ALARM(sys_timer.timer_id), true);
/* enable the timer alarm */
timer_hal_set_alarm_enable(&sys_timer, true);
timer_ll_enable_alarm(sys_timer.dev, sys_timer.timer_id, true);
}
static void _sys_clear_alarm(void)
{
/* disable alarms first */
timer_hal_intr_disable(&sys_timer);
timer_hal_set_alarm_enable(&sys_timer, false);
timer_ll_enable_intr(sys_timer.dev, TIMER_LL_EVENT_ALARM(sys_timer.timer_id), false);
timer_ll_enable_alarm(sys_timer.dev, sys_timer.timer_id, false);
/* clear the bit in interrupt status register */
timer_hal_clear_intr_status(&sys_timer);
timer_ll_clear_intr_status(sys_timer.dev, TIMER_LL_EVENT_ALARM(sys_timer.timer_id));
/* reset the alarm configuration for interrupt handling */
_sys_alarm.alarm_set = 0;
@ -161,8 +161,8 @@ static void _sys_save_counter(void)
critical_exit();
DEBUG("%s rtc_time_saved=%" PRIu64 " sys_time_saved=%" PRIu64 "\n", __func__,
_rtc_counter_saved, _sys_counter_saved);
DEBUG("%s rtc_time_saved=%" PRIu32 " sys_time_saved=%" PRIu32 "\n", __func__,
(uint32_t)_rtc_counter_saved, (uint32_t)_sys_counter_saved);
}
static void _sys_restore_counter(bool in_init)
@ -176,36 +176,36 @@ static void _sys_restore_counter(bool in_init)
critical_exit();
DEBUG("%s rtc_time_saved=%" PRIu64 " rtc_time_diff=%" PRIu64 " "
"sys_time_saved=%" PRIu64 " sys_time_offset=%" PRIu64 "\n", __func__,
_rtc_counter_saved, _rtc_time_diff,
_sys_counter_saved, _sys_counter_offset);
DEBUG("%s rtc_time_saved=%" PRIu32 " rtc_time_diff=%" PRIu32 " "
"sys_time_saved=%" PRIu32 " sys_time_offset=%" PRIu32 "\n", __func__,
(uint32_t)_rtc_counter_saved, (uint32_t)_rtc_time_diff,
(uint32_t)_sys_counter_saved, (uint32_t)_sys_counter_offset);
}
static void IRAM _sys_isr(void *arg)
{
uint32_t int_status;
timer_hal_get_intr_status(&sys_timer, &int_status);
if (!(int_status & TIMER_SYSTEM_INT_MASK)) {
uint32_t int_status = timer_ll_get_intr_status(sys_timer.dev);
if (!(int_status & TIMER_LL_EVENT_ALARM(sys_timer.timer_id))) {
/* return in case of another timer interrupt */
return;
}
/* disable alarms first */
timer_hal_intr_disable(&sys_timer);
timer_hal_set_alarm_enable(&sys_timer, false);
timer_ll_enable_intr(sys_timer.dev, TIMER_LL_EVENT_ALARM(sys_timer.timer_id), false);
timer_ll_enable_alarm(sys_timer.dev, sys_timer.timer_id, false);
/* clear the bit in interrupt status register */
timer_hal_clear_intr_status(&sys_timer);
timer_ll_clear_intr_status(sys_timer.dev, TIMER_LL_EVENT_ALARM(sys_timer.timer_id));
/* save the lower 32 bit of the current counter value */
uint32_t counter = _sys_get_counter();
DEBUG("%s %" PRIu32 "\n", __func__, counter);
DEBUG("%s %" PRIu32 " @sys_time=%" PRIu32 "\n",
__func__, counter, (uint32_t)system_get_time_64());
if (_sys_alarm.alarm_cb) {
DEBUG("%s alarm %" PRIu32 "\n", __func__, counter);
DEBUG("%s alarm %" PRIu32 " @sys_time=%" PRIu32 "\n",
__func__, counter, (uint32_t)system_get_time_64());
rtt_cb_t alarm_cb = _sys_alarm.alarm_cb;
void *alarm_arg = _sys_alarm.alarm_arg;

54
cpu/esp32/periph/sdmmc.c
View File

@ -122,6 +122,8 @@ static void _isr_cd_pin(void *arg);
static void _init(sdmmc_dev_t *sdmmc_dev)
{
DEBUG("[sdmmc] %s", __func__);
esp32_sdmmc_dev_t *dev = container_of(sdmmc_dev, esp32_sdmmc_dev_t, sdmmc_dev);
assert(dev);
@ -243,7 +245,7 @@ static int _send_cmd(sdmmc_dev_t *sdmmc_dev, sdmmc_cmd_t cmd_idx, uint32_t arg,
.data = 0,
.datalen = 0,
.blklen = 0,
.timeout_ms = 100,
.timeout_ms = 1000,
};
switch (resp_type) {
@ -266,7 +268,7 @@ static int _send_cmd(sdmmc_dev_t *sdmmc_dev, sdmmc_cmd_t cmd_idx, uint32_t arg,
cmd.flags |= SCF_RSP_R5;
break;
case SDMMC_R6:
cmd.flags |= SCF_RSP_R7;
cmd.flags |= SCF_RSP_R6;
break;
case SDMMC_R7:
cmd.flags |= SCF_RSP_R7;
@ -275,13 +277,13 @@ static int _send_cmd(sdmmc_dev_t *sdmmc_dev, sdmmc_cmd_t cmd_idx, uint32_t arg,
break;
}
DEBUG("[sdmmc] %s dev=%p slot=%d op=%" PRIu32 " arg=%" PRIx32 " flags=%x\n",
__func__, dev, dev->config->slot, cmd.opcode, cmd.arg, cmd.flags);
esp_err_t res = sdmmc_host_do_transaction(dev->config->slot, &cmd);
if (res) {
return _esp_err_to_sdmmc_err_code(res);
}
else if (cmd.error) {
return _esp_err_to_sdmmc_err_code(cmd.error);
}
if ((resp_type == SDMMC_R1) || (resp_type == SDMMC_R1B)) {
sdmmc_dev->status = cmd.response[0];
@ -299,6 +301,28 @@ static int _send_cmd(sdmmc_dev_t *sdmmc_dev, sdmmc_cmd_t cmd_idx, uint32_t arg,
}
}
if (cmd.error) {
#if CPU_FAM_ESP32S3
/*
* FIXME:
* The host controller triggers an invalid response error on ESP32-S3,
* although the response from the card is completely correct and is
* received completely by the host controller. The reason for this is
* not yet clear. The sequence of commands including all parameters
* sent to the host controller as well as the timing are exactly the
* same as in the IDF code. The initialization of the host controller
* is also exactly the same as in the IDF code. The problem only
* occurs with the ESP32-S3, but not with the ESP32. As a workaround,
* we ignore invalid response errors on ESP32-S3.
*/
if (cmd.error != ESP_ERR_INVALID_RESPONSE) {
return _esp_err_to_sdmmc_err_code(cmd.error);
}
#else
return _esp_err_to_sdmmc_err_code(cmd.error);
#endif
}
return 0;
}
@ -385,7 +409,7 @@ static int _xfer_execute(sdmmc_dev_t *sdmmc_dev, sdmmc_xfer_desc_t *xfer,
.data = xfer->write ? (void *)data_wr : data_rd,
.datalen = xfer->block_num * xfer->block_size,
.blklen = xfer->block_size,
.timeout_ms = xfer->write ? 2500 : 1000, // TODO
.timeout_ms = xfer->write ? 2500 : 1000, /* TODO */
};
if (done) {
@ -397,7 +421,25 @@ static int _xfer_execute(sdmmc_dev_t *sdmmc_dev, sdmmc_xfer_desc_t *xfer,
return _esp_err_to_sdmmc_err_code(res);
}
else if (cmd.error) {
#ifdef CPU_FAM_ESP32S3
/*
* FIXME:
* The host controller triggers an invalid response error on ESP32-S3,
* although the response from the card is completely correct and is
* received completely by the host controller. The reason for this is
* not yet clear. The sequence of commands including all parameters
* sent to the host controller as well as the timing are exactly the
* same as in the IDF code. The initialization of the host controller
* is also exactly the same as in the IDF code. The problem only
* occurs with the ESP32-S3, but not with the ESP32. As a workaround,
* we ignore invalid response errors on ESP32-S3.
*/
if (cmd.error != ESP_ERR_INVALID_RESPONSE) {
return _esp_err_to_sdmmc_err_code(cmd.error);
}
#else
return _esp_err_to_sdmmc_err_code(cmd.error);
#endif
}
if (done) {

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