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Merge pull request #21555 from HendrikVE/hendrik/dac-changes
cpu/sam0_common: enable static voltages
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commit
55c2061a42
@ -27,6 +27,14 @@
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#define DAC_VAL(in) (in >> (16 - DAC_RES_BITS))
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#define DAC_VAL(in) (in >> (16 - DAC_RES_BITS))
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#ifndef CONFIG_SAM0_DAC_REFRESH
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#define CONFIG_SAM0_DAC_REFRESH 2
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#endif
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#ifndef CONFIG_SAM0_DAC_RUN_ON_STANDBY
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#define CONFIG_SAM0_DAC_RUN_ON_STANDBY 0
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#endif
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static void _dac_init_clock(dac_t line)
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static void _dac_init_clock(dac_t line)
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{
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{
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sam0_gclk_enable(DAC_CLOCK);
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sam0_gclk_enable(DAC_CLOCK);
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@ -110,13 +118,29 @@ int8_t dac_init(dac_t line)
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_dac_init_clock(line);
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_dac_init_clock(line);
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/* Settings can only be changed when DAC is disabled, reset config */
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/* Settings can only be changed when DAC is disabled */
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DAC->CTRLA.reg = DAC_CTRLA_SWRST;
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DAC->CTRLA.reg &= ~DAC_CTRLA_ENABLE;
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_sync();
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_sync();
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#ifdef DAC_DACCTRL_ENABLE
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#ifdef DAC_DACCTRL_ENABLE
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DAC->DACCTRL[line].reg = DAC_DACCTRL_ENABLE
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DAC->DACCTRL[line].reg = DAC_DACCTRL_ENABLE
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| _get_CCTRL(sam0_gclk_freq(DAC_CLOCK));
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| _get_CCTRL(sam0_gclk_freq(DAC_CLOCK))
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#endif
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#if CONFIG_SAM0_DAC_RUN_ON_STANDBY && defined(DAC_DACCTRL_RUNSTDBY)
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| DAC_DACCTRL_RUNSTDBY
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#endif
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;
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#ifdef DAC_DACCTRL_REFRESH
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/** The DAC can only maintain its output on the desired value for approximately 100 μs.
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* For static voltages the conversion must be refreshed periodically (see e.g.
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* '47.6.9.3 Conversion Refresh' in the SAM D5xE5x family data sheet).
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*
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* Note: T_REFRESH = REFRESH * T_OSCULP32K
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*/
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static_assert(CONFIG_SAM0_DAC_REFRESH != 1, "DACCTRLx.REFRESH = 1 is reserved");
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DAC->DACCTRL[line].bit.REFRESH = CONFIG_SAM0_DAC_REFRESH;
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#endif
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#endif
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/* Set Reference Voltage & enable Output if needed */
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/* Set Reference Voltage & enable Output if needed */
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@ -126,7 +150,11 @@ int8_t dac_init(dac_t line)
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#endif
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#endif
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;
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;
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DAC->CTRLA.reg = DAC_CTRLA_ENABLE;
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DAC->CTRLA.reg = DAC_CTRLA_ENABLE
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#if CONFIG_SAM0_DAC_RUN_ON_STANDBY && defined(DAC_CTRLA_RUNSTDBY)
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| DAC_CTRLA_RUNSTDBY
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#endif
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;
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_sync();
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_sync();
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#ifdef DAC_STATUS_READY
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#ifdef DAC_STATUS_READY
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