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https://github.com/RIOT-OS/RIOT.git
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kinetis: Merge cpu_conf settings into kinetis_common
This commit is contained in:
Joakim Nohlgård
parent
de78f501ea
commit
60a5c85ca8
@ -22,52 +22,19 @@
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#ifndef CPU_CONF_H
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#define CPU_CONF_H
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#include "cpu_conf_common.h"
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#ifdef CPU_MODEL_MK22FN512VLH12
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#include "vendor/MK22F51212.h"
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#else
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#error "undefined CPU_MODEL"
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#endif
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#include "cpu_conf_kinetis.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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* @name ARM Cortex-M specific CPU configuration
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* @{
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*/
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#define CPU_DEFAULT_IRQ_PRIO (1U)
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#define CPU_IRQ_NUMOF (89U)
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#define CPU_FLASH_BASE (0x00000000)
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/** @} */
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/**
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* @name GPIO pin mux function numbers
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* @{
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*/
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#define PIN_MUX_FUNCTION_ANALOG 0
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#define PIN_MUX_FUNCTION_GPIO 1
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/** @} */
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/**
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* @name GPIO interrupt flank settings
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* @{
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*/
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#define PIN_INTERRUPT_RISING 0b1001
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#define PIN_INTERRUPT_FALLING 0b1010
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#define PIN_INTERRUPT_EDGE 0b1011
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/** @} */
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/**
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* @name Timer hardware information
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* @{
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*/
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#define LPTMR_CLKEN() (bit_set32(&SIM->SCGC5, SIM_SCGC5_LPTMR_SHIFT)) /**< Enable LPTMR0 clock gate */
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#define PIT_CLKEN() (bit_set32(&SIM->SCGC6, SIM_SCGC6_PIT_SHIFT)) /**< Enable PIT clock gate */
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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@ -7,9 +7,10 @@
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*/
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/**
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* @defgroup cpu_k60 Freescale Kinetis K60
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* @defgroup cpu_k60 NXP Kinetis K60
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* @ingroup cpu
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* @brief CPU specific implementations for the Freescale Kinetis K60
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* @brief CPU specific implementations for the NXP Kinetis K60
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* Cortex-M4 MCU
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* @{
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*
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* @file
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@ -21,15 +22,6 @@
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#ifndef CPU_CONF_H
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#define CPU_CONF_H
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#include "cpu_conf_common.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#include <stdint.h>
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#if defined(CPU_MODEL_MK60DN512VLL10) || defined(CPU_MODEL_MK60DN256VLL10)
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#include "vendor/MK60D10.h"
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@ -39,44 +31,18 @@ extern "C"
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#error Unknown CPU model. Update Makefile.include in the board directory.
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#endif
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#include "cpu_conf_kinetis.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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* @brief This CPU provides an additional ADC clock divider as CFG1[ADICLK]=1
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*/
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#define KINETIS_HAVE_ADICLK_BUS_DIV_2 1
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/**
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* @brief ARM Cortex-M specific CPU configuration
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* @{
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*/
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#define CPU_DEFAULT_IRQ_PRIO (1U)
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#define CPU_IRQ_NUMOF (104U)
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#define CPU_FLASH_BASE (0x00000000)
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/** @} */
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/**
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* @name GPIO pin mux function numbers
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*/
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/** @{ */
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#define PIN_MUX_FUNCTION_ANALOG 0
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#define PIN_MUX_FUNCTION_GPIO 1
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/** @} */
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/**
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* @name GPIO interrupt flank settings
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*/
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/** @{ */
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#define PIN_INTERRUPT_RISING 0b1001
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#define PIN_INTERRUPT_FALLING 0b1010
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#define PIN_INTERRUPT_EDGE 0b1011
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/** @} */
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/**
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* @name Timer hardware information
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*/
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/** @{ */
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#define LPTMR_CLKEN() (bit_set32(&SIM->SCGC5, SIM_SCGC5_LPTMR_SHIFT)) /**< Enable LPTMR0 clock gate */
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#define PIT_CLKEN() (bit_set32(&SIM->SCGC6, SIM_SCGC6_PIT_SHIFT)) /**< Enable PIT clock gate */
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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@ -24,52 +24,19 @@
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#ifndef CPU_CONF_H
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#define CPU_CONF_H
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#include "cpu_conf_common.h"
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#ifdef CPU_MODEL_MK64FN1M0VLL12
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#include "vendor/MK64F12.h"
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#else
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#error "undefined CPU_MODEL"
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#endif
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#include "cpu_conf_kinetis.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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* @brief ARM Cortex-M specific CPU configuration
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* @{
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*/
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#define CPU_DEFAULT_IRQ_PRIO (1U)
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#define CPU_IRQ_NUMOF (86U)
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#define CPU_FLASH_BASE (0x00000000)
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/** @} */
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/**
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* @name GPIO pin mux function numbers
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*/
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/** @{ */
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#define PIN_MUX_FUNCTION_ANALOG 0
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#define PIN_MUX_FUNCTION_GPIO 1
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/** @} */
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/**
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* @name GPIO interrupt flank settings
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*/
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/** @{ */
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#define PIN_INTERRUPT_RISING 0b1001
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#define PIN_INTERRUPT_FALLING 0b1010
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#define PIN_INTERRUPT_EDGE 0b1011
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/** @} */
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/**
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* @name Timer hardware information
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*/
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/** @{ */
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#define LPTMR_CLKEN() (bit_set32(&SIM->SCGC5, SIM_SCGC5_LPTMR_SHIFT)) /**< Enable LPTMR0 clock gate */
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#define PIT_CLKEN() (bit_set32(&SIM->SCGC6, SIM_SCGC6_PIT_SHIFT)) /**< Enable PIT clock gate */
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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77
cpu/kinetis_common/include/cpu_conf_kinetis.h
Normal file
77
cpu/kinetis_common/include/cpu_conf_kinetis.h
Normal file
@ -0,0 +1,77 @@
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/*
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* Copyright (C) 2017 Eistec AB
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_kinetis_common
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* @{
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*
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* @file
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* @brief CPU specific definitions common to all Kinetis CPUs
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*
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* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
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*/
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#ifndef CPU_CONF_KINETIS_H
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#define CPU_CONF_KINETIS_H
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#include "cpu_conf_common.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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* @name ARM Cortex-M specific CPU configuration
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* @{
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*/
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#define CPU_DEFAULT_IRQ_PRIO (1U)
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/* Each interrupt priority setting is 8 bits wide, for both CM4 and CM0+, but
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* they are laid out differently. CM0+ concatenates the settings into 32 bit
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* words, CM4 and CM7 uses direct 8 bit access */
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#define CPU_IRQ_NUMOF (sizeof(NVIC->IP))
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#define CPU_FLASH_BASE (0x00000000)
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/** @} */
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/**
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* @name GPIO pin mux function numbers
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* @{
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*/
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#define PIN_MUX_FUNCTION_ANALOG 0
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#define PIN_MUX_FUNCTION_GPIO 1
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/** @} */
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/**
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* @name GPIO interrupt flank settings
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* @{
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*/
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#define PIN_INTERRUPT_RISING 0b1001
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#define PIN_INTERRUPT_FALLING 0b1010
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#define PIN_INTERRUPT_EDGE 0b1011
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/** @} */
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/**
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* @name Timer hardware information
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* @{
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*/
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#ifdef SIM_SCGC5_LPTMR_SHIFT
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/** Enable LPTMR clock gate */
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#define LPTMR_CLKEN() (bit_set32(&SIM->SCGC5, SIM_SCGC5_LPTMR_SHIFT))
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#endif
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#ifdef SIM_SCGC6_PIT_SHIFT
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/** Enable PIT clock gate */
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#define PIT_CLKEN() (bit_set32(&SIM->SCGC6, SIM_SCGC6_PIT_SHIFT))
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#endif
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* CPU_CONF_KINETIS_H */
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/** @} */
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@ -25,8 +25,6 @@
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#ifndef CPU_CONF_H
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#define CPU_CONF_H
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#include "cpu_conf_common.h"
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#ifdef CPU_MODEL_KW21D256
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#include "vendor/MKW22D5.h"
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#elif CPU_MODEL_KW21D512
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@ -37,41 +35,18 @@
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#error "undefined CPU_MODEL"
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#endif
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#include "cpu_conf_kinetis.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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* @brief ARM Cortex-M specific CPU configuration
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* @{
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*/
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#define CPU_DEFAULT_IRQ_PRIO (1U)
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#define CPU_IRQ_NUMOF (65U)
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#define CPU_FLASH_BASE (0x00000000)
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/** @} */
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/**
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* @brief This CPU provides an additional ADC clock divider as CFG1[ADICLK]=1
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*/
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#define KINETIS_HAVE_ADICLK_BUS_DIV_2 1
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/**
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* @name GPIO pin mux function numbers
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*/
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/** @{ */
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#define PIN_MUX_FUNCTION_ANALOG 0
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#define PIN_MUX_FUNCTION_GPIO 1
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/** @} */
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/**
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* @name GPIO interrupt flank settings
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*/
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/** @{ */
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#define PIN_INTERRUPT_RISING 0b1001
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#define PIN_INTERRUPT_FALLING 0b1010
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#define PIN_INTERRUPT_EDGE 0b1011
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/** @} */
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/** @name PORT module clock gates */
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/** @{ */
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#define PORTA_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTA_SHIFT))
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@ -81,14 +56,6 @@ extern "C"
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#define PORTE_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT))
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/** @} */
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/**
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* @name Timer hardware information
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*/
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/** @{ */
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#define LPTMR_CLKEN() (bit_set32(&SIM->SCGC5, SIM_SCGC5_LPTMR_SHIFT)) /**< Enable LPTMR0 clock gate */
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#define PIT_CLKEN() (bit_set32(&SIM->SCGC6, SIM_SCGC6_PIT_SHIFT)) /**< Enable PIT clock gate */
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/** @} */
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/**
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* @name KW2XD SiP internal interconnects between MCU and Modem.
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*
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