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cpu/esp32: add flashpage support to linker scripts

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This commit is contained in:
Gunar Schorcht 2022-12-31 13:20:16 +01:00
parent 6f9c64c6cb
commit 80833a74e8
8 changed files with 71 additions and 1 deletions
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7
cpu/esp32/ld/esp32/memory.ld.in
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@ -84,9 +84,16 @@ MEMORY
#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS #ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/* Flash mapped constant data */ /* Flash mapped constant data */
#ifdef MODULE_PERIPH_FLASHPAGE
drom0_0_seg (R) : org = 0x3F400020,
len = 0x400000 - 0x20 - CONFIG_ESP_FLASHPAGE_CAPACITY
drom0_1_seg (R) : org = ORIGIN(drom0_0_seg) + LENGTH(drom0_0_seg),
len = CONFIG_ESP_FLASHPAGE_CAPACITY
#else
drom0_0_seg (R) : org = 0x3F400020, len = 0x400000-0x20 drom0_0_seg (R) : org = 0x3F400020, len = 0x400000-0x20
/* (See iram0_2_seg for meaning of 0x20 offset in the above.) */ /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
#endif /* MODULE_PERIPH_FLASHPAGE */
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/* RTC fast memory (executable). Persists over deep sleep. /* RTC fast memory (executable). Persists over deep sleep.

12
cpu/esp32/ld/esp32/sections.ld.in
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@ -466,7 +466,6 @@ SECTIONS
. = ALIGN(ALIGNOF(.flash.rodata)); . = ALIGN(ALIGNOF(.flash.rodata));
} >default_rodata_seg } >default_rodata_seg
_rodata_start = ABSOLUTE(.);
.flash.rodata : ALIGN(0x10) .flash.rodata : ALIGN(0x10)
{ {
_flash_rodata_start = ABSOLUTE(.); _flash_rodata_start = ABSOLUTE(.);
@ -617,6 +616,17 @@ SECTIONS
_heap_start = ABSOLUTE(.); _heap_start = ABSOLUTE(.);
_sheap = ABSOLUTE(.); _sheap = ABSOLUTE(.);
} > dram0_0_seg } > dram0_0_seg
#ifdef MODULE_PERIPH_FLASHPAGE
.flash_writable (NOLOAD) : ALIGN(65536)
{
_fp_mem_start = . ;
KEEP(*(SORT(.flash_writable.*)))
_fp_mem_end = . ;
. = ALIGN(4096);
_end_fw = . ;
} > drom0_1_seg
#endif
} }
ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)), ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),

7
cpu/esp32/ld/esp32c3/memory.ld.in
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@ -72,9 +72,16 @@ MEMORY
#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/* Flash mapped constant data */ /* Flash mapped constant data */
#ifdef MODULE_PERIPH_FLASHPAGE
drom0_0_seg (R) : org = 0x3C000020,
len = 0x800000 - 0x20 - CONFIG_ESP_FLASHPAGE_CAPACITY
drom0_1_seg (R) : org = ORIGIN(drom0_0_seg) + LENGTH(drom0_0_seg),
len = CONFIG_ESP_FLASHPAGE_CAPACITY
#else
drom0_0_seg (R) : org = 0x3C000020, len = 0x800000-0x20 drom0_0_seg (R) : org = 0x3C000020, len = 0x800000-0x20
/* (See iram0_2_seg for meaning of 0x20 offset in the above.) */ /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
#endif /* MODULE_PERIPH_FLASHPAGE */
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/** /**

10
cpu/esp32/ld/esp32c3/sections.ld.in
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@ -599,6 +599,16 @@ SECTIONS
} > dram0_0_seg } > dram0_0_seg
_eheap = phy_param_rom; _eheap = phy_param_rom;
#ifdef MODULE_PERIPH_FLASHPAGE
.flash_writable (NOLOAD) : ALIGN(65536)
{
_fp_mem_start = . ;
KEEP(*(SORT(.flash_writable.*)))
_fp_mem_end = . ;
. = ALIGN(4096);
_end_fw = . ;
} > drom0_1_seg
#endif
} }
ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)), ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),

7
cpu/esp32/ld/esp32s2/memory.ld.in
View File

@ -90,9 +90,16 @@ MEMORY
#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS #ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/* Flash mapped constant data */ /* Flash mapped constant data */
#ifdef MODULE_PERIPH_FLASHPAGE
drom0_0_seg (R) : org = 0x3F000020,
len = 0x3f0000-0x20 - CONFIG_ESP_FLASHPAGE_CAPACITY
drom0_1_seg (R) : org = ORIGIN(drom0_0_seg) + LENGTH(drom0_0_seg),
len = CONFIG_ESP_FLASHPAGE_CAPACITY
#else
drom0_0_seg (R) : org = 0x3F000020, len = 0x3f0000-0x20 drom0_0_seg (R) : org = 0x3F000020, len = 0x3f0000-0x20
/* (See iram0_2_seg for meaning of 0x20 offset in the above.) */ /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
#endif /* MODULE_PERIPH_FLASHPAGE */
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/* RTC fast memory (executable). Persists over deep sleep. /* RTC fast memory (executable). Persists over deep sleep.

11
cpu/esp32/ld/esp32s2/sections.ld.in
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@ -592,6 +592,17 @@ SECTIONS
. = _heap_end; . = _heap_end;
_eheap = ABSOLUTE(.); _eheap = ABSOLUTE(.);
#ifdef MODULE_PERIPH_FLASHPAGE
.flash_writable (NOLOAD) : ALIGN(65536)
{
_fp_mem_start = . ;
KEEP(*(SORT(.flash_writable.*)))
_fp_mem_end = . ;
. = ALIGN(4096);
_end_fw = . ;
} > drom0_1_seg
#endif
} }
ASSERT(((_iram_text_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)), ASSERT(((_iram_text_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),

7
cpu/esp32/ld/esp32s3/memory.ld.in
View File

@ -90,9 +90,16 @@ MEMORY
#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/* Flash mapped constant data */ /* Flash mapped constant data */
#ifdef MODULE_PERIPH_FLASHPAGE
drom0_0_seg (R) : org = 0x3C000020,
len = 0x800000-0x20 - CONFIG_ESP_FLASHPAGE_CAPACITY
drom0_1_seg (R) : org = ORIGIN(drom0_0_seg) + LENGTH(drom0_0_seg),
len = CONFIG_ESP_FLASHPAGE_CAPACITY
#else
drom0_0_seg (R) : org = 0x3C000020, len = 0x800000-0x20 drom0_0_seg (R) : org = 0x3C000020, len = 0x800000-0x20
/* (See iram0_2_seg for meaning of 0x20 offset in the above.) */ /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
#endif /* MODULE_PERIPH_FLASHPAGE */
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/** /**

11
cpu/esp32/ld/esp32s3/sections.ld.in
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@ -619,6 +619,17 @@ SECTIONS
. = _heap_end; . = _heap_end;
_eheap = ABSOLUTE(.); _eheap = ABSOLUTE(.);
#ifdef MODULE_PERIPH_FLASHPAGE
.flash_writable (NOLOAD) : ALIGN(65536)
{
_fp_mem_start = . ;
KEEP(*(SORT(.flash_writable.*)))
_fp_mem_end = . ;
. = ALIGN(4096);
_end_fw = . ;
} > drom0_1_seg
#endif
} }
ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)), ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),