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https://github.com/RIOT-OS/RIOT.git
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Merge pull request #11260 from maribu/nucleo-f767zi
boards/nucleof7*: SPI and refactoring
This commit is contained in:
Alexandre Abadie
GitHub
commit
f559ccb0c6
@ -111,6 +111,15 @@ extern "C" {
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1 /* -> 12500000Hz */ \
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},
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#define CFG_SPIDIV_54 \
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{ /* for 54000000Hz */ \
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7, /* -> 210937Hz */ \
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6, /* -> 421875Hz */ \
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5, /* -> 843750Hz */ \
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3, /* -> 3375000Hz */ \
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2 /* -> 6750000Hz */ \
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},
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#define CFG_SPIDIV_60 \
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{ /* for 60000000Hz */ \
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7, /* -> 234375Hz */ \
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@ -173,6 +182,15 @@ extern "C" {
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3, /* -> 6250000Hz */ \
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2 /* -> 12500000Hz */ \
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},
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#define CFG_SPIDIV_108 \
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{ /* for 108000000Hz */ \
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7, /* -> 421875Hz */ \
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7, /* -> 421875Hz */ \
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6, /* -> 843750Hz */ \
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4, /* -> 3375000Hz */ \
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3 /* -> 6750000Hz */ \
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},
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/** @} */
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@ -203,6 +221,8 @@ static const uint8_t spi_divtable[2][5] = {
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CFG_SPIDIV_48
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#elif (CLOCK_APB1 == 50000000)
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CFG_SPIDIV_50
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#elif (CLOCK_APB1 == 54000000)
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CFG_SPIDIV_54
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#elif (CLOCK_APB1 == 72000000)
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CFG_SPIDIV_72
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#elif (CLOCK_APB1 == 60000000)
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@ -253,6 +273,8 @@ static const uint8_t spi_divtable[2][5] = {
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CFG_SPIDIV_96
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#elif (CLOCK_APB2 == 100000000)
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CFG_SPIDIV_100
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#elif (CLOCK_APB2 == 108000000)
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CFG_SPIDIV_108
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#else
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#error "CFG_SPI_DIVTABLE: no prescalers for selected APB2 bus clock defined"
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#endif
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59
boards/common/stm32/include/f7/cfg_clock_216_8_1.h
Normal file
59
boards/common/stm32/include/f7/cfg_clock_216_8_1.h
Normal file
@ -0,0 +1,59 @@
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/*
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* Copyright (C) 2019 Otto-von-Guericke-Universität Magdeburg
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_common_stm32
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* @{
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*
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* @file
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* @brief Configure STM32F7 clock to 216MHz and 8MHz HSE using PLL with
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* LSE
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*
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* @author Marian Buschsieweke <marian.buschsieweke@ovgu.de>
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*
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* @note This is auto-generated from
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* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
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* @{
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*/
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#ifndef F7_CFG_CLOCK_216_8_1_H
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#define F7_CFG_CLOCK_216_8_1_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* give the target core clock (HCLK) frequency [in Hz],
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* maximum: 216MHz */
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#define CLOCK_CORECLOCK (216000000U)
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/* 0: no external high speed crystal available
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* else: actual crystal frequency [in Hz] */
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#define CLOCK_HSE (8000000U)
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz) */
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#define CLOCK_LSE (1U)
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/* peripheral clock setup */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 54MHz */
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 108MHz */
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
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/* Main PLL factors */
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#define CLOCK_PLL_M (4)
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#define CLOCK_PLL_N (216)
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#define CLOCK_PLL_P (2)
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#define CLOCK_PLL_Q (9)
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#ifdef __cplusplus
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}
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#endif
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#endif /* F7_CFG_CLOCK_216_8_1_H */
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/** @} */
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@ -22,43 +22,13 @@
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#include "f7/cfg_clock_216_8_1.h"
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#include "cfg_i2c1_pb8_pb9.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock settings
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*
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* @note This is auto-generated from
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* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
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* @{
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*/
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/* give the target core clock (HCLK) frequency [in Hz],
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* maximum: 216MHz */
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#define CLOCK_CORECLOCK (216000000U)
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/* 0: no external high speed crystal available
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* else: actual crystal frequency [in Hz] */
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#define CLOCK_HSE (8000000U)
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz) */
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#define CLOCK_LSE (1)
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/* peripheral clock setup */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 54MHz */
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 108MHz */
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
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/* Main PLL factors */
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#define CLOCK_PLL_M (4)
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#define CLOCK_PLL_N (216)
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#define CLOCK_PLL_P (2)
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#define CLOCK_PLL_Q (9)
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/** @} */
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/**
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* @name Timer configuration
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* @{
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@ -22,43 +22,13 @@
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#include "f7/cfg_clock_216_8_1.h"
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#include "cfg_i2c1_pb8_pb9.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock settings
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*
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* @note This is auto-generated from
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* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
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* @{
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*/
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/* give the target core clock (HCLK) frequency [in Hz],
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* maximum: 216MHz */
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#define CLOCK_CORECLOCK (216000000U)
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/* 0: no external high speed crystal available
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* else: actual crystal frequency [in Hz] */
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#define CLOCK_HSE (8000000U)
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz) */
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#define CLOCK_LSE (1)
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/* peripheral clock setup */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 54MHz */
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 108MHz */
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
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/* Main PLL factors */
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#define CLOCK_PLL_M (4)
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#define CLOCK_PLL_N (216)
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#define CLOCK_PLL_P (2)
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#define CLOCK_PLL_Q (9)
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/** @} */
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/**
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* @name Timer configuration
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* @{
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@ -2,6 +2,7 @@
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FEATURES_PROVIDED += periph_dma
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FEATURES_PROVIDED += periph_i2c
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FEATURES_PROVIDED += periph_rtc
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_timer
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FEATURES_PROVIDED += periph_uart
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@ -22,43 +22,14 @@
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#include "f7/cfg_clock_216_8_1.h"
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#include "cfg_i2c1_pb8_pb9.h"
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#include "cfg_spi_divtable.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock settings
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*
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* @note This is auto-generated from
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* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
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* @{
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*/
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/* give the target core clock (HCLK) frequency [in Hz],
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* maximum: 216MHz */
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#define CLOCK_CORECLOCK (216000000U)
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/* 0: no external high speed crystal available
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* else: actual crystal frequency [in Hz] */
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#define CLOCK_HSE (8000000U)
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz) */
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#define CLOCK_LSE (1)
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/* peripheral clock setup */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 54MHz */
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 108MHz */
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
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/* Main PLL factors */
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#define CLOCK_PLL_M (4)
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#define CLOCK_PLL_N (216)
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#define CLOCK_PLL_P (2)
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#define CLOCK_PLL_Q (9)
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/** @} */
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/**
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* @name DMA streams configuration
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* @{
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@ -153,6 +124,29 @@ static const uart_conf_t uart_config[] = {
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#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
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/** @} */
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/**
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* @name SPI configuration
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*
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* @note The spi_divtable is auto-generated from
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* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
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* @{
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*/
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static const spi_conf_t spi_config[] = {
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{
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.dev = SPI1,
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.mosi_pin = GPIO_PIN(PORT_A, 7),
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.miso_pin = GPIO_PIN(PORT_A, 6),
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.sclk_pin = GPIO_PIN(PORT_A, 5),
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.cs_pin = GPIO_UNDEF,
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.af = GPIO_AF5,
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.rccmask = RCC_APB2ENR_SPI1EN,
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.apbbus = APB2
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},
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};
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#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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