DMA mode is disabled for now due to several problems:
- The STALL bit of the OUT control endpoint does not seem to be cleared automatically on the next SETUP received. At least the USB OTG HS core does not generate an interrupt on the next SETUP received. This happens, for example, when CDC ACM is used and the host sends the SET_LINE_CODING request. In this case the enumeration of further interfaces, for example CDC ECM is stopped.
- The Enumeration fails for CDC ECM interface which uses URB support.
This commit fixes the problem that the driver uses the wrong number of EPs when using the USB OTG HS core. The reason is that the constant `DWC2_USB_OTG_FS_NUM_EP` is used in several places even though there is a function `_max_endpoints` which takes into account the configuration used. For most MCUs this is not a problem, because they have only a USB OTG FS core anyway. But for MCUs like the STM32, which has both a USB OTG FS core and a USB OTG HS core, it matters.
Use `DWC2_USB_OTG_FS_TOTAL_FIFO_SIZE` instead of `USB_OTG_FS_TOTAL_FIFO_SIZE` since the latter is only defined in the vendor headers for STM32 MCUs. The STM32-specific problem that `USB_OTG_FS_TOTAL_FIFO_SIZE` is not defined in the vendor headers for all STM32 families has therefore been moved from the driver to the STM32-specific USB device header.
When using DMA to transfer endpoint data from the RX FIFO to the
endpoint memory, the RXFLVL irq is not needed as that is already handled
by the DMA. Furthermore, servicing this irq anyway can cause the event
handling to interpret data from the FIFO as the endpoint and status
marker during the DMA transfer.
This commit masks the RXFLVL irq while DMA is used for the endpoint
transfers.
The existence of the macros USB_OTG_GUSBCFG_ULPI_UTMI_SEL, USB_OTG_GUSBCFG_PHYIF and USB_OTG_GUSBCFG_DDRSEL depends on a specific STM32 line and not on STM32 itself. Therefore, the settings are made when the macros are defined.
