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5903 Commits

Author SHA1 Message Date
Jean Pierre Dudey
e2489ced97
cc26xx_cc13xx: add register values 
Add some register values needed to trim registers.

Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-04-29 18:16:45 -05:00
Jean Pierre Dudey
e514266186
cc26x2_cc13x2: add FCFG->DAC_BIAS_CNF values 
These are necessary to trim some registers at startup.

Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-04-29 18:16:45 -05:00
Jean Pierre Dudey
6829dfdf1b
cc26xx_cc13xx: fix FLASH->CFG offset, update VIMS 
- Changed "meh" to "Reserved".
- Renamed CTL to CFG to match SDK/TRM name.
- Added constants for VIMS and FLASH necessary to trim registers.

Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-04-29 18:16:45 -05:00
Jean Pierre Dudey
1733e62217
cc26xx_cc13xx: update AON_IOC register bank 
- Updated documentation
- Fixed register bank name
- Added missing field

Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-04-29 18:16:45 -05:00
Jean Pierre Dudey
cdf2e88804
cc26x2_cc13x2: add 16-bit masked access to DDI_0_OSC 
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-04-29 18:16:45 -05:00
Jean Pierre Dudey
1586c89f1a
cc26x2_cc13x2: update DDI_0_OSC register bank 
- Fixes padding.
- Updates documentation.
- Removes documentation longer than 80-chars for the registers values.

Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-04-29 10:17:20 -05:00
Jean Pierre Dudey
2921944c66
cc26x2_cc13x2: add function to change AUX opmode 
This function is needed to setup the AUX operational mode at startup,
also used for managing low-power states.

Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-04-29 09:38:36 -05:00
Alexandre Abadie
5a9f01d91a
native: pass eeprom file path via command line 2020-04-29 08:56:33 +02:00
Alexandre Abadie
cbdda3c990
cpu/native: read/persist EEPROM data at startup/reboot/exit 2020-04-29 08:55:10 +02:00
Alexandre Abadie
4e1d7abddc
cpu/native: implement eeprom peripheral driver 
The driver simply manages an internal buffer in memory that can be filled/dumped from/to a file
 2020-04-29 08:55:08 +02:00
benpicco
4bb8fab1dc
Merge pull request #13971 from bergzand/pr/sam0_common/cpuid_clarify 
sam0_common: clarify memcpy in cpuid_get
 2020-04-28 18:31:27 +02:00
benpicco
96c638f2d1
Merge pull request #13949 from benpicco/MAKEFILEDIR-doc 
Makefile.include: update the documentation of $(MAKEFILEDIR)
 2020-04-28 18:30:44 +02:00
Benjamin Valentin
d5dce87e1b Makefile.include: rename MAKEFILEDIR to LAST_MAKEFILEDIR 
Rename the variable to make it clearer that it refers to the last Makefile
included.
Usually this is the current file, but when another Makefile is included this
changes.
 2020-04-28 15:45:27 +02:00
Koen Zandberg
fe299138aa
sam0_common: clarify memcpy in cpuid_get 2020-04-28 14:56:19 +02:00
Francisco Molina
b78e4efb56
cpu/stm32f1: dont provide periph_rtc at cpu level 
stm32f1 periph_rtc implementation gets a 1s resolution by dividing
CLOCK_LSx by 32768. This only make sense if CLOCK_LSE is set,
otherwise CLOCK_LSI=~40000, which will lead to an imprecise rtc.
 2020-04-27 08:59:21 +02:00
benpicco
4ceff67ca0
Merge pull request #13127 from francois-berder/remove-objcopy-warning 
cpu: mips_pic32*: Fix unused .gcc_except_table section warning
 2020-04-26 23:27:30 +02:00
Benjamin Valentin
da89f6ac5f cpu/samd21: don't hard-code number of channels 
Each TCC can have 8 PWM channels, so don't hard-code
3 channels/TCC.
 2020-04-26 22:26:01 +02:00
Marian Buschsieweke
70a558059e
Merge pull request #13955 from benpicco/cpu/lpc2387-pm_num_modes 
cpu/lpc2387: PM_NUM_MODES must only count non-idle modes
 2020-04-26 21:46:40 +02:00
benpicco
bbe1e723df
Merge pull request #13936 from btcven/2020_04_23-aux 
cc26x2_cc13x2: fix AUX_* register domain documentation
 2020-04-26 20:41:40 +02:00
Benjamin Valentin
c21b5d6f55 cpu/lpc2387: PM_NUM_MODES must only count non-idle modes 
lpc23xx has 3 sleep modes and one idle mode.
`PM_NUM_MODES` must only count the idle modes.

In practise, this makes no difference since `mode 3` (IDLE) is
the `default` case in `pm_set()` anyway.
 2020-04-26 19:45:43 +02:00
benpicco
5ca030b311
Merge pull request #13937 from btcven/2020_04_23-flash-aux 
cc26xx_cc13xx: update VIMS/FLASH documentation
 2020-04-26 17:23:51 +02:00
Jean Pierre Dudey
81d0d7c1f8
cc26x2_cc13x2: update AUX domain documentation 
The following registers were updated:

- AIO_AIODIOx documentation
- AUX_TDC documentation
- AUX_EVCTL documentation
- AUX_SYSIF documentation
  - Fixed a copy/paste error in AUX_SYSIF definition.
  - Registers now match original names.
- AUX_TIMER01 documentation
- AUX_TIMER2 documentation
- AUX_SMPH documentation
- AUX_ANAIF documentation
- update ADI_4_AUX documentation
  - Added missing LPMBIAS register
- ADDI_SEM documentation

Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-04-26 09:35:26 -05:00
Francisco Molina
4d398ab09e
cpu/stm32f1: add unified rtt configuration 2020-04-24 08:57:04 +02:00
Jean Pierre Dudey
0aba7556d0
cc26xx_cc13xx: update VIMS/FLASH documentation 
Also i've fixed the register bank offsets, 0x4 was being added without
need.

Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-04-23 17:10:18 -05:00
Marian Buschsieweke
fdf955cfb2
Merge pull request #13899 from Hoernchen20/stm32f1_adc 
boards/blxxxpill: improve adc
 2020-04-22 23:07:26 +02:00
Hoernchen20
11618d32c0 cpu/stm32f1/periph_adc: Reduce power consumption 2020-04-22 21:08:20 +02:00
Hoernchen20
4e87682ba1 boards/common/blxxxpill: Add internal ADC lines 2020-04-22 21:08:20 +02:00
Leandro Lanzieri
db316c14a7
Merge pull request #13919 from benpicco/cpu/lpc2387-fix_rtc 
cpu/lpc2387: fix RTC leap year calculation
 2020-04-22 11:10:37 +02:00
Benjamin Valentin
4ee8d3f4d2 cpu/lpc2387: enable full rtc_normalize() for RTC 
The RTC actually makes use of the day of year / day of week fields,
so enable the calculation of those fields in rtc_normalize().
 2020-04-22 10:39:33 +02:00
Koen Zandberg
3e922f878a
Merge pull request #13875 from fjmolinas/pr_core_macros 
core/includes: add common macros file
 2020-04-21 15:32:51 +02:00
Francisco Molina
da90407572
cpu/esp_common/include: include common xtstr header 2020-04-21 15:10:55 +02:00
Francisco
3d8f71768c
Merge pull request #13846 from benpicco/Makefile-THISDIR 
Makefile.include: add $(MAKEFILEDIR) helper and use it
 2020-04-21 11:00:52 +02:00
Matthew Bradbury
ba51e90228 cpu/cc2538: Flush the RX FIFO (if overflowed) after a receive 2020-04-20 18:19:23 +01:00
Matthew Bradbury
bcfb437746 cpu/cc2538: Do not check XREG_RSSISTATbits for RSSI_VALID 2020-04-20 18:18:56 +01:00
Matthew Bradbury
ecfe4a4e8f cpu/cc2538: Check CRC of received message after reading message contents 2020-04-20 18:18:56 +01:00
Matthew Bradbury
fc0581056a cpu/cc2538: Check for a minimum length to read from a received frame 2020-04-20 18:18:56 +01:00
Matthew Bradbury
f0e48f0741 cpu/cc2538: Prevent underflow of the RX FIFO 2020-04-20 18:18:53 +01:00
Benjamin Valentin
370fff90a8 cpu/lpc2387: timer: use lpc2387_pclk_scale() 2020-04-19 15:32:42 +02:00
Martine Lenders
55a7010a0a
Merge pull request #13157 from nmeum/pr/fuzzing_tcp_only 
Add AFL-based fuzzing setup for network modules
 2020-04-18 10:54:14 +02:00
Gunar Schorcht
bb51fbb7ec cpu/esp32: fix GPIO32 and GPIO 33 as I2C pins 
GPIO32 and GPIO33 are used during boot to start an 32.768 kHz XTAL if it is connected to these GPIOs. If the 32.768 kHz XTAL is not connected, these pins can be used digital IO. However, the 32.678 kHz XTAL has to be disabled explicitly in this case. Furthermore, the handling of GPIOs greater than GPIO31 had to be fixed in I2C software implementation.
 2020-04-17 18:46:15 +02:00
benpicco
91200aa6ea
Merge pull request #13867 from btcven/2020_04_14-ccfg-fcfg1 
cc26xx_cc13xx: fix CCFG/FCFG1 register offsets
 2020-04-15 17:33:12 +02:00
benpicco
7aa62006e7
Merge pull request #13840 from btcven/2020_04_06-uart1 
cc26xx_cc13xx: fix UART1 initialization
 2020-04-15 17:15:24 +02:00
Benjamin Valentin
c1d05f07a5 cpu/kinetis: use $(MAKEFILEDIR) 2020-04-15 11:51:11 +02:00
Jean Pierre Dudey
e944638d3d
cc26x2_cc13x2: fix FCFG1 register offsets 
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-04-14 17:22:02 -05:00
Jean Pierre Dudey
cbcd7d58e7
cc26xx_cc13xx: fix CCFG offset on x2 variants 
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-04-14 17:15:56 -05:00
benpicco
b9fda5630e
Merge pull request #13851 from iosabi/vectors_cortexm 
Allow to define reserved fields in CortexM vector table.
 2020-04-14 23:18:29 +02:00
Akshai M
642fe16807 cpu/nrf52/include/nrf802154.h : Add Group 
Add CT Params to netdev group in Config for Doxygen
 2020-04-14 20:52:16 +05:30
Benjamin Valentin
cfe606b601 cpu/lpc2387: gpio: Don't discriminate between rising & falling pins 
The `test_irq()` function does not discriminate between rising and
falling pins, so there is no need to handle them separately.
 2020-04-12 21:31:42 +02:00
Benjamin Valentin
6233175f16 cpu/lpc2387: gpio: Fix interrupts on PORT2 
The calculation of `_state_index` is broken for `port = 2`

    _gpio_isr_map[n + (port<<1)];

Will not yield the right result. As a consequence, IRQs on Port 2
are not working.
The right thing here would be

    _gpio_isr_map[n + (port ? 32 : 0)];

But we might just re-using the `_isr_map_entry()` function.
Also only iterate as many times as there are set interrupt bits.
 2020-04-12 21:31:42 +02:00
iosabi
7e7b6e1cfe Allow to define reserved fields in CortexM vector table. 
The ARM CortexM vector table has some reserved fields which are used by
some manufacturers to store their custom image information. In
particular, NXP QN908X stores the checksum, Code Read Protection, image
type and boot block pointer in this region.

This patch allows the cpu and board modules to define the value of these
fields at build time by defining a macro.
 2020-04-10 10:37:41 +00:00