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3625 Commits

Author SHA1 Message Date
steffen
3ad71d5be0 atmega_common/gpio.c Fixes GPIO interrupt
fixes the GPIO_LOW interrupt on the atmega platform.
It results from trying to shift GPIO_LOW. Since it is 0, it is not shiftable and will not be set correctly.
There were more issues with the other flanks too, as they are 0b01 or 0b00. If 0b11 was set as a flank before it would not be able to switch to any other mode anymore. Now the bits get cleared before the new flank will be written.
2018-06-21 11:28:42 +02:00
Alexandre Abadie
5d633cd6d1 cpu/lm4f120: drop useless periph timer guards 2018-06-21 08:56:55 +02:00
Michel Rottleuthner
e4c405daf3 cpu/stm32l4: add adc support 2018-06-20 13:34:16 +02:00
Peter Kietzmann
6fd4009b89
Merge pull request #8957 from aabadie/pr/cpu/guard_lpc2387
cpu/lpc2387: remove useless periph file guard
2018-06-20 09:06:31 +02:00
Vincent Dupont
26cb3d8953 cpu/stm32f0: make use of CPU_LINE and STM32_FLASHSIZE 2018-06-19 14:31:23 +02:00
Vincent Dupont
e1ce7e5026 cpu/stm32_common: add STM32_FLASHSIZE constant 2018-06-19 14:31:23 +02:00
Vincent Dupont
d6d0f1a851 cpu/stm32f0: add custom CPU_LINE 2018-06-19 14:31:23 +02:00
Vincent Dupont
2e90eda456 cpu/stm32f4: make use of CPU_LINE_ variable 2018-06-19 14:22:48 +02:00
Vincent Dupont
4d7a195d33 cpu/stm32_common: add CPU_LINE_ variable 2018-06-19 14:22:46 +02:00
Marian Buschsieweke
1d0f90dcdf
cpu/lpc2387: Various fixes for GPIO driver
- Fixed documentation
- Use bitwise operation instead of multiplication and addition in `GPIO_PIN()`
- Allow GPIOs to be configured as input via `gpio_init()`
- Fixed bugs in `gpio_init_mux`:
    - `0x01 << ((pin & 31) * 2)` was used before to generate the bitmask, but
      this would shift by 62 to the left. Correct is `0x01 << ((pin & 15) * 2)`
      (See [datasheet](https://www.nxp.com/docs/en/user-guide/UM10211.pdf) at
      pages 156ff)
    - Only one of the two bits was cleared previously
- Changed strategy to access GPIO pins:
    - Previous strategy:
        - Set all bits in FIOMASK except the one for the pin to control to
          disable access to them
        - Set/clear/read all pins in the target GPIO port (but access to all but
          the target pin is ignored because of the applied FIOMASK)
    - New strategy:
        - Set/clear/read only the target pin
    - Advantages:
        - Only one access to a GPIO register instead of two
        - Proven approach: Access to GPIOs on lpc2387 is mostly done by
          accessing the GPIO registers directy (e.g. see the sht11 driver).
          Those accesses never touch the FIOMASK register
        - No unwanted side effects: Disabling all but one pin in a GPIO port
          without undoing that seems not to be a good idea
2018-06-18 09:10:25 +02:00
Josarn
91359631d5 cpu/atmega_common/thread_arch.c: uncrustified 2018-06-14 21:47:33 +02:00
Josarn
40c1839a8c cpu/atmega_common/periph/uart.c: uncrustified 2018-06-14 21:47:33 +02:00
Josarn
0e491861af cpu/atmega_common/periph/timer.c: uncrustified 2018-06-14 21:47:33 +02:00
Josarn
fe92771372 cpu/atmega_common/include/cpu.h: uncrustified 2018-06-14 21:47:33 +02:00
Josarn
9b631170cb cpu/atmega_common: uncrustified 2018-06-14 21:47:33 +02:00
Josarn
80b02e5268 cpu/atmega_common: exit_isr thread_yield 2018-06-14 21:47:33 +02:00
Alexandre Abadie
938677cc83 cpu*: fix doxygen grouping 2018-06-11 19:12:02 +02:00
Alexandre Abadie
4133908fe0 cpu/native: fix doxygen grouping 2018-06-11 19:12:02 +02:00
Juan Carrano
da85094b65 cpu/saml21: Fix possibly uninitialized variable in pm.c. 2018-06-11 18:35:41 +02:00
Simon Brummer
323a38819a native: Enforce safe strncpy usage in tap device setup 2018-06-10 17:16:46 +02:00
Hauke Petersen
e99010ac3e cpu/nrf5x: include nrfx.h compatibility header 2018-06-06 13:52:57 +02:00
Bas Stottelaar
0c47233f97 cpu: efm32: add support for non-standard UART modes. 2018-06-04 18:16:41 +02:00
Bas Stottelaar
c3161ce524 cpu/efm32: efm32pg12b: add support 2018-06-03 16:48:04 +02:00
Bas Stottelaar
9b3f8ca047 cpu/efm32: efm32pg12b: add vendor headers 2018-06-03 16:48:04 +02:00
Peter Kietzmann
b3ef51fb39
Merge pull request #9232 from maribu/lpc2387
cpu/lpc2387: Fixed invalid call to send_msg in lpc2387-mci.c
2018-06-01 08:11:25 +02:00
Francisco Acosta
7529133558
Merge pull request #9068 from aabadie/pr/stm32-common/fix_flashpage_m3
cpu/stm32-common: slightly rework flashpage driver and fix iotlab-m3
2018-05-30 17:50:20 +02:00
Francisco Acosta
1aed925ca8
Merge pull request #8951 from ZetaR60/RIOT_atmega_ext_int_clarity
cpu/atmega_common: external interrupt fix and refactor
2018-05-30 16:33:34 +02:00
Francisco Acosta
9a0f3469b7
Merge pull request #8930 from gebart/pr/kinetis-rtt-refactor
kinetis: Refactor RTT driver
2018-05-30 14:54:15 +02:00
Alexandre Abadie
600727453b cpu/stm32_common/flashpage: clear EOP bit
This was taken from STM32 Cube generated code
2018-05-30 14:14:29 +02:00
Alexandre Abadie
f7b61b6ac1 cpu/stm32_common/flashpage: force waiting for pending operations
Moving the while loop in a separate function ensures no ordering
    optimizations is applied silently by gcc.
    This commit fixes the flashpage not working on iotlab-m3.
2018-05-30 14:12:24 +02:00
Alexandre Abadie
c73ec5c00f cpu/stm32_common/periph: don't lock if flash is already locked 2018-05-30 14:09:17 +02:00
Alexandre Abadie
cb089a2f74 cpu/stm32_common/periph: cleanup flashpage
- improve debug messages
- fix missing space before comment
- use a comment instead of debug message (the same message is displayed by the function called after)
2018-05-30 14:09:17 +02:00
Marian Buschsieweke
2c901ff181
cpu/lpc2387: Fixed invalid call to send_msg in lpc2387-mci.c
At `lpc2387-mci.c:383` in `send_cmd()` an `assert()` enforces that parameter
`buff` is not `NULL`. At `lpc2387-mci.c:538` in `mci_initialize()` `send_cmd()`
was called with `buff==NULL`.
2018-05-30 09:09:22 +02:00
kenrabold
db4d67c4fd make: add hifive1 to BOARD_INSUFFICIENT_MEMORY
Added HiFive1 to BOARD_INSUFFICIENT_MEMORY list for examples and tests that are too big to fit

build: fixed missing syscall and cpuid failures

Added missing syscall stubs for nanostubs and fixed compile error with cpuid periph

build: fixed whitespace error

build: add hifive1 to more BOARD_INSUFFICIENT_MEMORY

doc: fixed doxygen warnings

Addressed Doxygen warnings in source file comments

doc: more doxygen fixes

doc: even more doxygen fixes

doc: more changes

build: fix pedantic and rdci_simple build failures

make: exclude lua
2018-05-29 16:27:53 -07:00
kenrabold
7d1d5e77d8 cpu/fe310: add RISC-V cpu FE310
New CPU FE310 from SiFive based on RISC-V architecture

build: add makefile for RISC-V builds

Makefile for builds using RISC-V tools
2018-05-29 15:21:45 -07:00
Matthew Blue
0b2d620161 cpu/atmega328p: external interrupt refactor 2018-05-29 11:24:16 -04:00
Matthew Blue
6ea326112d cpu/atmega256rfr2: external interrupt refactor 2018-05-29 11:24:16 -04:00
Matthew Blue
737c46367a cpu/atmega2560: external interrupt refactor 2018-05-29 11:24:15 -04:00
Matthew Blue
327bf09d20 cpu/atmega1284p: external interrupt refactor 2018-05-29 11:24:15 -04:00
Matthew Blue
a61aff6404 cpu/atmega1281: external interrupt refactor 2018-05-29 11:24:15 -04:00
Matthew Blue
533388d3ae cpu/atmega_common: external interrupt fix and refactor 2018-05-29 11:24:15 -04:00
Francisco Acosta
6e484f7aed
Merge pull request #8814 from gebart/pr/kinetis-periph-timer-tfc
cpu/kinetis: Refactor LPTMR timer implementation
2018-05-29 15:54:11 +02:00
Loïc Dauphin
b7a8ba73a9
Merge pull request #8933 from gebart/pr/kinetis-pit-refactor
kinetis: Refactor PIT timer driver implementation
2018-05-29 11:09:55 +02:00
Matthew Blue
dfa8fb919d sys/timex: fix incompatible atmega time.h 2018-05-28 13:04:55 -04:00
Matthew Blue
442634728f cpu/atmega_common: add struct timespec to time.h 2018-05-28 13:04:55 -04:00
Matthew Blue
b597700a67 cpu/atmega_common: ignore format of avr-libc in CI 2018-05-28 13:04:55 -04:00
Matthew Blue
2a92d480ea cpu/atmega_common: Use updated time.h from avr-libc-2.0.0 2018-05-28 13:04:55 -04:00
Bas Stottelaar
840de5139b cpu: efm32: fix for cpp support. 2018-05-25 20:36:21 +02:00
Joakim Nohlgård
9657274d0d
Merge pull request #9147 from gebart/pr/kinetis-z-gpio-irqn
kinetis: GPIO: Enable the correct IRQn on CM0+
2018-05-25 00:50:59 +02:00
Joakim Nohlgård
09e0e8953d kinetis: GPIO: Enable the correct IRQn on CM0+ 2018-05-24 23:54:56 +02:00