Alexandre Abadie
53ac29aca4
Merge pull request #14887 from bergzand/pr/fe310/plic_periph
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fe310: Add custom PLIC driver as peripheral
2020-08-31 21:25:03 +02:00
Koen Zandberg
bef82edf43
fe310: Adapt peripherals to use the plic driver
2020-08-31 16:26:43 +02:00
Koen Zandberg
3180a11b51
fe310: Add PLIC peripheral driver
2020-08-31 16:26:42 +02:00
Koen Zandberg
889ea15936
fe310: Use read-modify-store instruction on GPIO
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The rv32imac supports the A (atomic) extensions containing
read-modify-store operations. This commit modifies the GPIO code to use
these for all bitwise operations. The atomic operations are emitted with
relaxed ordering as they do not require multiprocessor synchronization.
This decreases the duration of the gpio operations from 59 ns to 50 ns
per call. depending a bit on the type of operation.
2020-08-29 09:24:02 +02:00
Francisco Molina
442b11d0ee
cpu/fe310: add unified rtt configuration
2020-08-12 14:46:59 +02:00
Alexandre Abadie
ee3fc27e96
cpu/fe310: implement driver for watchdog
2020-04-07 14:37:55 +02:00
Sören Tempel
bd2f5fe110
fe310: fix power management configuration
2020-01-30 10:43:01 +01:00
Francisco
f76f7c73ce
Merge pull request #12957 from aabadie/pr/cpu/fe310_spi
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cpu/fe310: add spi peripheral driver
2020-01-14 10:54:47 +01:00
Tristan Bruns
532cdc64ff
cpu/fe310: implement SPI
2020-01-11 13:06:39 +01:00
Alexandre Abadie
298d573280
cpu/fe310: provide i2c driver
2020-01-11 13:06:10 +01:00
Alexandre Abadie
3f29eb9efb
cpu/fe310: use CLOCK_CORECLOCK macro to get cpu freq
2020-01-10 16:41:33 +01:00
4eba1427d2
cpu/fe310: uart_init(): drain RX fifo before enabling RX IRQ
2020-01-07 13:16:02 +01:00
e2f88abe63
cpu/fe310: periph_uart: only call rx_cb if set
2020-01-07 13:14:08 +01:00
Alexandre Abadie
e5c64c739a
cpu/fe310: rework uart driver implem/config
2019-12-20 15:22:09 +01:00
Francois Berder
4a31f94cfc
many typo fixes
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Signed-off-by: Francois Berder <18538310+francois-berder@users.noreply.github.com>
2019-11-23 22:39:07 +01:00
kenrabold
547ebd1b27
cpu/fe310: use WFI to wait for SW interrupt
2019-09-16 09:32:27 -07:00
38cc72d0e0
Merge pull request #11046 from kaspar030/reset_fe310_timer
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cpu/fe310: periph/timer: reset counter in timer_init()
2019-04-09 15:50:19 +02:00
847dc3d55c
cpu/fe310: implement pm_reset() using watchdog
2019-03-12 11:49:02 +01:00
1bc82c2378
cpu/fe310: periph/timer: reset counter in timer_init()
2019-02-21 11:34:59 +01:00
Martine Lenders
769bf572a0
fe310: mark closing #endif for MODULE_PERIPH_GPIO_IRQ
2018-10-09 15:11:00 +02:00
Martine Lenders
4e92c2a424
Merge pull request #10007 from haukepetersen/fix_gpioirq_fe310
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cpu/fe310/gpio: use gpio_irq feature
2018-10-09 14:22:43 +02:00
smlng
59e299635b
cppcheck: add/correct reason for cppcheck-suppress
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Adding and correcting description/rational on why certain cppcheck
warnings or errors are intentionally suppressed.
2018-09-25 12:03:58 +02:00
Hauke Petersen
be94b99eda
cpu/fe310/gpio: use gpio_irq feature
2018-09-21 08:18:14 +02:00
kenrabold
db4d67c4fd
make: add hifive1 to BOARD_INSUFFICIENT_MEMORY
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Added HiFive1 to BOARD_INSUFFICIENT_MEMORY list for examples and tests that are too big to fit
build: fixed missing syscall and cpuid failures
Added missing syscall stubs for nanostubs and fixed compile error with cpuid periph
build: fixed whitespace error
build: add hifive1 to more BOARD_INSUFFICIENT_MEMORY
doc: fixed doxygen warnings
Addressed Doxygen warnings in source file comments
doc: more doxygen fixes
doc: even more doxygen fixes
doc: more changes
build: fix pedantic and rdci_simple build failures
make: exclude lua
2018-05-29 16:27:53 -07:00
kenrabold
7d1d5e77d8
cpu/fe310: add RISC-V cpu FE310
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New CPU FE310 from SiFive based on RISC-V architecture
build: add makefile for RISC-V builds
Makefile for builds using RISC-V tools
2018-05-29 15:21:45 -07:00
