mirror of
https://github.com/RIOT-OS/RIOT.git
synced 2025-12-24 05:53:49 +01:00
Kaspar Schleiser
8afaf11bb5
/* Port 1:
* P1.0 is not assigned by default
* P1.1 is the bootstrap-loader (BSL) TX pin -> input, special function, default to GND
* THIS PIN MUST *NEVER* BE USED IN NORMAL EXECUTION, SINCE IT INTERFERES WITH UART0 !!!
* P1.2 receives the FIFOP interrupt from CC2420 -> input, GPIO, default to GND
* P1.3 receives the FIFO/GIO0 interrupt from CC2420 -> input, GPIO, default to GND
* P1.4 receives the CCA/GIO1 signal from CC2420 -> input, GPIO, default to GND
* P1.5 is wired to Vcc -> input, GPIO, default to Vcc
* P1.6 receives interrupt INT1 from accelerometer -> input, GPIO, default to GND
* P1.7 receives interrupt INT2 from accelerometer -> input, GPIO, default to GND
*/
(test starts indexing at 0)
30 lines
639 B
Makefile
30 lines
639 B
Makefile
include ../Makefile.tests_common
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FEATURES_REQUIRED = periph_gpio
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FEATURES_OPTIONAL = periph_gpio_irq
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USEMODULE += shell
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USEMODULE += shell_commands
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USEMODULE += benchmark
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BOARDS_BENCH_PORT_1 = \
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slstk3402a \
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z1 \
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#
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# port 0 pins are used for serial output on these boards, e.g.: on slstk3402a
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# PA5 (or port 0, pin 5) is used to control the BC enabling serial output,
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# therefore test on port 1.
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ifneq (,$(filter $(BOARD),$(BOARDS_BENCH_PORT_1)))
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PORT_UNDER_TEST ?= 1
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else
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PORT_UNDER_TEST ?= 0
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endif
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include $(RIOTBASE)/Makefile.include
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$(call target-export-variables,test,PORT_UNDER_TEST)
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bench:
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tests/02-bench.py
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