mirror of
https://github.com/RIOT-OS/RIOT.git
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8cfc42b562
This commit allows to share GPIO, Timers and UARTs driver across SAM3/SAM4s MCUs as they relies on the same IPs Signed-off-by: dylad <dylan.laduranty@mesotic.com>
150 lines
4.1 KiB
C
150 lines
4.1 KiB
C
/*
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* Copyright (C) 2015 Freie Universität Berlin
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* 2015 Hamburg University of Applied Sciences
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_sam3
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* @{
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*
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* @file
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* @brief CPU specific definitions for internal peripheral handling
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Tobias Fredersdorf <tobias.fredersdorf@haw-hamburg.de>
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*
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*/
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#ifndef PERIPH_CPU_H
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#define PERIPH_CPU_H
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#include "periph_cpu_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Declare needed generic SPI functions
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* @{
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*/
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#define PERIPH_SPI_NEEDS_INIT_CS
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#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
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#define PERIPH_SPI_NEEDS_TRANSFER_REG
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#define PERIPH_SPI_NEEDS_TRANSFER_REGS
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/** @} */
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/**
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* @brief Length of the CPU_ID in octets
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*/
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#define CPUID_LEN (16U)
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/**
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* @name RTT configuration
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* @{
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*/
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#define RTT_MAX_VALUE (0xffffffff)
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#define RTT_CLOCK_FREQUENCY (CHIP_FREQ_XTAL_32K) /* in Hz */
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#define RTT_MIN_FREQUENCY (1) /* in Hz */
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#define RTT_MAX_FREQUENCY (RTT_CLOCK_FREQUENCY) /* in Hz */
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/** @} */
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/**
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* @name ADC configuration, valid for all boards using this CPU
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*
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* The sam3 has a fixed mapping of ADC pins and a fixed number of ADC channels,
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* so this ADC configuration is valid for all boards using this CPU. No need for
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* any board specific configuration.
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*/
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#define ADC_NUMOF (16U)
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/**
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* @brief DAC configuration, valid for all boards using this CPU
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*
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* The sam3 has a fixed mapping of DAC pins and a fixed number of DAC channels,
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* so this DAC configuration is valid for all boards using this CPU. No need for
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* any board specific configuration.
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*
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* The sam3's DAC channels are mapped to the following fixed pins:
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* - line 0 (ch0): PB15
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* - line 1 (ch1): PB16
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*/
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#define DAC_NUMOF (2U)
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#ifndef DOXYGEN
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/**
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* @brief Override default SPI modes
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* @{
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*/
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#define HAVE_SPI_MODE_T
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typedef enum {
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SPI_MODE_0 = (SPI_CSR_NCPHA), /**< CPOL=0, CPHA=0 */
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SPI_MODE_1 = (0), /**< CPOL=0, CPHA=1 */
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SPI_MODE_2 = (SPI_CSR_CPOL | SPI_CSR_NCPHA), /**< CPOL=1, CPHA=0 */
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SPI_MODE_3 = (SPI_CSR_CPOL) /**< CPOL=1, CPHA=1 */
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} spi_mode_t;
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/** @} */
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/**
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* @brief Override default SPI clock values
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* @{
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*/
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#define HAVE_SPI_CLK_T
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typedef enum {
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SPI_CLK_100KHZ = (100000), /**< 100KHz */
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SPI_CLK_400KHZ = (400000), /**< 400KHz */
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SPI_CLK_1MHZ = (1000000), /**< 1MHz */
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SPI_CLK_5MHZ = (5000000), /**< 5MHz */
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SPI_CLK_10MHZ = (10000000) /**< 10MHz */
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} spi_clk_t;
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/** @} */
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#endif /* ndef DOXYGEN */
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#ifndef DOXYGEN
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/**
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* @brief Override ADC resolution values
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* @{
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*/
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#define HAVE_ADC_RES_T
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typedef enum {
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ADC_RES_6BIT = 0x1, /**< not applicable */
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ADC_RES_8BIT = 0x2, /**< not applicable */
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ADC_RES_10BIT = ADC_MR_LOWRES_BITS_10, /**< ADC resolution: 10 bit */
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ADC_RES_12BIT = ADC_MR_LOWRES_BITS_12, /**< ADC resolution: 12 bit */
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ADC_RES_14BIT = 0x4, /**< not applicable */
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ADC_RES_16BIT = 0x8 /**< not applicable */
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} adc_res_t;
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/** @} */
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#endif /* ndef DOXYGEN */
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/**
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* @brief PWM channel configuration data
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*/
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typedef struct {
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gpio_t pin; /**< GPIO pin connected to the channel */
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uint8_t hwchan; /**< the HW channel used for a logical channel */
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} pwm_chan_conf_t;
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/**
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* @brief SPI configuration data
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*/
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typedef struct {
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Spi *dev; /**< SPI module to use */
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uint8_t id; /**< corresponding ID of that module */
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gpio_t clk; /**< pin mapped to the CLK line */
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gpio_t mosi; /**< pin mapped to the MOSI line */
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gpio_t miso; /**< pin mapped to the MISO line */
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gpio_mux_t mux; /**< pin MUX setting */
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} spi_conf_t;
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CPU_H */
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/** @} */
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