Merge pull request #9728 from aabadie/pr/boards/stm32_common_i2c
boards: factorize some nucleo f4/f7/l4 i2c configuration
This commit is contained in:
Kevin "Bear Puncher" Weiss
GitHub
commit
02ec3845de
69
boards/common/stm32/include/cfg_i2c1_pb8_pb9.h
Normal file
69
boards/common/stm32/include/cfg_i2c1_pb8_pb9.h
Normal file
@ -0,0 +1,69 @@
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/*
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* Copyright (C) 2018 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
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||||
* directory for more details.
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*/
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/**
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* @ingroup boards_common_stm32
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* @{
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*
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* @file
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* @brief Common configuration for STM32 I2C
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*
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef CFG_I2C1_PB8_PB9_H
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#define CFG_I2C1_PB8_PB9_H
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name I2C configuration
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* @{
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*/
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static const i2c_conf_t i2c_config[] = {
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{
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.dev = I2C1,
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.speed = I2C_SPEED_NORMAL,
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.scl_pin = GPIO_PIN(PORT_B, 8),
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.sda_pin = GPIO_PIN(PORT_B, 9),
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.scl_af = GPIO_AF4,
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.sda_af = GPIO_AF4,
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.bus = APB1,
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#if CPU_FAM_STM32F4
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.rcc_mask = RCC_APB1ENR_I2C1EN,
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.clk = CLOCK_APB1,
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.irqn = I2C1_EV_IRQn,
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#elif CPU_FAM_STM32L4
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.rcc_mask = RCC_APB1ENR1_I2C1EN,
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.irqn = I2C1_ER_IRQn,
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#elif CPU_FAM_STM32F7
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.rcc_mask = RCC_APB1ENR_I2C1EN,
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.irqn = I2C1_ER_IRQn,
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#endif
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}
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};
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#if CPU_FAM_STM32F4
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#define I2C_0_ISR isr_i2c1_ev
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#elif CPU_FAM_STM32L4 || CPU_FAM_STM32F7
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#define I2C_0_ISR isr_i2c1_er
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#endif
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#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* CFG_I2C1_PB8_PB9_H */
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/** @} */
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77
boards/common/stm32/include/f4/cfg_clock_100_8_1.h
Normal file
77
boards/common/stm32/include/f4/cfg_clock_100_8_1.h
Normal file
@ -0,0 +1,77 @@
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/*
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* Copyright (C) 2018 Freie Universität Berlin
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* 2017 OTA keys S.A.
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* 2018 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_common_stm32
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* @{
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*
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* @file
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* @brief Configure STM32F4 clock to 100MHz using PLL
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Vincent Dupont <vincent@otakeys.com>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef F4_CFG_CLOCK_100_8_1_H
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#define F4_CFG_CLOCK_100_8_1_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock settings
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*
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* @note This is auto-generated from
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* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
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* @{
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*/
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/* give the target core clock (HCLK) frequency [in Hz],
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* maximum: 100MHz */
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#define CLOCK_CORECLOCK (100000000U)
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/* 0: no external high speed crystal available
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* else: actual crystal frequency [in Hz] */
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#define CLOCK_HSE (8000000U)
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz) */
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#define CLOCK_LSE (1)
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/* peripheral clock setup */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
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/* Main PLL factors */
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#define CLOCK_PLL_M (4)
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#define CLOCK_PLL_N (200)
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#define CLOCK_PLL_P (4)
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#define CLOCK_PLL_Q (0)
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/* PLL I2S configuration */
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#define CLOCK_ENABLE_PLL_I2S (1)
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#define CLOCK_PLL_I2S_SRC (0)
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#define CLOCK_PLL_I2S_M (4)
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#define CLOCK_PLL_I2S_N (216)
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#define CLOCK_PLL_I2S_P (0)
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#define CLOCK_PLL_I2S_Q (9)
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/* Use alternative source for 48MHz clock */
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#define CLOCK_USE_ALT_48MHZ (1)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* F4_CFG_CLOCK_100_8_1_H */
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/** @} */
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64
boards/common/stm32/include/f4/cfg_clock_84_8_1.h
Normal file
64
boards/common/stm32/include/f4/cfg_clock_84_8_1.h
Normal file
@ -0,0 +1,64 @@
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/*
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* Copyright (C) 2018 Freie Universität Berlin
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* 2018 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_common_stm32
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* @{
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*
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* @file
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* @brief Configure STM32F4 clock to 84MHz using PLL
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef F4_CFG_CLOCK_84_8_1_H
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#define F4_CFG_CLOCK_84_8_1_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock settings
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*
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* @note This is auto-generated from
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* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
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* @{
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*/
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/* give the target core clock (HCLK) frequency [in Hz],
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* maximum: 84MHz */
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#define CLOCK_CORECLOCK (84000000U)
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/* 0: no external high speed crystal available
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* else: actual crystal frequency [in Hz] */
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#define CLOCK_HSE (8000000U)
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz) */
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#define CLOCK_LSE (1)
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/* peripheral clock setup */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 42MHz */
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 84MHz */
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
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/* Main PLL factors */
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#define CLOCK_PLL_M (4)
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#define CLOCK_PLL_N (168)
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#define CLOCK_PLL_P (4)
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#define CLOCK_PLL_Q (7)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* F4_CFG_CLOCK_84_8_1_H */
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/** @} */
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64
boards/common/stm32/include/f4/cfg_clock_96_8_1.h
Normal file
64
boards/common/stm32/include/f4/cfg_clock_96_8_1.h
Normal file
@ -0,0 +1,64 @@
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/*
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* Copyright (C) 2018 Freie Universität Berlin
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* 2018 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_common_stm32
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* @{
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*
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* @file
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* @brief Configure STM32F4 clock to 96MHz using PLL
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef F4_CFG_CLOCK_96_8_1_H
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#define F4_CFG_CLOCK_96_8_1_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock settings
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*
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* @note This is auto-generated from
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* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
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* @{
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*/
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/* give the target core clock (HCLK) frequency [in Hz],
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* maximum: 100MHz */
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#define CLOCK_CORECLOCK (96000000U)
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/* 0: no external high speed crystal available
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* else: actual crystal frequency [in Hz] */
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#define CLOCK_HSE (8000000U)
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz) */
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#define CLOCK_LSE (1)
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/* peripheral clock setup */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
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/* Main PLL factors */
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#define CLOCK_PLL_M (4)
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#define CLOCK_PLL_N (192)
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#define CLOCK_PLL_P (4)
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#define CLOCK_PLL_Q (8)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* F4_CFG_CLOCK_96_8_1_H */
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/** @} */
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@ -22,42 +22,13 @@
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#include "f4/cfg_clock_84_8_1.h"
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#include "cfg_i2c1_pb8_pb9.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock settings
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*
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* @note This is auto-generated from
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* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
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* @{
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*/
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/* give the target core clock (HCLK) frequency [in Hz],
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* maximum: 84MHz */
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#define CLOCK_CORECLOCK (84000000U)
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/* 0: no external high speed crystal available
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* else: actual crystal frequency [in Hz] */
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#define CLOCK_HSE (8000000U)
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz) */
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#define CLOCK_LSE (1)
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/* peripheral clock setup */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 42MHz */
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 84MHz */
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
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/* Main PLL factors */
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#define CLOCK_PLL_M (4)
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#define CLOCK_PLL_N (168)
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#define CLOCK_PLL_P (4)
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#define CLOCK_PLL_Q (7)
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/** @} */
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/**
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* @name Timer configuration
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* @{
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@ -249,31 +220,6 @@ static const spi_conf_t spi_config[] = {
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#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
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/** @} */
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/**
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* @name I2C configuration
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* @{
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*/
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static const i2c_conf_t i2c_config[] = {
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{
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.dev = I2C1,
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.speed = I2C_SPEED_NORMAL,
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.scl_pin = GPIO_PIN(PORT_B, 8),
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.sda_pin = GPIO_PIN(PORT_B, 9),
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.scl_af = GPIO_AF4,
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.sda_af = GPIO_AF4,
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.bus = APB1,
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.rcc_mask = RCC_APB1ENR_I2C1EN,
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.clk = CLOCK_APB1,
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.irqn = I2C1_EV_IRQn
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}
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};
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#define I2C_0_ISR isr_i2c1_ev
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#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
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/** @} */
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/**
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* @name ADC configuration
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*
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@ -22,42 +22,13 @@
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#define PERIPH_CONF_H
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|
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#include "periph_cpu.h"
|
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#include "f4/cfg_clock_96_8_1.h"
|
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#include "cfg_i2c1_pb8_pb9.h"
|
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|
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#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
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/**
|
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* @name Clock settings
|
||||
*
|
||||
* @note This is auto-generated from
|
||||
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
|
||||
* @{
|
||||
*/
|
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/* give the target core clock (HCLK) frequency [in Hz],
|
||||
* maximum: 100MHz */
|
||||
#define CLOCK_CORECLOCK (96000000U)
|
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/* 0: no external high speed crystal available
|
||||
* else: actual crystal frequency [in Hz] */
|
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#define CLOCK_HSE (8000000U)
|
||||
/* 0: no external low speed crystal available,
|
||||
* 1: external crystal available (always 32.768kHz) */
|
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#define CLOCK_LSE (1)
|
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/* peripheral clock setup */
|
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
|
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
|
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */
|
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
|
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */
|
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
|
||||
|
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/* Main PLL factors */
|
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#define CLOCK_PLL_M (4)
|
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#define CLOCK_PLL_N (192)
|
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#define CLOCK_PLL_P (4)
|
||||
#define CLOCK_PLL_Q (8)
|
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/** @} */
|
||||
|
||||
/**
|
||||
* @name Timer configuration
|
||||
* @{
|
||||
@ -178,30 +149,6 @@ static const spi_conf_t spi_config[] = {
|
||||
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name I2C configuration
|
||||
* @{
|
||||
*/
|
||||
static const i2c_conf_t i2c_config[] = {
|
||||
{
|
||||
.dev = I2C1,
|
||||
.speed = I2C_SPEED_NORMAL,
|
||||
.scl_pin = GPIO_PIN(PORT_B, 8),
|
||||
.sda_pin = GPIO_PIN(PORT_B, 9),
|
||||
.scl_af = GPIO_AF4,
|
||||
.sda_af = GPIO_AF4,
|
||||
.bus = APB1,
|
||||
.rcc_mask = RCC_APB1ENR_I2C1EN,
|
||||
.clk = CLOCK_APB1,
|
||||
.irqn = I2C1_EV_IRQn
|
||||
}
|
||||
};
|
||||
|
||||
#define I2C_0_ISR isr_i2c1_ev
|
||||
|
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#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name ADC configuration
|
||||
*
|
||||
|
||||
@ -22,42 +22,13 @@
|
||||
#define PERIPH_CONF_H
|
||||
|
||||
#include "periph_cpu.h"
|
||||
#include "f4/cfg_clock_96_8_1.h"
|
||||
#include "cfg_i2c1_pb8_pb9.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @name Clock settings
|
||||
*
|
||||
* @note This is auto-generated from
|
||||
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
|
||||
* @{
|
||||
*/
|
||||
/* give the target core clock (HCLK) frequency [in Hz],
|
||||
* maximum: 100MHz */
|
||||
#define CLOCK_CORECLOCK (96000000U)
|
||||
/* 0: no external high speed crystal available
|
||||
* else: actual crystal frequency [in Hz] */
|
||||
#define CLOCK_HSE (8000000U)
|
||||
/* 0: no external low speed crystal available,
|
||||
* 1: external crystal available (always 32.768kHz) */
|
||||
#define CLOCK_LSE (1)
|
||||
/* peripheral clock setup */
|
||||
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
|
||||
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
|
||||
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */
|
||||
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
|
||||
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */
|
||||
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
|
||||
|
||||
/* Main PLL factors */
|
||||
#define CLOCK_PLL_M (4)
|
||||
#define CLOCK_PLL_N (192)
|
||||
#define CLOCK_PLL_P (4)
|
||||
#define CLOCK_PLL_Q (8)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Timer configuration
|
||||
* @{
|
||||
@ -208,30 +179,6 @@ static const spi_conf_t spi_config[] = {
|
||||
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name I2C configuration
|
||||
* @{
|
||||
*/
|
||||
static const i2c_conf_t i2c_config[] = {
|
||||
{
|
||||
.dev = I2C1,
|
||||
.speed = I2C_SPEED_NORMAL,
|
||||
.scl_pin = GPIO_PIN(PORT_B, 8),
|
||||
.sda_pin = GPIO_PIN(PORT_B, 9),
|
||||
.scl_af = GPIO_AF4,
|
||||
.sda_af = GPIO_AF4,
|
||||
.bus = APB1,
|
||||
.rcc_mask = RCC_APB1ENR_I2C1EN,
|
||||
.clk = CLOCK_APB1,
|
||||
.irqn = I2C1_EV_IRQn
|
||||
}
|
||||
};
|
||||
|
||||
#define I2C_0_ISR isr_i2c1_ev
|
||||
|
||||
#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name ADC configuration
|
||||
*
|
||||
|
||||
@ -24,53 +24,13 @@
|
||||
#define PERIPH_CONF_H
|
||||
|
||||
#include "periph_cpu.h"
|
||||
#include "f4/cfg_clock_100_8_1.h"
|
||||
#include "cfg_i2c1_pb8_pb9.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @name Clock settings
|
||||
*
|
||||
* @note This is auto-generated from
|
||||
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
|
||||
* @{
|
||||
*/
|
||||
/* give the target core clock (HCLK) frequency [in Hz],
|
||||
* maximum: 100MHz */
|
||||
#define CLOCK_CORECLOCK (100000000U)
|
||||
/* 0: no external high speed crystal available
|
||||
* else: actual crystal frequency [in Hz] */
|
||||
#define CLOCK_HSE (8000000U)
|
||||
/* 0: no external low speed crystal available,
|
||||
* 1: external crystal available (always 32.768kHz) */
|
||||
#define CLOCK_LSE (1)
|
||||
/* peripheral clock setup */
|
||||
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
|
||||
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
|
||||
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */
|
||||
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
|
||||
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */
|
||||
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
|
||||
|
||||
/* Main PLL factors */
|
||||
#define CLOCK_PLL_M (4)
|
||||
#define CLOCK_PLL_N (200)
|
||||
#define CLOCK_PLL_P (4)
|
||||
#define CLOCK_PLL_Q (0)
|
||||
|
||||
/* PLL I2S configuration */
|
||||
#define CLOCK_ENABLE_PLL_I2S (1)
|
||||
#define CLOCK_PLL_I2S_SRC (0)
|
||||
#define CLOCK_PLL_I2S_M (4)
|
||||
#define CLOCK_PLL_I2S_N (216)
|
||||
#define CLOCK_PLL_I2S_P (0)
|
||||
#define CLOCK_PLL_I2S_Q (9)
|
||||
|
||||
/* Use alternative source for 48MHz clock */
|
||||
#define CLOCK_USE_ALT_48MHZ (1)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Timer configuration
|
||||
* @{
|
||||
@ -219,30 +179,6 @@ static const spi_conf_t spi_config[] = {
|
||||
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name I2C configuration
|
||||
* @{
|
||||
*/
|
||||
static const i2c_conf_t i2c_config[] = {
|
||||
{
|
||||
.dev = I2C1,
|
||||
.speed = I2C_SPEED_NORMAL,
|
||||
.scl_pin = GPIO_PIN(PORT_B, 8),
|
||||
.sda_pin = GPIO_PIN(PORT_B, 9),
|
||||
.scl_af = GPIO_AF4,
|
||||
.sda_af = GPIO_AF4,
|
||||
.bus = APB1,
|
||||
.rcc_mask = RCC_APB1ENR_I2C1EN,
|
||||
.clk = CLOCK_APB1,
|
||||
.irqn = I2C1_EV_IRQn
|
||||
}
|
||||
};
|
||||
|
||||
#define I2C_0_ISR isr_i2c1_ev
|
||||
|
||||
#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name ADC configuration
|
||||
*
|
||||
|
||||
@ -24,53 +24,13 @@
|
||||
#define PERIPH_CONF_H
|
||||
|
||||
#include "periph_cpu.h"
|
||||
#include "f4/cfg_clock_100_8_1.h"
|
||||
#include "cfg_i2c1_pb8_pb9.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @name Clock settings
|
||||
*
|
||||
* @note This is auto-generated from
|
||||
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
|
||||
* @{
|
||||
*/
|
||||
/* give the target core clock (HCLK) frequency [in Hz],
|
||||
* maximum: 100MHz */
|
||||
#define CLOCK_CORECLOCK (100000000U)
|
||||
/* 0: no external high speed crystal available
|
||||
* else: actual crystal frequency [in Hz] */
|
||||
#define CLOCK_HSE (8000000U)
|
||||
/* 0: no external low speed crystal available,
|
||||
* 1: external crystal available (always 32.768kHz) */
|
||||
#define CLOCK_LSE (1)
|
||||
/* peripheral clock setup */
|
||||
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
|
||||
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
|
||||
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */
|
||||
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
|
||||
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */
|
||||
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
|
||||
|
||||
/* Main PLL factors */
|
||||
#define CLOCK_PLL_M (4)
|
||||
#define CLOCK_PLL_N (200)
|
||||
#define CLOCK_PLL_P (4)
|
||||
#define CLOCK_PLL_Q (0)
|
||||
|
||||
/* PLL I2S configuration */
|
||||
#define CLOCK_ENABLE_PLL_I2S (1)
|
||||
#define CLOCK_PLL_I2S_SRC (0)
|
||||
#define CLOCK_PLL_I2S_M (4)
|
||||
#define CLOCK_PLL_I2S_N (216)
|
||||
#define CLOCK_PLL_I2S_P (0)
|
||||
#define CLOCK_PLL_I2S_Q (9)
|
||||
|
||||
/* Use alternative source for 48MHz clock */
|
||||
#define CLOCK_USE_ALT_48MHZ (1)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name DMA streams configuration
|
||||
* @{
|
||||
@ -248,30 +208,6 @@ static const spi_conf_t spi_config[] = {
|
||||
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name I2C configuration
|
||||
* @{
|
||||
*/
|
||||
static const i2c_conf_t i2c_config[] = {
|
||||
{
|
||||
.dev = I2C1,
|
||||
.speed = I2C_SPEED_NORMAL,
|
||||
.scl_pin = GPIO_PIN(PORT_B, 8),
|
||||
.sda_pin = GPIO_PIN(PORT_B, 9),
|
||||
.scl_af = GPIO_AF4,
|
||||
.sda_af = GPIO_AF4,
|
||||
.bus = APB1,
|
||||
.rcc_mask = RCC_APB1ENR_I2C1EN,
|
||||
.clk = CLOCK_APB1,
|
||||
.irqn = I2C1_EV_IRQn
|
||||
}
|
||||
};
|
||||
|
||||
#define I2C_0_ISR isr_i2c1_ev
|
||||
|
||||
#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name ADC configuration
|
||||
*
|
||||
|
||||
@ -23,6 +23,7 @@
|
||||
|
||||
#include "periph_cpu.h"
|
||||
#include "f4/cfg_clock_168_8_1.h"
|
||||
#include "cfg_i2c1_pb8_pb9.h"
|
||||
#include "cfg_spi_divtable.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
@ -157,30 +158,6 @@ static const spi_conf_t spi_config[] = {
|
||||
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name I2C configuration
|
||||
* @{
|
||||
*/
|
||||
static const i2c_conf_t i2c_config[] = {
|
||||
{
|
||||
.dev = I2C1,
|
||||
.speed = I2C_SPEED_NORMAL,
|
||||
.scl_pin = GPIO_PIN(PORT_B, 8),
|
||||
.sda_pin = GPIO_PIN(PORT_B, 9),
|
||||
.scl_af = GPIO_AF4,
|
||||
.sda_af = GPIO_AF4,
|
||||
.bus = APB1,
|
||||
.rcc_mask = RCC_APB1ENR_I2C1EN,
|
||||
.clk = CLOCK_APB1,
|
||||
.irqn = I2C1_EV_IRQn
|
||||
}
|
||||
};
|
||||
|
||||
#define I2C_0_ISR isr_i2c1_ev
|
||||
|
||||
#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name ADC configuration
|
||||
*
|
||||
|
||||
@ -23,6 +23,7 @@
|
||||
|
||||
#include "periph_cpu.h"
|
||||
#include "f4/cfg_clock_180_8_1.h"
|
||||
#include "cfg_i2c1_pb8_pb9.h"
|
||||
#include "cfg_spi_divtable.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
@ -213,31 +214,6 @@ static const spi_conf_t spi_config[] = {
|
||||
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
|
||||
/** @} */
|
||||
|
||||
|
||||
/**
|
||||
* @name I2C configuration
|
||||
* @{
|
||||
*/
|
||||
static const i2c_conf_t i2c_config[] = {
|
||||
{
|
||||
.dev = I2C1,
|
||||
.speed = I2C_SPEED_NORMAL,
|
||||
.scl_pin = GPIO_PIN(PORT_B, 8),
|
||||
.sda_pin = GPIO_PIN(PORT_B, 9),
|
||||
.scl_af = GPIO_AF4,
|
||||
.sda_af = GPIO_AF4,
|
||||
.bus = APB1,
|
||||
.rcc_mask = RCC_APB1ENR_I2C1EN,
|
||||
.clk = CLOCK_APB1,
|
||||
.irqn = I2C1_EV_IRQn
|
||||
}
|
||||
};
|
||||
|
||||
#define I2C_0_ISR isr_i2c1_ev
|
||||
|
||||
#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name ADC configuration
|
||||
*
|
||||
|
||||
@ -23,6 +23,7 @@
|
||||
|
||||
#include "periph_cpu.h"
|
||||
#include "f4/cfg_clock_180_8_1.h"
|
||||
#include "cfg_i2c1_pb8_pb9.h"
|
||||
#include "cfg_spi_divtable.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
@ -157,30 +158,6 @@ static const spi_conf_t spi_config[] = {
|
||||
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name I2C configuration
|
||||
* @{
|
||||
*/
|
||||
static const i2c_conf_t i2c_config[] = {
|
||||
{
|
||||
.dev = I2C1,
|
||||
.speed = I2C_SPEED_NORMAL,
|
||||
.scl_pin = GPIO_PIN(PORT_B, 8),
|
||||
.sda_pin = GPIO_PIN(PORT_B, 9),
|
||||
.scl_af = GPIO_AF4,
|
||||
.sda_af = GPIO_AF4,
|
||||
.bus = APB1,
|
||||
.rcc_mask = RCC_APB1ENR_I2C1EN,
|
||||
.clk = CLOCK_APB1,
|
||||
.irqn = I2C1_EV_IRQn
|
||||
}
|
||||
};
|
||||
|
||||
#define I2C_0_ISR isr_i2c1_ev
|
||||
|
||||
#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name ADC configuration
|
||||
* @{
|
||||
|
||||
@ -22,6 +22,7 @@
|
||||
#define PERIPH_CONF_H
|
||||
|
||||
#include "periph_cpu.h"
|
||||
#include "cfg_i2c1_pb8_pb9.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
@ -136,29 +137,6 @@ static const uart_conf_t uart_config[] = {
|
||||
#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name I2C configuration
|
||||
* @{
|
||||
*/
|
||||
static const i2c_conf_t i2c_config[] = {
|
||||
{
|
||||
.dev = I2C1,
|
||||
.speed = I2C_SPEED_NORMAL,
|
||||
.scl_pin = GPIO_PIN(PORT_B, 8),
|
||||
.sda_pin = GPIO_PIN(PORT_B, 9),
|
||||
.scl_af = GPIO_AF4,
|
||||
.sda_af = GPIO_AF4,
|
||||
.bus = APB1,
|
||||
.rcc_mask = RCC_APB1ENR_I2C1EN,
|
||||
.irqn = I2C1_ER_IRQn,
|
||||
}
|
||||
};
|
||||
|
||||
#define I2C_0_ISR isr_i2c1_er
|
||||
|
||||
#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
# Put defined MCU peripherals here (in alphabetical order)
|
||||
FEATURES_PROVIDED += periph_i2c
|
||||
FEATURES_PROVIDED += periph_rtc
|
||||
FEATURES_PROVIDED += periph_timer
|
||||
FEATURES_PROVIDED += periph_uart
|
||||
|
||||
@ -22,6 +22,7 @@
|
||||
#define PERIPH_CONF_H
|
||||
|
||||
#include "periph_cpu.h"
|
||||
#include "cfg_i2c1_pb8_pb9.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
|
||||
@ -26,6 +26,7 @@
|
||||
#define PERIPH_CONF_H
|
||||
|
||||
#include "periph_cpu.h"
|
||||
#include "cfg_i2c1_pb8_pb9.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
@ -249,29 +250,6 @@ static const spi_conf_t spi_config[] = {
|
||||
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name I2C configuration
|
||||
* @{
|
||||
*/
|
||||
static const i2c_conf_t i2c_config[] = {
|
||||
{
|
||||
.dev = I2C1,
|
||||
.speed = I2C_SPEED_NORMAL,
|
||||
.scl_pin = GPIO_PIN(PORT_B, 8),
|
||||
.sda_pin = GPIO_PIN(PORT_B, 9),
|
||||
.scl_af = GPIO_AF4,
|
||||
.sda_af = GPIO_AF4,
|
||||
.bus = APB1,
|
||||
.rcc_mask = RCC_APB1ENR1_I2C1EN,
|
||||
.irqn = I2C1_ER_IRQn,
|
||||
}
|
||||
};
|
||||
|
||||
#define I2C_0_ISR isr_i2c1_er
|
||||
|
||||
#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name ADC configuration
|
||||
*
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
# Put defined MCU peripherals here (in alphabetical order)
|
||||
FEATURES_PROVIDED += periph_i2c
|
||||
FEATURES_PROVIDED += periph_pwm
|
||||
FEATURES_PROVIDED += periph_rtc
|
||||
FEATURES_PROVIDED += periph_rtt
|
||||
|
||||
@ -20,6 +20,7 @@
|
||||
#define PERIPH_CONF_H
|
||||
|
||||
#include "periph_cpu.h"
|
||||
#include "cfg_i2c1_pb8_pb9.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user