Merge pull request #11211 from aabadie/cpu_stm32f3_cpu

cpu/stm32: add STOP and STANDBY low-power for stm32f3, unify for all stm32

cpu/stm32_common/Makefile.include

@@ -5,6 +5,9 @@ export CFLAGS += -DCPU_FAM_$(FAM)
 # include common periph module
 USEMODULE += periph_common
 
+# All stm32 families provide pm support
+USEMODULE += pm_layered
+
 # include stm32 common functions and stm32 common periph drivers
 USEMODULE += stm32_common stm32_common_periph
 

cpu/stm32_common/include/periph_cpu_common.h

@@ -78,10 +78,6 @@ extern "C" {
  * @name    PM definitions
  * @{
  */
-#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
-    defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
-    defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1) || \
-    defined(DOXYGEN)
 /**
  * @brief   Number of usable low power modes
  */
@@ -101,7 +97,6 @@ extern "C" {
  */
 #define PM_EWUP_CONFIG          (0U)
 #endif
-#endif
 /** @} */
 
 /**

cpu/stm32_common/periph/pm.c

@@ -3,6 +3,7 @@
  *               2015 Freie Universität Berlin
  *               2015 Engineering-Spirit
  *               2017-2019 OTA keys S.A.
+ *               2019 Inria
  *
  * This file is subject to the terms and conditions of the GNU Lesser
  * General Public License v2.1. See the file LICENSE in the top level
@@ -21,6 +22,7 @@
  * @author      Kaspar Schleiser <kaspar@schleiser.de>
  * @author      Fabian Nack <nack@inf.fu-berlin.de>
  * @author      Vincent Dupont <vincent@otakeys.com>
+ * @author      Alexandre Abadie <alexandre.abadie@inria.fr>
  *
  * @}
  */
@@ -38,10 +40,15 @@
  *
  * Available values can be found in reference manual, PWR section, register CR.
  */
-#if defined(CPU_FAM_STM32F0)
+#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3)
 #define PM_STOP_CONFIG  (PWR_CR_LPDS)
 #elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
-#define PM_STOP_CONFIG  (PWR_CR_LPSDSR | PWR_CR_ULP)
+/* Enable ultra low-power and clear wakeup flags */
+#define PM_STOP_CONFIG  (PWR_CR_LPSDSR | PWR_CR_ULP | PWR_CR_CWUF)
+#elif defined(CPU_FAM_STM32L4)
+#define PM_STOP_CONFIG  (PWR_CR1_LPMS_STOP1)
+#elif defined(CPU_FAM_STM32F7)
+#define PM_STOP_CONFIG  (PWR_CR1_LPDS | PWR_CR1_FPDS | PWR_CR1_LPUDS)
 #else
 #define PM_STOP_CONFIG  (PWR_CR_LPDS | PWR_CR_FPDS)
 #endif
@@ -55,11 +62,31 @@
  */
 #if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
 #define PM_STANDBY_CONFIG   (PWR_CR_PDDS | PWR_CR_CWUF | PWR_CR_CSBF | PWR_CR_ULP)
+#elif defined(CPU_FAM_STM32L4)
+#define PM_STANDBY_CONFIG   (PWR_CR1_LPMS_STANDBY)
+#elif defined(CPU_FAM_STM32F7)
+#define PM_STANDBY_CONFIG   (PWR_CR1_PDDS | PWR_CR1_CSBF)
 #else
 #define PM_STANDBY_CONFIG   (PWR_CR_PDDS | PWR_CR_CWUF | PWR_CR_CSBF)
 #endif
 #endif
 
+#if defined(CPU_FAM_STM32L4)
+#define PWR_CR_REG     PWR->CR1
+#define PWR_WUP_REG    PWR->CR3
+/* Allow overridable SRAM2 retention mode using CFLAGS */
+#ifndef STM32L4_SRAM2_RETENTION
+/* Disable SRAM2 retention by default for maximum power saving */
+#define STM32L4_SRAM2_RETENTION  (0)
+#endif
+#elif defined(CPU_FAM_STM32F7)
+#define PWR_CR_REG     PWR->CR1
+#define PWR_WUP_REG    PWR->CSR2
+#else
+#define PWR_CR_REG     PWR->CR
+#define PWR_WUP_REG    PWR->CSR
+#endif
+
 void pm_set(unsigned mode)
 {
     int deep;
@@ -67,18 +94,27 @@ void pm_set(unsigned mode)
     switch (mode) {
 #ifdef STM32_PM_STANDBY
         case STM32_PM_STANDBY:
-            PWR->CR &= ~(PM_STOP_CONFIG | PM_STANDBY_CONFIG);
+            PWR_CR_REG &= ~(PM_STOP_CONFIG | PM_STANDBY_CONFIG);
-            PWR->CR |= PM_STANDBY_CONFIG;
+            PWR_CR_REG |= PM_STANDBY_CONFIG;
+#if defined(CPU_FAM_STM32L4)
+#if STM32L4_SRAM2_RETENTION
+            PWR->CR3 |= PWR_CR3_RRS;
+#else
+            PWR->CR3 &= ~PWR_CR3_RRS;
+#endif
+            /* Clear flags */
+            PWR->SCR |= PWR_SCR_CSBF;
+#endif
             /* Enable WKUP pin to use for wakeup from standby mode */
-            PWR->CSR |= PM_EWUP_CONFIG;
+            PWR_WUP_REG |= PM_EWUP_CONFIG;
             /* Set SLEEPDEEP bit of system control block */
             deep = 1;
             break;
 #endif
 #ifdef STM32_PM_STOP
         case STM32_PM_STOP:
-            PWR->CR &= ~(PM_STOP_CONFIG | PM_STANDBY_CONFIG);
+            PWR_CR_REG &= ~(PM_STOP_CONFIG | PM_STANDBY_CONFIG);
-            PWR->CR |= PM_STOP_CONFIG;
+            PWR_CR_REG |= PM_STOP_CONFIG;
             /* Set SLEEPDEEP bit of system control block */
             deep = 1;
             break;

cpu/stm32f0/Makefile.include

@@ -1,7 +1,5 @@
 export CPU_ARCH = cortex-m0
 export CPU_FAM  = stm32f0
 
-USEMODULE += pm_layered
-
 include $(RIOTCPU)/stm32_common/Makefile.include
 include $(RIOTMAKE)/arch/cortexm.inc.mk

cpu/stm32f1/Makefile.include

@@ -1,7 +1,5 @@
 export CPU_ARCH = cortex-m3
 export CPU_FAM  = stm32f1
 
-USEMODULE += pm_layered
-
 include $(RIOTCPU)/stm32_common/Makefile.include
 include $(RIOTMAKE)/arch/cortexm.inc.mk

cpu/stm32f2/Makefile.include

@@ -1,7 +1,5 @@
 export CPU_ARCH = cortex-m3
 export CPU_FAM  = stm32f2
 
-USEMODULE += pm_layered
-
 include $(RIOTCPU)/stm32_common/Makefile.include
 include $(RIOTMAKE)/arch/cortexm.inc.mk

cpu/stm32f4/Makefile.include

@@ -1,7 +1,5 @@
 export CPU_ARCH = cortex-m4f
 export CPU_FAM  = stm32f4
 
-USEMODULE += pm_layered
-
 include $(RIOTCPU)/stm32_common/Makefile.include
 include $(RIOTMAKE)/arch/cortexm.inc.mk

cpu/stm32l0/Makefile.include

@@ -1,7 +1,5 @@
 export CPU_ARCH = cortex-m0plus
 export CPU_FAM  = stm32l0
 
-USEMODULE += pm_layered
-
 include $(RIOTCPU)/stm32_common/Makefile.include
 include $(RIOTMAKE)/arch/cortexm.inc.mk

cpu/stm32l1/Makefile.include

@@ -1,7 +1,5 @@
 export CPU_ARCH = cortex-m3
 export CPU_FAM  = stm32l1
 
-USEMODULE += pm_layered
-
 include $(RIOTCPU)/stm32_common/Makefile.include
 include $(RIOTMAKE)/arch/cortexm.inc.mk