cpu/cc13x2: Add support for cc13x2 MCUs
Signed-off-by: Anton Gerasimov <tossel@gmail.com>
This commit is contained in:
Anton Gerasimov
parent
1442561c8e
commit
1659a71ed0
7
cpu/cc13x2/Makefile
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7
cpu/cc13x2/Makefile
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# Define the module that is built:
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MODULE = cpu
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# Add a list of subdirectories, that should also be built:
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DIRS = periph $(RIOTCPU)/cortexm_common $(RIOTCPU)/cc26xx_cc13xx
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include $(RIOTBASE)/Makefile.base
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1
cpu/cc13x2/Makefile.features
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1
cpu/cc13x2/Makefile.features
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-include $(RIOTCPU)/cc26xx_cc13xx/Makefile.features
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7
cpu/cc13x2/Makefile.include
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cpu/cc13x2/Makefile.include
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CPU_ARCH = cortex-m4f
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CPU_VARIANT = x2
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VECTORS_O = $(BINDIR)/cc26xx_cc13xx/vectors.o
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include ${RIOTCPU}/cc26xx_cc13xx/Makefile.include
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include $(RIOTMAKE)/arch/cortexm.inc.mk
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41
cpu/cc13x2/cpu.c
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cpu/cc13x2/cpu.c
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/*
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* Copyright (C) 2016 Leon George
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* Copyright (C) 2018 Anton Gerasimov
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_cc13x2
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* @{
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*
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* @file
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* @brief implementation of the CPU initialization
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*
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* @author Leon M. George <leon@georgemail.eu>, Anton Gerasimov <tossel@gmail.com>
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* @}
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*/
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#include "cpu.h"
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#include "periph_conf.h"
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#include "periph/init.h"
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#include "stdio_base.h"
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#include "cc13x2_prcm.h"
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/**
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* @brief Initialize the CPU, set IRQ priorities
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*/
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void cpu_init(void)
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{
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/* initialize the Cortex-M core */
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cortexm_init();
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/* initialize stdio prior to periph_init() to allow use of DEBUG() there */
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stdio_init();
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/* trigger static peripheral initialization */
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periph_init();
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}
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17
cpu/cc13x2/doc.txt
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17
cpu/cc13x2/doc.txt
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/**
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* @defgroup cpu_cc13x2 TI CC13x2
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* @ingroup cpu
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* @brief Texas Instruments CC13x2 Cortex-M4F MCU specific code
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*/
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/**
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* @defgroup cpu_cc13x2_peripheral_memory_map TI CC13x2 peripheral memory map
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* @ingroup cpu
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* @brief Texas Instruments CC13x2 memory mappings for peripherals
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*/
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/**
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* @defgroup cpu_cc13x2_definitions TI CC13x2 definitions
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* @ingroup cpu_cc13x2
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* @brief Texas Instruments CC13x2 specific defines
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*/
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346
cpu/cc13x2/include/cc13x2_aux.h
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346
cpu/cc13x2/include/cc13x2_aux.h
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/*
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* Copyright (C) 2016 Leon George
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* Copyright (C) 2018 Anton Gerasimov
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_cc13x2_definitions
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* @{
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*
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* @file
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* @brief CC13x2 AUX register definitions
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*/
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#ifndef CC13X2_AUX_H
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#define CC13X2_AUX_H
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#include <stdbool.h>
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#include "cc26xx_cc13xx.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* AUX_AIODIO registers
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*/
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typedef struct {
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reg32_t IOMODE; /**< input output mode */
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reg32_t GPIODIE; /**< gpio data input enable */
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reg32_t IOPOE; /**< io peripheral output enable */
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reg32_t GPIODOUT; /**< gpio data output */
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reg32_t GPIODIN; /**< gpio data input */
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reg32_t GPIODOUTSET; /**< gpio data out set */
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reg32_t GPIODOUTCLR; /**< gpio data out clear */
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reg32_t GPIODOUTTGL; /**< gpio data out toggle */
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reg32_t IO0PSEL; /**< i/o 0 peripheral select */
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reg32_t IO1PSEL; /**< i/o 1 peripheral select */
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reg32_t IO2PSEL; /**< i/o 2 peripheral select */
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reg32_t IO3PSEL; /**< i/o 3 peripheral select */
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reg32_t IO4PSEL; /**< i/o 4 peripheral select */
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reg32_t IO5PSEL; /**< i/o 5 peripheral select */
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reg32_t IO6PSEL; /**< i/o 6 peripheral select */
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reg32_t IO7PSEL; /**< i/o 7 peripheral select */
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reg32_t IOMODEH; /**< input output mode high */
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reg32_t IOMODEL; /**< input output mode low */
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} aux_aiodio_regs_t;
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AUX_AIODIO0_BASE 0x400CC000 /**< AUX_AIODIO0 base address */
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#define AUX_AIODIO1_BASE 0x400CD000 /**< AUX_AIODIO1 base address */
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#define AUX_AIODIO2_BASE 0x400CE000 /**< AUX_AIODIO2 base address */
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#define AUX_AIODIO3_BASE 0x400CF000 /**< AUX_AIODIO3 base address */
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/** @} */
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#define AUX_AIODIO0 ((aux_aiodio_regs_t *) (AUX_AIODIO0_BASE)) /**< AUX_AIODIO0 register bank */
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#define AUX_AIODIO1 ((aux_aiodio_regs_t *) (AUX_AIODIO1_BASE)) /**< AUX_AIODIO1 register bank */
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#define AUX_AIODIO2 ((aux_aiodio_regs_t *) (AUX_AIODIO2_BASE)) /**< AUX_AIODIO2 register bank */
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#define AUX_AIODIO3 ((aux_aiodio_regs_t *) (AUX_AIODIO3_BASE)) /**< AUX_AIODIO3 register bank */
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/**
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* AUX_TDC registers
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*/
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typedef struct {
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reg32_t CTL; /**< control */
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reg32_t STAT; /**< status */
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reg32_t RESULT; /**< result */
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reg32_t SATCFG; /**< saturaion configuration */
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reg32_t TRIGSRC; /**< trigger source */
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reg32_t TRIGCNT; /**< trigger counter */
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reg32_t TRIGCNTLOAD; /**< trigger counter load */
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reg32_t TRIGCNTCFG; /**< trigger counter config */
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reg32_t PRECTL; /**< prescaler control */
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reg32_t PRECNT; /**< prescaler counter */
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} aux_tdc_regs_t;
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AUX_TDC_BASE 0x400C4000 /**< AUX_TDC base address */
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/** @} */
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#define AUX_TDC ((aux_tdc_regs_t *) (AUX_TDC_BASE)) /**< AUX_TDC register bank */
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/**
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* AUX_EVCTL registers
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*/
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typedef struct {
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reg32_t EVSTAT0; /**< event status 0 */
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reg32_t EVSTAT1; /**< event status 1 */
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reg32_t EVSTAT2; /**< event status 2 */
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reg32_t EVSTAT3; /**< event status 3 */
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reg32_t SCEWEVSEL0; /**< sensor controller engine wait event configuration 0 */
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reg32_t SCEWEVSEL1; /**< sensor controller engine wait event configuration 1 */
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reg32_t DMACTL; /**< direct memoty access control */
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reg32_t __reserved; /**< meh */
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reg32_t SWEVSET; /**< software event set */
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reg32_t EVTOAONFLAGS; /**< events to AON domain flags */
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reg32_t EVTOAONPOL; /**< events to AON domain polarity */
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reg32_t EVTOAONFLAGSCLR; /**< events to AON domain clear */
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reg32_t EVTOMCUFLAGS; /**< event to MCU domain flags */
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reg32_t EVTOMCUPOL; /**< event to MCU domain polarity */
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reg32_t EVTOMCUFLAGSCLR; /**< events to MCU domain flags clear */
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reg32_t COMBEVTOMCUMASK; /**< combined event to MCU domain mask */
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reg32_t PROGDLY; /**< programmable delay */
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reg32_t MANUAL; /**< manual */
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reg32_t EVSTAT0L; /**< event status 0 low */
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reg32_t EVSTAT0H; /**< event status 0 high */
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reg32_t EVSTAT1L; /**< event status 1 low */
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reg32_t EVSTAT1H; /**< event status 1 high */
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reg32_t EVSTAT2L; /**< event status 2 low */
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reg32_t EVSTAT2H; /**< event status 2 high */
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reg32_t EVSTAT3L; /**< event status 3 low */
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reg32_t EVSTAT3H; /**< event status 3 high */
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} aux_evtcl_regs_t;
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AUX_EVCTL_BASE 0x400C5000 /**< AUX_EVCTL base address */
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/** @} */
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#define AUX_EVCTL ((aux_evctl_regs_t *) (AUX_EVCTL_BASE)) /**< AUX_EVCTL register bank */
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/**
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* AUX_SYSIF registers
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*/
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typedef struct {
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reg32_t OPMODEREQ; /**< operational mode request */
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reg32_t OPMODEACK; /**< operational mode acknowledgement */
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reg32_t PROGWU0CFG; /**< programmanble wakeup 0 configuration */
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reg32_t PROGWU1CFG; /**< programmanble wakeup 0 configuration */
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reg32_t PROGWU2CFG; /**< programmanble wakeup 0 configuration */
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reg32_t PROGWU3CFG; /**< programmanble wakeup 0 configuration */
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reg32_t SWUTRIG; /**< software wakeup triggers */
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reg32_t WUFLAGS; /**< wakeup flags */
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reg32_t WUFLAGSCLR; /**< wakeup flags clear */
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reg32_t WUGATE; /**< wakeup gate */
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reg32_t VECCFG0; /**< vector configuration 0 */
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reg32_t VECCFG1; /**< vector configuration 1 */
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reg32_t VECCFG2; /**< vector configuration 2 */
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reg32_t VECCFG3; /**< vector configuration 3 */
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reg32_t VECCFG4; /**< vector configuration 4 */
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reg32_t VECCFG5; /**< vector configuration 5 */
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reg32_t VECCFG6; /**< vector configuration 6 */
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reg32_t VECCFG7; /**< vector configuration 7 */
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reg32_t EVSYNCRATE; /**< event synchronization rate */
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reg32_t PEROPRATE; /**< peripheral operational rate */
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reg32_t ADCCLKCTL; /**< ADC clock control */
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reg32_t TDCCLKCTL; /**< TDC clock control */
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reg32_t TDCREFCLKCTL; /**< TDC reference clock control */
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reg32_t TIMER2CLKCTL; /**< AUX_TIMER2 clock control */
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reg32_t TIMER2CLKSTAT; /**< AUX_TIMER2 clock status */
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reg32_t TIMER2CLKSWITCH; /**< AUX_TIMER2 clock switch */
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reg32_t TIMER2DBGCTL; /**< AUX_TIMER2 debug control */
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reg32_t __reserved1; /**< meh */
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reg32_t CLKSHIFTDET; /**< clock shift detection */
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reg32_t RECHARGETRIG; /**< recharge trigger */
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reg32_t RECHARGEDET; /**< recharge detector */
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reg32_t RTCSUBSECINC0; /**< RTC sub-second increment 0 */
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reg32_t RTCSUBSECINC1; /**< RTC sub-second increment 1 */
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reg32_t RTCSUBSECINCCTL; /**< RTC sub-second increment control */
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reg32_t RTCSEC; /**< RTC second */
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reg32_t RTCSUBSEC; /**< RTC sub-second */
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reg32_t RTCEVCLR; /**< RTC event clear */
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reg32_t BATMONBAT; /**< battery voltage */
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reg32_t __reserved2; /**< meh */
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reg32_t BATMONTEMP; /**< batmon temperature */
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reg32_t TIMERHALT; /**< timer halt */
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reg32_t __reserved3[3]; /**< meh */
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reg32_t TIMER2BRIDGE; /**< timer2 bridge */
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reg32_t SWPWRPROF; /**< software power profiler */
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} aux_sysif_regs_t;
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/** @} */
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AUX_SYSIF_BASE 0x400C6000 /**< AUX_SYSIF base address */
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/** @} */
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#define AUX_SYSIF ((aux_wuc_regs_t *) (AUX_SYSIF_BASE)) /**< AUX_SYSIF register bank */
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/**
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* AUX_TIMER registers
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*/
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typedef struct {
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reg32_t T0CFG; /**< timer 0 config */
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reg32_t T0CTL; /**< timer 0 control */
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reg32_t T0TARGET; /**< timer 0 target */
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reg32_t T0CNTR; /**< timer 0 counter */
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reg32_t T1CFG; /**< timer 1 config */
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reg32_t T1TARGET; /**< timer 1 target */
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reg32_t T1CTL; /**< timer 1 control */
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reg32_t T1CNTR; /**< timer 0 counter */
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} aux_timer01_regs_t;
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AUX_TIMER01_BASE 0x400C7000 /**< AUX_WUC base address */
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/** @} */
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#define AUX_TIMER01 ((aux_timer01_regs_t *) (AUX_TIMER01_BASE)) /**< AUX_TIMER01 register bank */
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/**
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* AUX_TIMER2 registers
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*/
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typedef struct {
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reg32_t CTL; /**< timer 2 control */
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reg32_t TARGET; /**< timer 2 target */
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reg32_t SHDWTARGET; /**< timer 2 shadow target */
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reg32_t CNTR; /**< timer 2 counter */
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reg32_t PRECFG; /**< timer 2 prescaler config */
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reg32_t EVCTL; /**< timer 2 event control */
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reg32_t PULSETRIG; /**< timer 2 pulse trigger */
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reg32_t __reserved[25]; /**< meh */
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reg32_t CH0EVCFG; /**< timer 2 channel 0 event configuration */
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reg32_t CH0CCFG; /**< timer 2 channel 0 capture configuration */
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reg32_t CH0PCC; /**< timer 2 channel 0 pipeline capture compare */
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reg32_t CH0CC; /**< timer 2 channel 0 capture compare */
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reg32_t CH1EVCFG; /**< timer 2 channel 1 event configuration */
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reg32_t CH1CCFG; /**< timer 2 channel 1 capture configuration */
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reg32_t CH1PCC; /**< timer 2 channel 1 pipeline capture compare */
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reg32_t CH1CC; /**< timer 2 channel 1 capture compare */
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reg32_t CH2EVCFG; /**< timer 2 channel 2 event configuration */
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reg32_t CH2CCFG; /**< timer 2 channel 2 capture configuration */
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reg32_t CH2PCC; /**< timer 2 channel 2 pipeline capture compare */
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reg32_t CH2CC; /**< timer 2 channel 2 capture compare */
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reg32_t CH3EVCFG; /**< timer 2 channel 3 event configuration */
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reg32_t CH3CCFG; /**< timer 2 channel 3 capture configuration */
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reg32_t CH3PCC; /**< timer 2 channel 3 pipeline capture compare */
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reg32_t CH3CC; /**< timer 2 channel 3 capture compare */
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} aux_timer2_regs_t;
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AUX_TIMER2_BASE 0x400C3000 /**< AUX_WUC base address */
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/** @} */
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#define AUX_TIMER2 ((aux_timer2_regs_t *) (AUX_TIMER2_BASE)) /**< AUX_TIMER2 register bank */
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/**
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* AUX_SMPH registers
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*/
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typedef struct {
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reg32_t SMPH0; /**< semaphore 0 */
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reg32_t SMPH1; /**< semaphore 1 */
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reg32_t SMPH2; /**< semaphore 2 */
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reg32_t SMPH3; /**< semaphore 3 */
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reg32_t SMPH4; /**< semaphore 4 */
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reg32_t SMPH5; /**< semaphore 5 */
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reg32_t SMPH6; /**< semaphore 6 */
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reg32_t SMPH7; /**< semaphore 7 */
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reg32_t AUTOTAKE; /**< sticky request for single semaphore */
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} aux_smph_regs_t;
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AUX_SMPH_BASE 0x400C8000 /**< AUX_WUC base address */
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/* @} */
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#define AUX_SMPH ((aux_smph_regs_t *) (AUX_SMPH_BASE)) /**< AUX_SMPH register bank */
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/**
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* AUX_ANAIF registers
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*/
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typedef struct {
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reg32_t __reserved1[4]; /**< meh */
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reg32_t ADCCTL; /**< ADC control */
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reg32_t ADCFIFOSTAT; /**< ADC fifo status */
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reg32_t ADCFIFO; /**< ADC fifo */
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reg32_t ADCTRIG; /**< ADC trigger */
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reg32_t ISRCCTL; /**< current source control */
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reg32_t __reserved2[3]; /**< meh */
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reg32_t DACCTL; /**< DAC control */
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reg32_t LPMBIASCTL; /**< low-power mode bias control */
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reg32_t DACSMPLCTL; /**< DAC sample control */
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reg32_t DACSMPLCFG0; /**< DAC sample configuration 0 */
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reg32_t DACSMPLCFG1; /**< DAC sample configuration 1 */
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reg32_t DACVALUE; /**< DAC value */
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reg32_t DACSTAT; /**< DAC status */
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} aux_anaif_regs_t;
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AUX_ANAIF_BASE 0x400C9000 /**< AUX_WUC base address */
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/** @} */
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#define AUX_ANAIF ((aux_anaif_regs_t *) (AUX_ANAIF_BASE)) /**< AUX_ANAIF register bank */
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/**
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* ADI_4_AUX registers
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*/
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typedef struct {
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reg8_t MUX0; /**< multiplexer 0 */
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reg8_t MUX1; /**< multiplexer 1 */
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reg8_t MUX2; /**< multiplexer 2 */
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reg8_t MUX3; /**< multiplexer 3 */
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reg8_t ISRC; /**< current source */
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reg8_t COMP; /**< comparator */
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reg8_t MUX4; /**< multiplexer 4 */
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reg8_t ADC0; /**< ADC control 0 */
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reg8_t ADC1; /**< ADC control 1 */
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reg8_t ADCREF0; /**< ADC reference 0 */
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reg8_t ADCREF1; /**< ADC reference 1 */
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} adi_4_aux_regs_t;
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
|
||||
#define ADI_4_AUX_BASE 0x400CB000 /**< AUX_WUC base address */
|
||||
/** @} */
|
||||
|
||||
#define ADI_4_AUX ((adi_4_aux_regs_t *) (ADI_4_AUX_BASE)) /**< ADI_4_AUX register bank */
|
||||
|
||||
|
||||
#define ADDI_SEM AUX_SMPH->SMPH0 /**< the semamphore used for ADDI */
|
||||
|
||||
#ifdef __cplusplus
|
||||
} /* end extern "C" */
|
||||
#endif
|
||||
|
||||
#endif /* CC13X2_AUX_H */
|
||||
|
||||
/** @}*/
|
||||
147
cpu/cc13x2/include/cc13x2_fcfg.h
Normal file
147
cpu/cc13x2/include/cc13x2_fcfg.h
Normal file
@ -0,0 +1,147 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Leon George
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser General
|
||||
* Public License v2.1. See the file LICENSE in the top level directory for more
|
||||
* details.
|
||||
*/
|
||||
/**
|
||||
* @ingroup cpu_cc13x2_definitions
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief CC13x2 FCFG register definitions
|
||||
*/
|
||||
|
||||
#ifndef CC13X2_FCFG_H
|
||||
#define CC13X2_FCFG_H
|
||||
|
||||
#include <cc26xx_cc13xx.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @ingroup cpu_specific_peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
#define FCFG_BASE 0x50001000 /**< base address of FCFG memory */
|
||||
/*@}*/
|
||||
|
||||
/**
|
||||
* FCFG registers
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t __reserved1[0xA0]; /**< meh */
|
||||
/* TODO does it pad here? */
|
||||
reg32_t MISC_CONF_1; /**< misc config */
|
||||
reg32_t MISC_CONF_2; /**< misc config */
|
||||
reg32_t __reserved2[7]; /**< meh */
|
||||
reg32_t CONFIG_FE_CC26; /**< internal */
|
||||
reg32_t CONFIG_FE_CC13; /**< internal */
|
||||
reg32_t CONFIG_RF_COMMON; /**< internal */
|
||||
reg32_t CONFIG_SYNTH_DIV2_CC26_2G4; /**< config of synthesizer in divide-by-2-mode */
|
||||
reg32_t CONFIG_SYNTH_DIV2_CC13_2G4; /**< config of synthesizer in divide-by-2-mode */
|
||||
reg32_t CONFIG_SYNTH_DIV2_CC26_1G; /**< config of synthesizer in divide-by-2-mode */
|
||||
reg32_t CONFIG_SYNTH_DIV2_CC13_1G; /**< config of synthesizer in divide-by-2-mode */
|
||||
reg32_t CONFIG_SYNTH_DIV4_CC26; /**< config of synthesizer in divide-by-4-mode */
|
||||
reg32_t CONFIG_SYNTH_DIV4_CC13; /**< config of synthesizer in divide-by-4-mode */
|
||||
reg32_t CONFIG_SYNTH_DIV5; /**< config of synthesizer in divide-by-5-mode */
|
||||
reg32_t CONFIG_SYNTH_DIV6_CC26; /**< config of synthesizer in divide-by-5-mode */
|
||||
reg32_t CONFIG_SYNTH_DIV6_CC13; /**< config of synthesizer in divide-by-5-mode */
|
||||
reg32_t CONFIG_SYNTH_DIV10; /**< config of synthesizer in divide-by-10-mode */
|
||||
reg32_t CONFIG_SYNTH_DIV12_CC26; /**< config of synthesizer in divide-by-12-mode */
|
||||
reg32_t CONFIG_SYNTH_DIV12_CC13; /**< config of synthesizer in divide-by-12-mode */
|
||||
reg32_t CONFIG_SYNTH_DIV15; /**< config of synthesizer in divide-by-15-mode */
|
||||
reg32_t CONFIG_SYNTH_DIV30; /**< config of synthesizer in divide-by-30-mode */
|
||||
reg32_t __reserved3[23]; /**< meh */
|
||||
reg32_t FLASH_NUMBER; /**< manufacturing lot number */
|
||||
reg32_t __reserved4; /**< meh */
|
||||
reg32_t FLASH_COORDINATE; /**< chip coordinates on a wafer */
|
||||
reg32_t FLASH_E_P; /**< internal */
|
||||
reg32_t FLASH_C_E_P_R; /**< internal */
|
||||
reg32_t FLASH_P_R_PV; /**< internal */
|
||||
reg32_t FLASH_EH_SEQ; /**< internal */
|
||||
reg32_t FLASH_VHV_E; /**< internal */
|
||||
reg32_t FLASH_PP; /**< internal */
|
||||
reg32_t FLASH_PROG_EP; /**< internal */
|
||||
reg32_t FLASH_ERA_PW; /**< internal */
|
||||
reg32_t FLASH_VHV; /**< internal */
|
||||
reg32_t FLASH_VHV_PV; /**< internal */
|
||||
reg32_t FLASH_V; /**< internal */
|
||||
reg32_t __reserved5[38]; /**< meh */
|
||||
reg32_t USER_ID; /* user identification */
|
||||
reg32_t __reserved6[6]; /**< meh */
|
||||
reg32_t FLASH_OTP_DATA3; /**< internal */
|
||||
reg32_t ANA2_TRIM; /**< internal */
|
||||
reg32_t LDO_TRIM; /**< internal */
|
||||
reg32_t __reserved7[11]; /**< meh */
|
||||
reg32_t MAC_BLE_0; /**< MAC BLE address 0 */
|
||||
reg32_t MAC_BLE_1; /**< MAC BLE address 1 */
|
||||
reg32_t MAC_15_4_0; /**< MAC IEEE 802.15.4 address 0 */
|
||||
reg32_t MAC_15_4_1; /**< MAC IEEE 802.15.4 address 1 */
|
||||
reg32_t __reserved8[4]; /**< meh */
|
||||
reg32_t FLASH_OTP_DATA4; /**< Internal */
|
||||
reg32_t MISC_TRIM; /**< Miscelaneous trim parameters */
|
||||
reg32_t RCOSC_HF_TEMPCOMP; /**< Internal */
|
||||
reg32_t __reserved9; /**< meh */
|
||||
reg32_t ICEPICK_DEVICE_ID; /**< IcePick Device Identification */
|
||||
reg32_t FCFG1_REVISION; /**< Factory configuration revision */
|
||||
reg32_t MISC_OTP_DATA; /**< Miscelanous OTP data */
|
||||
reg32_t __reserved10[8]; /**< meh */
|
||||
reg32_t IOCONF; /**< I/O Configuration */
|
||||
reg32_t __reserved11; /**< meh */
|
||||
reg32_t CONFIG_IF_ADC; /**< Internal */
|
||||
reg32_t CONFIG_OSC_TOP; /**< Internal */
|
||||
reg32_t __reserved12[2]; /**< meh */
|
||||
reg32_t SOC_ADC_ABS_GAIN; /**< AUX_ADC gain in absolute reference mode */
|
||||
reg32_t SOC_ADC_REL_GAIN; /**< AUX_ADC gain in relative reference mode */
|
||||
reg32_t __reserved13; /**< meh */
|
||||
reg32_t SOC_ADC_OFFSET_INT; /**< AUX_ADC temperature offsets in absolute reference mode */
|
||||
reg32_t SOC_ADC_REF_TRIM_AND_OFFSET_EXT; /**< Internal */
|
||||
reg32_t AMPCOMP_TH1; /**< Internal */
|
||||
reg32_t AMPCOMP_TH2; /**< Internal */
|
||||
reg32_t AMPCOMP_CTRL1; /**< Internal */
|
||||
reg32_t ANABYPASS_VALUE2; /**< Internal */
|
||||
reg32_t __reserved14[2]; /**< meh */
|
||||
reg32_t VOLT_TRIM; /**< Internal */
|
||||
reg32_t OSC_CONF; /**< OSC configuration */
|
||||
reg32_t FREQ_OFFSET; /**< Internal */
|
||||
reg32_t __reserved15; /**< meh */
|
||||
reg32_t MISC_OTP_DATA_1; /**< Internal */
|
||||
reg32_t PWD_CURR_20C; /**< power down current control 20C */
|
||||
reg32_t PWD_CURR_35C; /**< power down current control 35C */
|
||||
reg32_t PWD_CURR_50C; /**< power down current control 50C */
|
||||
reg32_t PWD_CURR_65C; /**< power down current control 65C */
|
||||
reg32_t PWD_CURR_80C; /**< power down current control 80C */
|
||||
reg32_t PWD_CURR_95C; /**< power down current control 95C */
|
||||
reg32_t PWD_CURR_110C; /**< power down current control 110C */
|
||||
reg32_t PWD_CURR_125C; /**< power down current control 125C */
|
||||
reg32_t __reserved16[5]; /**< meh */
|
||||
reg32_t SHDW_DIE_ID_0; /**< shadow of JTAG_TAP::EFUSE::DIE_ID_0.* */
|
||||
reg32_t SHDW_DIE_ID_1; /**< shadow of JTAG_TAP::EFUSE::DIE_ID_1.* */
|
||||
reg32_t SHDW_DIE_ID_2; /**< shadow of JTAG_TAP::EFUSE::DIE_ID_2.* */
|
||||
reg32_t SHDW_DIE_ID_3; /**< shadow of JTAG_TAP::EFUSE::DIE_ID_3.* */
|
||||
reg32_t __reserved17[2]; /**< meh */
|
||||
reg32_t SHDW_OSC_BIAS_LDO_TRIM; /**< Internal */
|
||||
reg32_t SHDW_ANA_TRIM; /**< Internal */
|
||||
reg32_t __reserved18[3]; /**< meh */
|
||||
reg32_t DAC_BIAS_CNF; /**< Internal */
|
||||
reg32_t __reserved19[2]; /**< meh */
|
||||
reg32_t TFW_PROBE; /**< Internal */
|
||||
reg32_t TFW_FT; /**< Internal */
|
||||
reg32_t DAC_CAL0; /**< Internal */
|
||||
reg32_t DAC_CAL1; /**< Internal */
|
||||
reg32_t DAC_CAL2; /**< Internal */
|
||||
reg32_t DAC_CAL3; /**< Internal */
|
||||
} fcfg_regs_t;
|
||||
|
||||
#define FCFG ((fcfg_regs_t *) (FCFG_BASE)) /**< FCFG register bank */
|
||||
|
||||
#ifdef __cplusplus
|
||||
} /* end extern "C" */
|
||||
#endif
|
||||
|
||||
#endif /* CC13X2_FCFG_H */
|
||||
|
||||
/*@}*/
|
||||
237
cpu/cc13x2/include/cc13x2_prcm.h
Normal file
237
cpu/cc13x2/include/cc13x2_prcm.h
Normal file
@ -0,0 +1,237 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Leon George
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_cc13x2_definitions
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief CC13x2 PRCM register definitions
|
||||
*/
|
||||
|
||||
#ifndef CC13X2_PRCM_H
|
||||
#define CC13X2_PRCM_H
|
||||
|
||||
#include <cc26xx_cc13xx.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* DDI_0_OSC registers
|
||||
*/
|
||||
typedef struct {
|
||||
reg32_t CTL0; /**< control 0 */
|
||||
reg32_t CTL1; /**< control 1 */
|
||||
reg32_t RADCEXTCFG; /**< RADC external config */
|
||||
reg32_t AMPCOMPCTL; /**< amplitude compensation control */
|
||||
reg32_t AMPCOMPTH1; /**< amplitude compensation threshold 1 */
|
||||
reg32_t AMPCOMPTH2; /**< amplitude compensation threshold 2 */
|
||||
reg32_t ANABYPASSVAL1; /**< analog bypass values 1 */
|
||||
reg32_t ANABYPASSVAL2; /**< analog bypass values 2 */
|
||||
reg32_t ATESTCTL; /**< analog test control */
|
||||
reg32_t ADCDOUBLERNANOAMPCTL; /**< ADC doubler nanoamp control */
|
||||
reg32_t XOSCHFCTL; /**< XOSCHF control */
|
||||
reg32_t LFOSCCTL; /**< low frequency oscillator control */
|
||||
reg32_t RCOSCHFCTL; /**< RCOSCHF control */
|
||||
reg32_t RCOSCHMCTL; /**< RCOSCHM control */
|
||||
reg32_t STAT0; /**< status 0 */
|
||||
reg32_t STAT1; /**< status 1 */
|
||||
reg32_t STAT2; /**< status 2 */
|
||||
} ddi0_osc_regs_t;
|
||||
|
||||
/**
|
||||
* @brief DDI_0_OSC register values
|
||||
* @{
|
||||
*/
|
||||
#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL 0x00000001
|
||||
#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL 0x0000000C
|
||||
#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL 0x00000180
|
||||
#define DDI_0_OSC_CTL0_CLK_LOSS_EN 0x00000200 /* enable clock loss detection */
|
||||
#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS 0x00000400 /* bypass XOSC_LF and use digital input clock from AON foor xosx_lf (precuations in datasheet) */
|
||||
#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE 0x00000800
|
||||
#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED 0x00001000
|
||||
#define DDI_0_OSC_CTL0_HPOSC_MODE_EN 0x00004000
|
||||
#define DDI_0_OSC_CTL0_DCDC_SRC_SEL 0x01000000
|
||||
#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION 0x02000000
|
||||
#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION 0x0C000000
|
||||
#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL 0x10000000
|
||||
#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL 0x20000000
|
||||
#define DDI_0_OSC_CTL0_XTAL_IS_24M 0x80000000
|
||||
/** @} */
|
||||
|
||||
/** @ingroup cpu_cc13x2_peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
#define DDI0_OSC_BASE 0x400CA000 /**< DDI0_OSC base address */
|
||||
/*@}*/
|
||||
|
||||
#define DDI_0_OSC ((ddi0_osc_regs_t *) (DDI0_OSC_BASE)) /**< DDI_0_OSC register bank */
|
||||
|
||||
/**
|
||||
* AON_PMCTL registers
|
||||
*/
|
||||
typedef struct {
|
||||
reg32_t __reserved1; /**< meh */
|
||||
reg32_t AUXSCECLK; /**< AUX SCE management */
|
||||
reg32_t RAMCFG; /**< RAM configuration */
|
||||
reg32_t __reserved2; /**< meh */
|
||||
reg32_t PWRCTL; /**< Power management control */
|
||||
reg32_t PWRSTAT; /**< Power status */
|
||||
reg32_t SHUTDOWN; /**< Shutdown control */
|
||||
reg32_t RECHARGECFG; /**< Recharge controller configuration */
|
||||
reg32_t RECHARGESTAT; /**< Recharge controller status */
|
||||
reg32_t OSCCFG; /**< Oscillator configuration */
|
||||
reg32_t RESETCTL; /**< Reset control */
|
||||
reg32_t SLEEPCTL; /**< Reset control */
|
||||
reg32_t __reserved3; /**< meh */
|
||||
reg32_t JTAGCFG; /**< JTAG configuration */
|
||||
reg32_t JTAGUSERCODE; /**< JTAG USERCODE */
|
||||
} aon_pmctl_regs_t;
|
||||
|
||||
/** @ingroup cpu_specific_peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
#define AON_PMCTL_BASE 0x40090000 /**< AON_PMCTL base address */
|
||||
/*@}*/
|
||||
|
||||
#define AON_PMCTL ((aon_pmctl_regs_t *) (AON_PMCTL_BASE)) /**< AON_PMCTL register bank */
|
||||
|
||||
/**
|
||||
* PRCM registers
|
||||
*/
|
||||
typedef struct {
|
||||
reg32_t INFRCLKDIVR; /**< infrastructure clock division factor for run mode */
|
||||
reg32_t INFRCLKDIVS; /**< infrastructure clock division factor for sleep mode */
|
||||
reg32_t INFRCLKDIVDS; /**< infrastructure clock division factor for deep sleep mode */
|
||||
reg32_t VDCTL; /**< MCU voltage domain control */
|
||||
reg32_t __reserved1[6]; /**< meh */
|
||||
reg32_t CLKLOADCTL; /**< clock load control */
|
||||
reg32_t RFCCLKG; /**< RFC clock gate */
|
||||
reg32_t VIMSCLKG; /**< VIMS clock gate */
|
||||
reg32_t __reserved2[2]; /**< meh */
|
||||
reg32_t SECDMACLKGR; /**< TRNG, CRYPTO, and UDMA clock gate for run mode */
|
||||
reg32_t SECDMACLKGS; /**< TRNG, CRYPTO, and UDMA clock gate for sleep mode */
|
||||
reg32_t SECDMACLKGDS; /**< TRNG, CRYPTO, and UDMA clock gate for deep sleep mode */
|
||||
reg32_t GPIOCLKGR; /**< GPIO clock gate for run mode */
|
||||
reg32_t GPIOCLKGS; /**< GPIO clock gate for sleep mode */
|
||||
reg32_t GPIOCLKGDS; /**< GPIO clock gate for deep sleep mode */
|
||||
reg32_t GPTCLKGR; /**< GPT clock gate for run mode */
|
||||
reg32_t GPTCLKGS; /**< GPT clock gate for sleep mode */
|
||||
reg32_t GPTCLKGDS; /**< GPT clock gate for deep sleep mode */
|
||||
reg32_t I2CCLKGR; /**< I2C clock gate for run mode */
|
||||
reg32_t I2CCLKGS; /**< I2C clock gate for sleep mode */
|
||||
reg32_t I2CCLKGDS; /**< I2C clock gate for deep sleep mode */
|
||||
reg32_t UARTCLKGR; /**< UART clock gate for run mode */
|
||||
reg32_t UARTCLKGS; /**< UART clock gate for sleep mode */
|
||||
reg32_t UARTCLKGDS; /**< UART clock gate for deep sleep mode */
|
||||
reg32_t SSICLKGR; /**< SSI clock gate for run mode */
|
||||
reg32_t SSICLKGS; /**< SSI clock gate for sleep mode */
|
||||
reg32_t SSICLKGDS; /**< SSI clock gate for deep sleep mode */
|
||||
reg32_t I2SCLKGR; /**< I2S clock gate for run mode */
|
||||
reg32_t I2SCLKGS; /**< I2S clock gate for sleep mode */
|
||||
reg32_t I2SCLKGDS; /**< I2S clock gate for deep sleep mode */
|
||||
reg32_t __reserved3[9]; /**< meh */
|
||||
reg32_t SYSBUSCLKDIV; /**< System bus clock division factor */
|
||||
reg32_t CPUCLKDIV; /**< CPU clock division factor */
|
||||
reg32_t PERBUSCPUCLKDIV; /**< Peripheral bus division factor */
|
||||
reg32_t __reserved4; /**< meh */
|
||||
reg32_t PERDMACLKDIV; /**< DMA clock division factor */
|
||||
reg32_t I2SBCLKSEL; /**< I2S clock select */
|
||||
reg32_t GPTCLKDIV; /**< GPT scalar */
|
||||
reg32_t I2SCLKCTL; /**< I2S clock control */
|
||||
reg32_t I2SMCLKDIV; /**< MCLK division ratio */
|
||||
reg32_t I2SBCLKDIV; /**< BCLK division ratio */
|
||||
reg32_t I2SWCLKDIV; /**< WCLK division ratio */
|
||||
reg32_t __reserved5[4]; /**< meh */
|
||||
reg32_t RESETSECDMA; /**< Reset SEC and UDMA */
|
||||
reg32_t RESETGPIO; /**< Reset GPIO */
|
||||
reg32_t RESETGPT; /**< Reset GPTs */
|
||||
reg32_t RESETI2C; /**< Reset I2C */
|
||||
reg32_t RESETUART; /**< Reset UART */
|
||||
reg32_t RESETSSI; /**< Reset SSI */
|
||||
reg32_t RESETI2S; /**< Reset I2S */
|
||||
reg32_t __reserved6[8]; /**< meh */
|
||||
reg32_t PDCTL0; /**< power domain control */
|
||||
reg32_t PDCTL0RFC; /**< RFC power domain control */
|
||||
reg32_t PDCTL0SERIAL; /**< SERIAL power domain control */
|
||||
reg32_t PDCTL0PERIPH; /**< PERIPH power domain control */
|
||||
reg32_t __reserved7; /**< meh */
|
||||
reg32_t PDSTAT0; /**< power domain status */
|
||||
reg32_t PDSTAT0RFC; /**< RFC power domain status */
|
||||
reg32_t PDSTAT0SERIAL; /**< SERIAL power domain status */
|
||||
reg32_t PDSTAT0PERIPH; /**< PERIPH power domain status */
|
||||
reg32_t __reserved8[11]; /**< meh */
|
||||
reg32_t PDCTL1; /**< power domain control */
|
||||
reg32_t __reserved9; /**< power domain control */
|
||||
reg32_t PDCTL1CPU; /**< CPU power domain control */
|
||||
reg32_t PDCTL1RFC; /**< RFC power domain control */
|
||||
reg32_t PDCTL1VIMS; /**< VIMS power domain control */
|
||||
reg32_t __reserved10; /**< meh */
|
||||
reg32_t PDSTAT1; /**< power domain status */
|
||||
reg32_t PDSTAT1BUS; /**< BUS power domain status */
|
||||
reg32_t PDSTAT1RFC; /**< RFC power domain status */
|
||||
reg32_t PDSTAT1CPU; /**< CPU power domain status */
|
||||
reg32_t PDSTAT1VIMS; /**< VIMS power domain status */
|
||||
reg32_t __reserved11[9]; /**< meh */
|
||||
reg32_t RFCBITS; /**< Control to RFC */
|
||||
reg32_t RFCMODESEL; /**< selected RFC mode */
|
||||
reg32_t RFCMODEHWOPT; /**< allowed RFC modes */
|
||||
reg32_t __reserved12[2]; /**< meh */
|
||||
reg32_t PWRPROFSTAT; /**< power profiler register */
|
||||
reg32_t __reserved13[14]; /**< meh */
|
||||
reg32_t MCUSRAMCFG; /**< MCU SRAM configuration */
|
||||
reg32_t __reserved14; /**< meh */
|
||||
reg32_t RAMRETEN; /**< memory retention control */
|
||||
reg32_t __reserved15[27]; /**< meh */
|
||||
reg32_t OSCIMSC; /**< oscillator interrupt mask */
|
||||
reg32_t OSCRIS; /**< oscillator raw interrupt status */
|
||||
reg32_t OSCICR; /**< oscillator raw interrupt clear */
|
||||
} prcm_regs_t;
|
||||
|
||||
/**
|
||||
* @brief PRCM register values
|
||||
* @{
|
||||
*/
|
||||
#define CLKLOADCTL_LOAD 0x1
|
||||
#define CLKLOADCTL_LOADDONE 0x2
|
||||
|
||||
#define PDCTL0_RFC_ON 0x1
|
||||
#define PDCTL0_SERIAL_ON 0x2
|
||||
#define PDCTL0_PERIPH_ON 0x4
|
||||
|
||||
#define PDSTAT0_RFC_ON 0x1
|
||||
#define PDSTAT0_SERIAL_ON 0x2
|
||||
#define PDSTAT0_PERIPH_ON 0x4
|
||||
|
||||
#define PDCTL1_CPU_ON 0x2
|
||||
#define PDCTL1_RFC_ON 0x4
|
||||
#define PDCTL1_VIMS_ON 0x8
|
||||
|
||||
#define PDSTAT1_CPU_ON 0x2
|
||||
#define PDSTAT1_RFC_ON 0x4
|
||||
#define PDSTAT1_VIMS_ON 0x8
|
||||
/** @} */
|
||||
|
||||
/** @ingroup cpu_specific_peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
#define PRCM_BASE 0x40082000 /**< PRCM base address */
|
||||
/*@}*/
|
||||
|
||||
#define PRCM ((prcm_regs_t *) (PRCM_BASE)) /**< PRCM register bank */
|
||||
|
||||
#ifdef __cplusplus
|
||||
} /* end extern "C" */
|
||||
#endif
|
||||
|
||||
#endif /* CC13X2_PRCM_H */
|
||||
|
||||
/*@}*/
|
||||
40
cpu/cc13x2/include/cpu_conf.h
Normal file
40
cpu/cc13x2/include/cpu_conf.h
Normal file
@ -0,0 +1,40 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Leon George
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_cc13x2
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Implementation specific CPU configuration options
|
||||
*
|
||||
* @author Leon M. George <leon@georgemail.eu>
|
||||
* @author Anton Gerasimov <tossel@gmail.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef CPU_CONF_H
|
||||
#define CPU_CONF_H
|
||||
|
||||
#define __FPU_PRESENT 1U /**< Presence of FPU */
|
||||
#include "cpu_conf_cc26xx_cc13xx.h"
|
||||
|
||||
#include "cc13x2_aux.h"
|
||||
#include "cc13x2_fcfg.h"
|
||||
#include "cc13x2_prcm.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* CPU_CONF_H */
|
||||
/** @} */
|
||||
35
cpu/cc13x2/include/periph_cpu.h
Normal file
35
cpu/cc13x2/include/periph_cpu.h
Normal file
@ -0,0 +1,35 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Leon George
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_cc13x2
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief CPU specific definitions for internal peripheral handling
|
||||
*
|
||||
* @author Leon M. George <leon@georgemail.de>
|
||||
*/
|
||||
|
||||
#ifndef PERIPH_CPU_H
|
||||
#define PERIPH_CPU_H
|
||||
|
||||
#include "periph_cpu_common.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// Empty, but makes linter happy
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PERIPH_CPU_H */
|
||||
/** @} */
|
||||
19
cpu/cc13x2/ldscripts/cc1352r1.ld
Normal file
19
cpu/cc13x2/ldscripts/cc1352r1.ld
Normal file
@ -0,0 +1,19 @@
|
||||
/**
|
||||
* @addtogroup cpu_cc13x2
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief linker script for cc13x2 MCUs
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Memory Space Definitions: */
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x58000
|
||||
gpram : ORIGIN = 0x11000000, LENGTH = 8K /* configurable as cache. 20K here, 8K there, and 2K in the ld-script of cc13x2ware */
|
||||
ram (w!rx) : ORIGIN = 0x20000000, LENGTH = 20K /* sram */
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
1
cpu/cc13x2/periph/Makefile
Normal file
1
cpu/cc13x2/periph/Makefile
Normal file
@ -0,0 +1 @@
|
||||
include $(RIOTMAKE)/periph.mk
|
||||
32
cpu/cc13x2/pm.c
Normal file
32
cpu/cc13x2/pm.c
Normal file
@ -0,0 +1,32 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Kaspar Schleiser <kaspar@schleiser.de
|
||||
* 2017 Freie Universität Berlin
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_cortexm_common
|
||||
* @ingroup drivers_periph_pm
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief common periph/pm functions
|
||||
*
|
||||
* @author Kaspar Schleiser <kaspar@schleiser.de>
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
#include "cpu.h"
|
||||
#include "periph/pm.h"
|
||||
|
||||
#ifdef PROVIDES_PM_SET_LOWEST_CORTEXM
|
||||
void pm_set_lowest(void)
|
||||
{
|
||||
/* don't do anything here */
|
||||
}
|
||||
#endif
|
||||
Loading…
x
Reference in New Issue
Block a user