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stm32: Adapt to flashpage/flashpage_pagewise API

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This commit is contained in:
Koen Zandberg 2020-11-09 16:45:22 +01:00
parent 72d7a903a2
commit 1c063a74ea
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GPG Key ID: 0895A893E6D2985B
13 changed files with 36 additions and 41 deletions
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2
cpu/stm32/Makefile.features
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@ -11,7 +11,7 @@ FEATURES_PROVIDED += periph_wdt
ifneq (,$(filter $(CPU_FAM),f0 f1 f3 g0 g4 l0 l1 l4 l5 wb)) ifneq (,$(filter $(CPU_FAM),f0 f1 f3 g0 g4 l0 l1 l4 l5 wb))
FEATURES_PROVIDED += periph_flashpage FEATURES_PROVIDED += periph_flashpage
FEATURES_PROVIDED += periph_flashpage_raw FEATURES_PROVIDED += periph_flashpage_pagewise
endif endif
ifneq (,$(filter $(CPU_FAM),l0 l1)) ifneq (,$(filter $(CPU_FAM),l0 l1))

10
cpu/stm32/include/cpu_conf.h
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@ -116,20 +116,20 @@ extern "C" {
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \ #if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \ defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
defined(CPU_FAM_STM32L5) defined(CPU_FAM_STM32L5)
#define FLASHPAGE_RAW_BLOCKSIZE (8U) #define FLASHPAGE_WRITE_BLOCK_SIZE (8U)
#elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1) #elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
#define FLASHPAGE_RAW_BLOCKSIZE (4U) #define FLASHPAGE_WRITE_BLOCK_SIZE (4U)
#else #else
#define FLASHPAGE_RAW_BLOCKSIZE (2U) #define FLASHPAGE_WRITE_BLOCK_SIZE (2U)
#endif #endif
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \ #if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \ defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
defined(CPU_FAM_STM32L5) defined(CPU_FAM_STM32L5)
#define FLASHPAGE_RAW_ALIGNMENT (8U) #define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (8U)
#else #else
/* Writing should be always 4 bytes aligned */ /* Writing should be always 4 bytes aligned */
#define FLASHPAGE_RAW_ALIGNMENT (4U) #define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4U)
#endif #endif
/** @} */ /** @} */

2
cpu/stm32/kconfigs/f0/Kconfig
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@ -14,7 +14,7 @@ config CPU_FAM_F0
select CPU_CORE_CORTEX_M0 select CPU_CORE_CORTEX_M0
select HAS_CPU_STM32F0 select HAS_CPU_STM32F0
select HAS_PERIPH_FLASHPAGE select HAS_PERIPH_FLASHPAGE
select HAS_PERIPH_FLASHPAGE_RAW select HAS_PERIPH_FLASHPAGE_PAGEWISE
config HAS_CPU_STM32F0 config HAS_CPU_STM32F0
bool bool

2
cpu/stm32/kconfigs/f1/Kconfig
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@ -11,7 +11,7 @@ config CPU_FAM_F1
select CPU_CORE_CORTEX_M3 select CPU_CORE_CORTEX_M3
select HAS_CPU_STM32F1 select HAS_CPU_STM32F1
select HAS_PERIPH_FLASHPAGE select HAS_PERIPH_FLASHPAGE
select HAS_PERIPH_FLASHPAGE_RAW select HAS_PERIPH_FLASHPAGE_PAGEWISE
config CPU_FAM config CPU_FAM
default "f1" if CPU_FAM_F1 default "f1" if CPU_FAM_F1

2
cpu/stm32/kconfigs/f3/Kconfig
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@ -11,7 +11,7 @@ config CPU_FAM_F3
select CPU_CORE_CORTEX_M4F select CPU_CORE_CORTEX_M4F
select HAS_CPU_STM32F3 select HAS_CPU_STM32F3
select HAS_PERIPH_FLASHPAGE select HAS_PERIPH_FLASHPAGE
select HAS_PERIPH_FLASHPAGE_RAW select HAS_PERIPH_FLASHPAGE_PAGEWISE
config CPU_FAM config CPU_FAM
default "f3" if CPU_FAM_F3 default "f3" if CPU_FAM_F3

2
cpu/stm32/kconfigs/g0/Kconfig
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@ -11,7 +11,7 @@ config CPU_FAM_G0
select CPU_CORE_CORTEX_M0PLUS select CPU_CORE_CORTEX_M0PLUS
select HAS_CPU_STM32G0 select HAS_CPU_STM32G0
select HAS_PERIPH_FLASHPAGE select HAS_PERIPH_FLASHPAGE
select HAS_PERIPH_FLASHPAGE_RAW select HAS_PERIPH_FLASHPAGE_PAGEWISE
config CPU_FAM config CPU_FAM
default "g0" if CPU_FAM_G0 default "g0" if CPU_FAM_G0

2
cpu/stm32/kconfigs/g4/Kconfig
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@ -12,7 +12,7 @@ config CPU_FAM_G4
select HAS_CPU_STM32G4 select HAS_CPU_STM32G4
select HAS_CORTEXM_MPU select HAS_CORTEXM_MPU
select HAS_PERIPH_FLASHPAGE select HAS_PERIPH_FLASHPAGE
select HAS_PERIPH_FLASHPAGE_RAW select HAS_PERIPH_FLASHPAGE_PAGEWISE
select HAS_PERIPH_HWRNG select HAS_PERIPH_HWRNG
config CPU_FAM config CPU_FAM

2
cpu/stm32/kconfigs/l0/Kconfig
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@ -11,7 +11,7 @@ config CPU_FAM_L0
select CPU_CORE_CORTEX_M0PLUS select CPU_CORE_CORTEX_M0PLUS
select HAS_CPU_STM32L0 select HAS_CPU_STM32L0
select HAS_PERIPH_FLASHPAGE select HAS_PERIPH_FLASHPAGE
select HAS_PERIPH_FLASHPAGE_RAW select HAS_PERIPH_FLASHPAGE_PAGEWISE
select HAS_PERIPH_EEPROM select HAS_PERIPH_EEPROM
config CPU_FAM config CPU_FAM

2
cpu/stm32/kconfigs/l1/Kconfig
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@ -12,7 +12,7 @@ config CPU_FAM_L1
select HAS_CPU_STM32L1 select HAS_CPU_STM32L1
select HAS_CORTEXM_MPU select HAS_CORTEXM_MPU
select HAS_PERIPH_FLASHPAGE select HAS_PERIPH_FLASHPAGE
select HAS_PERIPH_FLASHPAGE_RAW select HAS_PERIPH_FLASHPAGE_PAGEWISE
select HAS_PERIPH_EEPROM select HAS_PERIPH_EEPROM
config CPU_FAM config CPU_FAM

2
cpu/stm32/kconfigs/l4/Kconfig
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@ -12,7 +12,7 @@ config CPU_FAM_L4
select HAS_CPU_STM32L4 select HAS_CPU_STM32L4
select HAS_CORTEXM_MPU select HAS_CORTEXM_MPU
select HAS_PERIPH_FLASHPAGE select HAS_PERIPH_FLASHPAGE
select HAS_PERIPH_FLASHPAGE_RAW select HAS_PERIPH_FLASHPAGE_PAGEWISE
select HAS_PERIPH_HWRNG select HAS_PERIPH_HWRNG
config CPU_FAM config CPU_FAM

2
cpu/stm32/kconfigs/l5/Kconfig
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@ -11,7 +11,7 @@ config CPU_FAM_L5
select CPU_CORE_CORTEX_M33 select CPU_CORE_CORTEX_M33
select HAS_CPU_STM32L5 select HAS_CPU_STM32L5
select HAS_PERIPH_FLASHPAGE select HAS_PERIPH_FLASHPAGE
select HAS_PERIPH_FLASHPAGE_RAW select HAS_PERIPH_FLASHPAGE_PAGEWISE
select HAS_PERIPH_HWRNG select HAS_PERIPH_HWRNG
config CPU_FAM config CPU_FAM

2
cpu/stm32/kconfigs/wb/Kconfig
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@ -11,7 +11,7 @@ config CPU_FAM_WB
select CPU_CORE_CORTEX_M4 select CPU_CORE_CORTEX_M4
select HAS_CPU_STM32WB select HAS_CPU_STM32WB
select HAS_PERIPH_FLASHPAGE select HAS_PERIPH_FLASHPAGE
select HAS_PERIPH_FLASHPAGE_RAW select HAS_PERIPH_FLASHPAGE_PAGEWISE
select HAS_PERIPH_HWRNG select HAS_PERIPH_HWRNG
config CPU_FAM config CPU_FAM

45
cpu/stm32/periph/flashpage.c
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@ -163,15 +163,30 @@ static void _erase_page(void *page_addr)
#endif #endif
} }
void flashpage_write_raw(void *target_addr, const void *data, size_t len) void flashpage_erase(unsigned page)
{ {
/* assert multiples of FLASHPAGE_RAW_BLOCKSIZE are written and no less of assert(page < (int)FLASHPAGE_NUMOF);
/* ensure there is no attempt to write to CPU2 protected area */
#if defined(CPU_FAM_STM32WB)
assert(page < (int)(FLASH->SFR & FLASH_SFR_SFSA));
#endif
void *page_addr = flashpage_addr(page);
/* ERASE sequence */
_erase_page(page_addr);
}
void flashpage_write(void *target_addr, const void *data, size_t len)
{
/* assert multiples of FLASHPAGE_WRITE_BLOCK_SIZE are written and no less of
that length. */ that length. */
assert(!(len % FLASHPAGE_RAW_BLOCKSIZE)); assert(!(len % FLASHPAGE_WRITE_BLOCK_SIZE));
/* ensure writes are aligned */ /* ensure writes are aligned */
assert(!(((unsigned)target_addr % FLASHPAGE_RAW_ALIGNMENT) || assert(!(((unsigned)target_addr % FLASHPAGE_WRITE_BLOCK_ALIGNMENT) ||
((unsigned)data % FLASHPAGE_RAW_ALIGNMENT))); ((unsigned)data % FLASHPAGE_WRITE_BLOCK_ALIGNMENT)));
/* ensure the length doesn't exceed the actual flash size */ /* ensure the length doesn't exceed the actual flash size */
assert(((unsigned)target_addr + len) < assert(((unsigned)target_addr + len) <
@ -238,23 +253,3 @@ void flashpage_write_raw(void *target_addr, const void *data, size_t len)
} }
#endif #endif
} }
void flashpage_write(int page, const void *data)
{
assert(page < (int)FLASHPAGE_NUMOF);
/* ensure there is no attempt to write to CPU2 protected area */
#if defined(CPU_FAM_STM32WB)
assert(page < (int)(FLASH->SFR & FLASH_SFR_SFSA));
#endif
void *page_addr = flashpage_addr(page);
/* ERASE sequence */
_erase_page(page_addr);
/* WRITE sequence */
if (data != NULL) {
flashpage_write_raw(page_addr, data, FLASHPAGE_SIZE);
}
}