Merge pull request #14516 from benpicco/bitband_hw

cortexm_common: fix check for bitbanding feature

cpu/cc2538/include/cpu_conf.h

@@ -40,6 +40,7 @@ extern "C" {
 #define CPU_DEFAULT_IRQ_PRIO            (1U)
 #define CPU_IRQ_NUMOF                   PERIPH_COUNT_IRQn
 #define CPU_FLASH_BASE                  FLASH_BASE
+#define CPU_HAS_BITBAND                 (1)
 /** @} */
 
 #ifdef __cplusplus

cpu/cc26x0/include/cpu_conf.h

@@ -27,6 +27,11 @@
 #include "cc26x0_fcfg.h"
 #include "cc26x0_prcm.h"
 
+/**
+ * @brief   Bit-Band configuration
+ */
+#define CPU_HAS_BITBAND 1
+
 #ifdef __cplusplus
 extern "C" {
 #endif

cpu/cc26x2_cc13x2/include/cpu_conf.h

@@ -29,6 +29,11 @@
 #include "cc26x2_cc13x2_prcm.h"
 #include "cc26x2_cc13x2_setup.h"
 
+/**
+ * @brief   Bit-Band configuration
+ */
+#define CPU_HAS_BITBAND 1
+
 #ifdef __cplusplus
 extern "C" {
 #endif

cpu/cortexm_common/include/bit.h

@@ -35,16 +35,8 @@ extern "C" {
 #define CPU_HAS_BITBAND 1 || 0 (1 for Cortex-M3 and up, 0 for Cortex-M0)
 #endif
 
-#ifndef CPU_HAS_BITBAND
-#if (__CORTEX_M >= 3)
-#define CPU_HAS_BITBAND 1
-#else
-#define CPU_HAS_BITBAND 0
-#endif
-#endif
-
 #if CPU_HAS_BITBAND || DOXYGEN
-/* Cortex-M3 and higher provide a bitband address space for atomically accessing
+/* Some MCUs provide a bitband address space for atomically accessing
  * single bits of peripheral registers, and sometimes for RAM as well */
 /**
  * @name Bit manipulation functions

cpu/efm32/include/cpu_conf.h

@@ -51,6 +51,15 @@ extern "C" {
 #define FLASHPAGE_RAW_ALIGNMENT    (4U)
 /** @} */
 
+/**
+ * @brief   Bit-Band configuration
+ * @{
+ */
+#ifdef BITBAND_RAM_BASE
+#define CPU_HAS_BITBAND 1
+#endif
+/** @} */
+
 #ifdef __cplusplus
 }
 #endif

cpu/ezr32wg/include/cpu_conf.h

@@ -42,6 +42,15 @@ extern "C" {
 #define CPU_FLASH_BASE                  FLASH_BASE
 /** @} */
 
+/**
+ * @brief   Bit-Band configuration
+ * @{
+ */
+#ifdef BITBAND_RAM_BASE
+#define CPU_HAS_BITBAND 1
+#endif
+/** @} */
+
 #ifdef __cplusplus
 }
 #endif

cpu/kinetis/include/cpu_conf.h

@@ -44,6 +44,15 @@ extern "C"
 {
 #endif
 
+/**
+ * @brief   Bit-Band configuration
+ * @{
+ */
+#ifdef BITBAND_REG32
+#define CPU_HAS_BITBAND 1
+#endif
+/** @} */
+
 #ifdef __cplusplus
 }
 #endif

cpu/lm4f120/include/cpu_conf.h

@@ -58,6 +58,7 @@ extern "C" {
 #define CPU_DEFAULT_IRQ_PRIO            (1U)
 #define CPU_IRQ_NUMOF                   (139U)
 #define CPU_FLASH_BASE                  FLASH_BASE
+#define CPU_HAS_BITBAND                 (1)
 /** @} */
 
 /**

cpu/lpc1768/include/cpu_conf.h

@@ -36,6 +36,7 @@ extern "C" {
 #define CPU_DEFAULT_IRQ_PRIO            (1U)
 #define CPU_IRQ_NUMOF                   (35U)
 #define CPU_FLASH_BASE                  LPC_FLASH_BASE
+#define CPU_HAS_BITBAND                 (1)
 /** @} */
 
 /**

cpu/sam_common/include/cpu_conf.h

@@ -34,6 +34,7 @@ extern "C" {
 #define CPU_DEFAULT_IRQ_PRIO            (1U)
 #define CPU_IRQ_NUMOF                   PERIPH_COUNT_IRQn
 #define CPU_FLASH_BASE                  IFLASH0_ADDR
+#define CPU_HAS_BITBAND                 (1)
 /** @} */
 
 #ifdef __cplusplus

cpu/stm32/include/cpu_conf.h

@@ -174,6 +174,15 @@ extern "C" {
 #endif
 /** @} */
 
+/**
+ * @brief   Bit-Band configuration
+ * @{
+ */
+#ifdef SRAM_BB_BASE
+#define CPU_HAS_BITBAND 1
+#endif
+/** @} */
+
 #ifdef __cplusplus
 }
 #endif