Merge pull request #14691 from gdoffe/mp1_dev
Port of RIOT-OS to stm32mp1
This commit is contained in:
Alexandre Abadie
GitHub
commit
57116e737b
3
boards/common/stm32/dist/stm32mp1.cfg
vendored
Normal file
3
boards/common/stm32/dist/stm32mp1.cfg
vendored
Normal file
@ -0,0 +1,3 @@
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|
source [find target/stm32mp15x.cfg]
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|
reset_config srst_only
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|
$_CHIPNAME.cm4 configure -rtos auto
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@ -40,6 +40,8 @@ static const timer_conf_t timer_config[] = {
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#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
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#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
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defined(CPU_FAM_STM32G4)
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defined(CPU_FAM_STM32G4)
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.rcc_mask = RCC_APB1ENR1_TIM2EN,
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.rcc_mask = RCC_APB1ENR1_TIM2EN,
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#elif CPU_FAM_STM32MP1
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.rcc_mask = RCC_MC_APB1ENSETR_TIM2EN,
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#else
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#else
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.rcc_mask = RCC_APB1ENR_TIM2EN,
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.rcc_mask = RCC_APB1ENR_TIM2EN,
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#endif
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#endif
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17
boards/stm32mp157c-dk2/Kconfig
Normal file
17
boards/stm32mp157c-dk2/Kconfig
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@ -0,0 +1,17 @@
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# Copyright (C) 2020 Savoir-faire Linux
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#
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# This file is subject to the terms and conditions of the GNU Lesser General
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# Public License v2.1. See the file LICENSE in the top level directory for more
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# details.
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config BOARD
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default "stm32mp157c-dk2" if BOARD_STM32MP157C_DK2
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config BOARD_STM32MP157C_DK2
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bool
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default y
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select CPU_MODEL_STM32MP157CAC
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# Put defined MCU peripherals here (in alphabetical order)
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select HAS_PERIPH_TIMER
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select HAS_PERIPH_UART
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3
boards/stm32mp157c-dk2/Makefile
Normal file
3
boards/stm32mp157c-dk2/Makefile
Normal file
@ -0,0 +1,3 @@
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MODULE = board
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include $(RIOTBASE)/Makefile.base
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6
boards/stm32mp157c-dk2/Makefile.dep
Normal file
6
boards/stm32mp157c-dk2/Makefile.dep
Normal file
@ -0,0 +1,6 @@
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USEMODULE += mpu_stack_guard
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# Uncomment this line to build firmware in Engineering mode (BOOT0 off and
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# BOOT2 on).
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# You can also add it in your application Makefile.
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# USEMODULE += stm32mp1_eng_mode
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7
boards/stm32mp157c-dk2/Makefile.features
Normal file
7
boards/stm32mp157c-dk2/Makefile.features
Normal file
@ -0,0 +1,7 @@
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CPU = stm32
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CPU_MODEL = stm32mp157cac
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# Put defined MCU peripherals here (in alphabetical order)
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FEATURES_PROVIDED += periph_gpio
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FEATURES_PROVIDED += periph_timer
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FEATURES_PROVIDED += periph_uart
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20
boards/stm32mp157c-dk2/Makefile.include
Normal file
20
boards/stm32mp157c-dk2/Makefile.include
Normal file
@ -0,0 +1,20 @@
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# we use shared STM32 configuration snippets
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INCLUDES += -I$(RIOTBOARD)/common/stm32/include
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# set default port depending on operating system
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PORT_LINUX ?= /dev/ttyACM0
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PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*)))
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# setup serial terminal
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include $(RIOTMAKE)/tools/serial.inc.mk
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# this board has an on-board ST-link adapter
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DEBUG_ADAPTER = stlink-dap
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OPENOCD_CORE = stm32mp15x.cm4
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GDB_PORT_CORE_OFFSET = 1
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FFLAGS ?= flashr $(FLASHFILE)
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DEBUGGER_FLAGS ?= debugr $(ELFFILE)
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# Setup of programmer and serial is shared between STM32 based boards
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include $(RIOTMAKE)/boards/stm32.inc.mk
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30
boards/stm32mp157c-dk2/board.c
Normal file
30
boards/stm32mp157c-dk2/board.c
Normal file
@ -0,0 +1,30 @@
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/*
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* Copyright (C) 2020 Savoir-faire Linux
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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|
* Public License v2.1. See the file LICENSE in the top level directory for more
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|
* details.
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*/
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/**
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* @ingroup boards_stm32mp157c-dk2
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* @{
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*
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* @file
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* @brief Board specific implementations for the STM32MP157C-DK2 board
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*
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* @author Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
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*
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* @}
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*/
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#include "board.h"
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#include "periph/gpio.h"
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#include <stdio.h>
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void board_init(void)
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|
{
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/* initialize the CPU */
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cpu_init();
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}
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105
boards/stm32mp157c-dk2/doc.txt
Normal file
105
boards/stm32mp157c-dk2/doc.txt
Normal file
@ -0,0 +1,105 @@
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|
/**
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@defgroup boards_stm32mp157c-dk2 STM32MP157C-DK2 board
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@ingroup boards
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@brief Support for the STM32MP157C-DK2 board
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## Overview
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The STM32MP157C-DK2 is a board from ST featuring a double architecture based on
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a dual Cortex-A7 and a Cortex-M4 STM32MP157C microcontroller with 384KB of SRAM
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and no ROM Flash.
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## Hardware
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|
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|
![STM32MP157C-DK2]
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(https://www.st.com/bin/ecommerce/api/image.PF267415.en.feature-description-include-personalized-no-cpn-medium.jpg)
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### MCU
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| MCU | STM32MP157CAC |
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|:---------- |:----------------- |
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| Family | ARM Dual Cortex-A7 & Cortex-M4 |
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| Vendor | ST Microelectronics |
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| RAM | 384Kb for Cortex-M4 |
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| Flash | None but 64KB of RETRAM |
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| Frequency | up to 209MHz |
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| FPU | yes |
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| Timers | 32 (3x watchdog, 2x 4 Cortex-A7 system timers, 1x SysTick, 5x 16-bit Low-Power, 12x 16-bit, 2x 32-bit, 1 RTC) |
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| ADCs | 2x 12-bit (16 channels), 2x 16-bit (16 channels) |
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| UARTs | 4x UART + 4x USART |
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| SPIs | 6 |
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|
| I2Cs | 6 |
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|
| RTC | 1 |
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|
| CAN | 2 |
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| USB | 3 |
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| Vcc | 1.8V - 3.6V |
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| Datasheet | [Datasheet](https://www.st.com/resource/en/datasheet/stm32mp157c.pdf) |
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| Reference Manual | [Reference Manual](https://www.st.com/resource/en/reference_manual/dm00327659-stm32mp157-advanced-armbased-32bit-mpus-stmicroelectronics.pdf) |
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| Programming Manual | [Programming Manual](https://www.st.com/resource/en/programming_manual/dm00046982-stm32-cortexm4-mcus-and-mpus-programming-manual-stmicroelectronics.pdf) |
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| Board Manual | [Board Manual](https://www.st.com/resource/en/user_manual/dm00591354-discovery-kits-with-stm32mp157-mpus-stmicroelectronics.pdf)|
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## Implementation Status
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| Device | ID | Supported | Comments |
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|:------------- |:------------- |:------------- |:------------- |
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| MCU | STM32MP157CAC | partly | |
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| Low-level driver | GPIO | yes | |
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| | UART | 1 UART | USART3 on PB12(RX)/PB10(TX) |
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| | Timer | one 32 bit timer | TIM2 |
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|
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## Flashing the device
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|
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Note that the STM32MP157C-DK2 board has no ROM Flash, thus the firmware
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needs to be reflashed each time the board is rebooted.
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|
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### Boot selection jumper:
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| BOOT mode | BOOT0 | BOOT2 |
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| :-------- |:----- |:----- |
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| Engineering | 1 | 1 |
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| SD Card (Linux) | 0 | 1 |
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|
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### Engineering mode
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|
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The STM32MP157C-DK2 board includes an on-board ST-LINK V2 programmer. The
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easiest way to program the board is to use OpenOCD. Once you have installed
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|
OpenOCD (look [here](https://github.com/RIOT-OS/RIOT/wiki/OpenOCD) for
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|
installation instructions), you can flash the board simply by typing inside
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your application directory:
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```
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USEMODULE='stm32mp1_eng_mode' make BOARD=stm32mp157c-dk2 flash
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```
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and debug via GDB by simply typing
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|
```
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USEMODULE='stm32mp1_eng_mode' make BOARD=stm32mp157c-dk2 debug
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|
```
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### SD Card (Linux) mode
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|
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|
This assumes that Linux is booted and that your Linux kernel supports STM32
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remoteproc framework.
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Build the firmware inside your application directory:
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|
```
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|
make BOARD=stm32mp157c-dk2
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|
```
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|
Copy your firmware firmware.elf in /lib/firmwares on the Linux system.
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|
(replace firmware.elf by your firmware filename)
|
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|
|
||||||
|
Then simply launch this commands on the Linux system as root user:
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```
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echo firmware.elf > /sys/class/remoteproc/remoteproc0/firmware
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echo start > /sys/class/remoteproc/remoteproc0/state
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|
```
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|
|
||||||
|
You can stop RIOT from Linux command line:
|
||||||
|
```
|
||||||
|
echo stop > /sys/class/remoteproc/remoteproc0/state
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|
```
|
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|
|
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|
## Supported Toolchains
|
||||||
|
|
||||||
|
For using the STM32MP157C-DK2 board we strongly recommend the usage of the
|
||||||
|
[GNU Tools for ARM Embedded Processors](https://launchpad.net/gcc-arm-embedded)
|
||||||
|
toolchain.
|
||||||
|
*/
|
||||||
41
boards/stm32mp157c-dk2/include/board.h
Normal file
41
boards/stm32mp157c-dk2/include/board.h
Normal file
@ -0,0 +1,41 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (C) 2020 Savoir-faire Linux
|
||||||
|
*
|
||||||
|
* This file is subject to the terms and conditions of the GNU Lesser General
|
||||||
|
* Public License v2.1. See the file LICENSE in the top level directory for more
|
||||||
|
* details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @ingroup boards_stm32mp157c-dk2
|
||||||
|
* @{
|
||||||
|
*
|
||||||
|
* @file
|
||||||
|
* @brief Board specific definitions for the STM32MP157C-DK2 board
|
||||||
|
*
|
||||||
|
* @author Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
|
||||||
|
*
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef BOARD_H
|
||||||
|
#define BOARD_H
|
||||||
|
|
||||||
|
#include "cpu.h"
|
||||||
|
#include "periph_conf.h"
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initialize board specific hardware
|
||||||
|
*/
|
||||||
|
void board_init(void);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* BOARD_H */
|
||||||
|
/** @} */
|
||||||
78
boards/stm32mp157c-dk2/include/periph_conf.h
Normal file
78
boards/stm32mp157c-dk2/include/periph_conf.h
Normal file
@ -0,0 +1,78 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (C) 2020 Savoir-faire Linux
|
||||||
|
*
|
||||||
|
* This file is subject to the terms and conditions of the GNU Lesser General
|
||||||
|
* Public License v2.1. See the file LICENSE in the top level directory for more
|
||||||
|
* details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @ingroup boards_stm32mp157c-dk2
|
||||||
|
* @{
|
||||||
|
*
|
||||||
|
* @file
|
||||||
|
* @brief Board specific implementations for the STM32MP157C-DK2 board
|
||||||
|
*
|
||||||
|
* @author Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef PERIPH_CONF_H
|
||||||
|
#define PERIPH_CONF_H
|
||||||
|
|
||||||
|
/* This board provides an LSE */
|
||||||
|
#ifndef CONFIG_BOARD_HAS_LSE
|
||||||
|
#define CONFIG_BOARD_HAS_LSE 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* This board provides an HSE */
|
||||||
|
#ifndef CONFIG_BOARD_HAS_HSE
|
||||||
|
#define CONFIG_BOARD_HAS_HSE 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "periph_cpu.h"
|
||||||
|
#include "clk_conf.h"
|
||||||
|
#include "cfg_timer_tim2.h"
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @name UART configuration
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
static const uart_conf_t uart_config[] = {
|
||||||
|
{
|
||||||
|
.dev = USART3,
|
||||||
|
.rcc_mask = RCC_MC_APB1ENSETR_USART3EN,
|
||||||
|
.rx_pin = GPIO_PIN(PORT_B, 12),
|
||||||
|
.tx_pin = GPIO_PIN(PORT_B, 10),
|
||||||
|
.rx_af = GPIO_AF8,
|
||||||
|
.tx_af = GPIO_AF7,
|
||||||
|
.bus = APB1,
|
||||||
|
.irqn = USART3_IRQn,
|
||||||
|
.type = STM32_USART,
|
||||||
|
#ifdef UART_USE_DMA
|
||||||
|
.dma_stream = 4,
|
||||||
|
.dma_chan = 4,
|
||||||
|
#endif
|
||||||
|
#if IS_USED(MODULE_STM32MP1_ENG_MODE)
|
||||||
|
.clk_src = RCC_UART35CKSELR_UART35SRC_4, /* HSE clock source */
|
||||||
|
#else
|
||||||
|
.clk_src = RCC_UART35CKSELR_UART35SRC_2, /* HSI clock source */
|
||||||
|
#endif
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
#define UART_0_ISR (isr_usart3)
|
||||||
|
#define UART_0_DMA_ISR (isr_dma1_stream4)
|
||||||
|
|
||||||
|
#define UART_NUMOF ARRAY_SIZE(uart_config)
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* PERIPH_CONF_H */
|
||||||
|
/** @} */
|
||||||
@ -8,14 +8,12 @@
|
|||||||
config CPU_STM32
|
config CPU_STM32
|
||||||
bool
|
bool
|
||||||
select HAS_CPU_STM32
|
select HAS_CPU_STM32
|
||||||
select HAS_BOOTLOADER_STM32
|
|
||||||
select HAS_PERIPH_CPUID
|
select HAS_PERIPH_CPUID
|
||||||
select HAS_PERIPH_GPIO
|
select HAS_PERIPH_GPIO
|
||||||
select HAS_PERIPH_GPIO_IRQ
|
select HAS_PERIPH_GPIO_IRQ
|
||||||
select HAS_PERIPH_TIMER_PERIODIC
|
select HAS_PERIPH_TIMER_PERIODIC
|
||||||
select HAS_PERIPH_UART_MODECFG
|
select HAS_PERIPH_UART_MODECFG
|
||||||
select HAS_PERIPH_UART_NONBLOCKING
|
select HAS_PERIPH_UART_NONBLOCKING
|
||||||
select HAS_PERIPH_WDT
|
|
||||||
|
|
||||||
# Common CPU symbol
|
# Common CPU symbol
|
||||||
config CPU
|
config CPU
|
||||||
|
|||||||
@ -1,13 +1,15 @@
|
|||||||
include $(RIOTCPU)/stm32/stm32_info.mk
|
include $(RIOTCPU)/stm32/stm32_info.mk
|
||||||
|
|
||||||
FEATURES_PROVIDED += bootloader_stm32
|
ifneq (mp1,$(CPU_FAM))
|
||||||
|
FEATURES_PROVIDED += bootloader_stm32
|
||||||
|
FEATURES_PROVIDED += periph_wdt
|
||||||
|
endif
|
||||||
FEATURES_PROVIDED += cpu_stm32$(CPU_FAM)
|
FEATURES_PROVIDED += cpu_stm32$(CPU_FAM)
|
||||||
FEATURES_PROVIDED += periph_cpuid
|
FEATURES_PROVIDED += periph_cpuid
|
||||||
FEATURES_PROVIDED += periph_gpio periph_gpio_irq
|
FEATURES_PROVIDED += periph_gpio periph_gpio_irq
|
||||||
FEATURES_PROVIDED += periph_timer_periodic
|
FEATURES_PROVIDED += periph_timer_periodic
|
||||||
FEATURES_PROVIDED += periph_uart_modecfg
|
FEATURES_PROVIDED += periph_uart_modecfg
|
||||||
FEATURES_PROVIDED += periph_uart_nonblocking
|
FEATURES_PROVIDED += periph_uart_nonblocking
|
||||||
FEATURES_PROVIDED += periph_wdt
|
|
||||||
|
|
||||||
ifneq (,$(filter $(CPU_FAM),f0 f1 f3 g0 g4 l0 l1 l4 l5 wb))
|
ifneq (,$(filter $(CPU_FAM),f0 f1 f3 g0 g4 l0 l1 l4 l5 wb))
|
||||||
FEATURES_PROVIDED += periph_flashpage
|
FEATURES_PROVIDED += periph_flashpage
|
||||||
@ -31,7 +33,7 @@ ifneq (,$(filter $(CPU_FAM),f2 f4 f7 g4 l0 l4 l5 wb))
|
|||||||
endif
|
endif
|
||||||
endif
|
endif
|
||||||
|
|
||||||
ifneq (,$(filter $(CPU_FAM),f2 f4 f7 g4 l1 l4))
|
ifneq (,$(filter $(CPU_FAM),f2 f4 f7 g4 l1 l4 mp1))
|
||||||
FEATURES_PROVIDED += cortexm_mpu
|
FEATURES_PROVIDED += cortexm_mpu
|
||||||
endif
|
endif
|
||||||
|
|
||||||
|
|||||||
@ -55,9 +55,11 @@ $(call target-export-variables,$(VECTORS_O),CPU_LINE)
|
|||||||
# which are only used for STM32 system includes and not of interest for RIOT.
|
# which are only used for STM32 system includes and not of interest for RIOT.
|
||||||
CFLAGS += -D__SYSTEM_STM32$(call uppercase,$(CPU_FAM))XX_H
|
CFLAGS += -D__SYSTEM_STM32$(call uppercase,$(CPU_FAM))XX_H
|
||||||
|
|
||||||
STM32CMSIS_INCLUDE_DIR = $(RIOTCPU)/stm32/include/vendor/cmsis/$(CPU_FAM)/Include
|
ifeq (,$(filter STM32MP157Cxx,$(CPU_LINE)))
|
||||||
STM32FAM_INCLUDE_FILE = $(STM32CMSIS_INCLUDE_DIR)/stm32$(CPU_FAM)xx.h
|
STM32CMSIS_INCLUDE_DIR = $(RIOTCPU)/stm32/include/vendor/cmsis/$(CPU_FAM)/Include
|
||||||
INCLUDES += -I$(STM32CMSIS_INCLUDE_DIR)
|
STM32FAM_INCLUDE_FILE = $(STM32CMSIS_INCLUDE_DIR)/stm32$(CPU_FAM)xx.h
|
||||||
|
INCLUDES += -I$(STM32CMSIS_INCLUDE_DIR)
|
||||||
|
endif
|
||||||
|
|
||||||
# Fetch all CMSIS headers using the package mechanism. This rule is called all
|
# Fetch all CMSIS headers using the package mechanism. This rule is called all
|
||||||
# the time to ensure it's correctly updated when versions in the packages are
|
# the time to ensure it's correctly updated when versions in the packages are
|
||||||
@ -70,19 +72,19 @@ $(STM32FAM_INCLUDE_FILE): FORCE
|
|||||||
$(VECTORS_FILE): $(STM32FAM_INCLUDE_FILE)
|
$(VECTORS_FILE): $(STM32FAM_INCLUDE_FILE)
|
||||||
$(Q)$(RIOTBASE)/cpu/stm32/dist/irqs/gen_vectors.py $(CPU_LINE)
|
$(Q)$(RIOTBASE)/cpu/stm32/dist/irqs/gen_vectors.py $(CPU_LINE)
|
||||||
|
|
||||||
ifneq (STM32F030x4,$(CPU_LINE))
|
ifeq (,$(filter STM32MP157Cxx STM32F030x4,$(CPU_LINE)))
|
||||||
# IRQs of STM32F030x4 family are not available in the CMSIS package so they
|
# IRQs of STM32F030x4 and STM32MP157Cxx lines are not available in the CMSIS
|
||||||
# are hardcoded in RIOTs codebase.
|
# package so they are hardcoded in RIOTs codebase.
|
||||||
# For other lines, the IRQs are automatically generated once from the whole
|
# For other lines, the IRQs are automatically generated once from the whole
|
||||||
# list of CMSIS headers available in a given family
|
# list of CMSIS headers available in a given family
|
||||||
STM32IRQS_INCLUDE_FILE = $(RIOTCPU)/stm32/include/irqs/$(CPU_FAM)/irqs.h
|
STM32IRQS_INCLUDE_FILE = $(RIOTCPU)/stm32/include/irqs/$(CPU_FAM)/irqs.h
|
||||||
BUILDDEPS += $(STM32IRQS_INCLUDE_FILE)
|
BUILDDEPS += $(STM32IRQS_INCLUDE_FILE)
|
||||||
|
endif
|
||||||
|
|
||||||
# The IRQ header for a given family requires the family headers to be fetched
|
# The IRQ header for a given family requires the family headers to be fetched
|
||||||
# before since it's generated from all CMSIS content of that family
|
# before since it's generated from all CMSIS content of that family
|
||||||
$(STM32IRQS_INCLUDE_FILE): $(STM32FAM_INCLUDE_FILE)
|
$(STM32IRQS_INCLUDE_FILE): $(STM32FAM_INCLUDE_FILE)
|
||||||
$(Q)$(RIOTBASE)/cpu/stm32/dist/irqs/gen_irqs.py $(CPU_FAM)
|
$(Q)$(RIOTBASE)/cpu/stm32/dist/irqs/gen_irqs.py $(CPU_FAM)
|
||||||
endif
|
|
||||||
|
|
||||||
# Include clock configuration directory
|
# Include clock configuration directory
|
||||||
INCLUDES += -I$(RIOTCPU)/stm32/include/clk
|
INCLUDES += -I$(RIOTCPU)/stm32/include/clk
|
||||||
|
|||||||
@ -72,13 +72,19 @@ void periph_clk_en(bus_t bus, uint32_t mask)
|
|||||||
RCC->APB1ENR1 |= mask;
|
RCC->APB1ENR1 |= mask;
|
||||||
#elif defined(CPU_FAM_STM32G0)
|
#elif defined(CPU_FAM_STM32G0)
|
||||||
RCC->APBENR1 |= mask;
|
RCC->APBENR1 |= mask;
|
||||||
|
#elif defined(CPU_FAM_STM32MP1)
|
||||||
|
RCC->MC_APB1ENSETR |= mask;
|
||||||
#else
|
#else
|
||||||
RCC->APB1ENR |= mask;
|
RCC->APB1ENR |= mask;
|
||||||
#endif
|
#endif
|
||||||
break;
|
break;
|
||||||
#if !defined(CPU_FAM_STM32G0)
|
#if !defined(CPU_FAM_STM32G0)
|
||||||
case APB2:
|
case APB2:
|
||||||
|
#if defined(CPU_FAM_STM32MP1)
|
||||||
|
RCC->MC_APB2ENSETR |= mask;
|
||||||
|
#else
|
||||||
RCC->APB2ENR |= mask;
|
RCC->APB2ENR |= mask;
|
||||||
|
#endif
|
||||||
break;
|
break;
|
||||||
#endif
|
#endif
|
||||||
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
|
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
|
||||||
@ -119,6 +125,11 @@ void periph_clk_en(bus_t bus, uint32_t mask)
|
|||||||
RCC->AHB3ENR |= mask;
|
RCC->AHB3ENR |= mask;
|
||||||
break;
|
break;
|
||||||
#endif
|
#endif
|
||||||
|
#endif
|
||||||
|
#if defined(CPU_FAM_STM32MP1)
|
||||||
|
case AHB4:
|
||||||
|
RCC->MC_AHB4ENSETR |= mask;
|
||||||
|
break;
|
||||||
#endif
|
#endif
|
||||||
default:
|
default:
|
||||||
DEBUG("unsupported bus %d\n", (int)bus);
|
DEBUG("unsupported bus %d\n", (int)bus);
|
||||||
@ -137,13 +148,20 @@ void periph_clk_dis(bus_t bus, uint32_t mask)
|
|||||||
RCC->APB1ENR1 &= ~(mask);
|
RCC->APB1ENR1 &= ~(mask);
|
||||||
#elif defined(CPU_FAM_STM32G0)
|
#elif defined(CPU_FAM_STM32G0)
|
||||||
RCC->APBENR1 &= ~(mask);
|
RCC->APBENR1 &= ~(mask);
|
||||||
|
#elif defined(CPU_FAM_STM32MP1)
|
||||||
|
/* Write 1 to clear */
|
||||||
|
RCC->MC_APB1ENCLRR |= mask;
|
||||||
#else
|
#else
|
||||||
RCC->APB1ENR &= ~(mask);
|
RCC->APB1ENR &= ~(mask);
|
||||||
#endif
|
#endif
|
||||||
break;
|
break;
|
||||||
#if !defined(CPU_FAM_STM32G0)
|
#if !defined(CPU_FAM_STM32G0)
|
||||||
case APB2:
|
case APB2:
|
||||||
|
#if defined(CPU_FAM_STM32MP1)
|
||||||
|
RCC->MC_APB2ENCLRR |= mask;
|
||||||
|
#else
|
||||||
RCC->APB2ENR &= ~(mask);
|
RCC->APB2ENR &= ~(mask);
|
||||||
|
#endif
|
||||||
break;
|
break;
|
||||||
#endif
|
#endif
|
||||||
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
|
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
|
||||||
|
|||||||
@ -44,7 +44,7 @@
|
|||||||
#define BIT_APB_PWREN RCC_APB1ENR1_PWREN
|
#define BIT_APB_PWREN RCC_APB1ENR1_PWREN
|
||||||
#elif defined (CPU_FAM_STM32G0)
|
#elif defined (CPU_FAM_STM32G0)
|
||||||
#define BIT_APB_PWREN RCC_APBENR1_PWREN
|
#define BIT_APB_PWREN RCC_APBENR1_PWREN
|
||||||
#else
|
#elif !defined(CPU_FAM_STM32MP1)
|
||||||
#define BIT_APB_PWREN RCC_APB1ENR_PWREN
|
#define BIT_APB_PWREN RCC_APB1ENR_PWREN
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
@ -152,7 +152,7 @@ void cpu_init(void)
|
|||||||
/* initialize the Cortex-M core */
|
/* initialize the Cortex-M core */
|
||||||
cortexm_init();
|
cortexm_init();
|
||||||
/* enable PWR module */
|
/* enable PWR module */
|
||||||
#ifndef CPU_FAM_STM32WB
|
#if !defined(CPU_FAM_STM32WB) && !defined(CPU_FAM_STM32MP1)
|
||||||
periph_clk_en(APB1, BIT_APB_PWREN);
|
periph_clk_en(APB1, BIT_APB_PWREN);
|
||||||
#endif
|
#endif
|
||||||
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
|
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
|
||||||
@ -161,8 +161,10 @@ void cpu_init(void)
|
|||||||
defined(CPU_FAM_STM32L1)
|
defined(CPU_FAM_STM32L1)
|
||||||
_gpio_init_ain();
|
_gpio_init_ain();
|
||||||
#endif
|
#endif
|
||||||
|
#if !defined(CPU_FAM_STM32MP1) || IS_USED(MODULE_STM32MP1_ENG_MODE)
|
||||||
/* initialize the system clock as configured in the periph_conf.h */
|
/* initialize the system clock as configured in the periph_conf.h */
|
||||||
stmclk_init_sysclk();
|
stmclk_init_sysclk();
|
||||||
|
#endif
|
||||||
#ifdef MODULE_PERIPH_DMA
|
#ifdef MODULE_PERIPH_DMA
|
||||||
/* initialize DMA streams */
|
/* initialize DMA streams */
|
||||||
dma_init();
|
dma_init();
|
||||||
|
|||||||
53
cpu/stm32/dist/clk_conf/clk_conf.c
vendored
53
cpu/stm32/dist/clk_conf/clk_conf.c
vendored
@ -188,6 +188,10 @@ static void usage(char **argv)
|
|||||||
|
|
||||||
int main(int argc, char **argv)
|
int main(int argc, char **argv)
|
||||||
{
|
{
|
||||||
|
int char_offset = 0;
|
||||||
|
const unsigned int* stm32_model_p = stm32_f_model;
|
||||||
|
const clk_cfg_t* stm32_clk_cfg_p = stm32_f_clk_cfg;
|
||||||
|
int model_max = MODEL_F_MAX;
|
||||||
if (argc < 2) {
|
if (argc < 2) {
|
||||||
usage(argv);
|
usage(argv);
|
||||||
return 1;
|
return 1;
|
||||||
@ -199,23 +203,36 @@ int main(int argc, char **argv)
|
|||||||
|| !isdigit(argv[1][8])
|
|| !isdigit(argv[1][8])
|
||||||
|| ((argv[1][5] != 'f') && (argv[1][5] != 'F')
|
|| ((argv[1][5] != 'f') && (argv[1][5] != 'F')
|
||||||
/* && (argv[1][5] != 'l') && (argv[1][5] != 'L') */)) {
|
/* && (argv[1][5] != 'l') && (argv[1][5] != 'L') */)) {
|
||||||
|
if (strlen(argv[1]) < 10
|
||||||
|
|| !isdigit(argv[1][7])
|
||||||
|
|| !isdigit(argv[1][8])
|
||||||
|
|| !isdigit(argv[1][9])
|
||||||
|
|| ((argv[1][5] != 'm') && (argv[1][5] != 'M'))
|
||||||
|
|| ((argv[1][6] != 'p') && (argv[1][5] != 'p'))
|
||||||
|
) {
|
||||||
fprintf(stderr, "Invalid model : %s\n", argv[1]);
|
fprintf(stderr, "Invalid model : %s\n", argv[1]);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
int model = atoi(argv[1] + 6);
|
char_offset = 1;
|
||||||
|
stm32_model_p = stm32_model_mp;
|
||||||
|
stm32_clk_cfg_p = stm32_mp_clk_cfg;
|
||||||
|
model_max = MODEL_MP_MAX;
|
||||||
|
}
|
||||||
|
|
||||||
|
int model = atoi(argv[1] + 6 + char_offset);
|
||||||
int i;
|
int i;
|
||||||
for (i = 0; i < MODEL_MAX; i++) {
|
for (i = 0; i < model_max; i++) {
|
||||||
if (stm32_model[i] == model) {
|
if (stm32_model_p[i] == model) {
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
if (i == MODEL_MAX) {
|
if (i == model_max) {
|
||||||
fprintf(stderr, "Unsupported CPU model %s\n", argv[1]);
|
fprintf(stderr, "Unsupported CPU model %s\n", argv[1]);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
const clk_cfg_t *cfg = &stm32_clk_cfg[i];
|
const clk_cfg_t *cfg = &stm32_clk_cfg_p[i];
|
||||||
|
|
||||||
/* print help for given cpu */
|
/* print help for given cpu */
|
||||||
if (argc < 5) {
|
if (argc < 5) {
|
||||||
@ -399,6 +416,7 @@ int main(int argc, char **argv)
|
|||||||
/* APB prescalers */
|
/* APB prescalers */
|
||||||
unsigned apb1_pre;
|
unsigned apb1_pre;
|
||||||
unsigned apb2_pre;
|
unsigned apb2_pre;
|
||||||
|
unsigned apb3_pre;
|
||||||
|
|
||||||
for (apb1_pre = 1; apb1_pre <= 16; apb1_pre <<= 1) {
|
for (apb1_pre = 1; apb1_pre <= 16; apb1_pre <<= 1) {
|
||||||
if (coreclock / apb1_pre <= cfg->max_apb1) {
|
if (coreclock / apb1_pre <= cfg->max_apb1) {
|
||||||
@ -412,6 +430,13 @@ int main(int argc, char **argv)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
if (cfg->family == STM32MP1) {
|
||||||
|
for (apb3_pre = 1; apb3_pre <= 16; apb3_pre <<= 1) {
|
||||||
|
if (coreclock / apb3_pre <= cfg->max_apb3) {
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
/* Print constants */
|
/* Print constants */
|
||||||
@ -435,14 +460,32 @@ int main(int argc, char **argv)
|
|||||||
" * 1: external crystal available (always 32.768kHz) */\n"
|
" * 1: external crystal available (always 32.768kHz) */\n"
|
||||||
"#define CLOCK_LSE (%uU)\n", is_lse);
|
"#define CLOCK_LSE (%uU)\n", is_lse);
|
||||||
printf("/* peripheral clock setup */\n");
|
printf("/* peripheral clock setup */\n");
|
||||||
|
|
||||||
|
if (cfg->family != STM32MP1) {
|
||||||
printf("#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1\n"
|
printf("#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1\n"
|
||||||
"#define CLOCK_AHB (CLOCK_CORECLOCK / 1)\n");
|
"#define CLOCK_AHB (CLOCK_CORECLOCK / 1)\n");
|
||||||
|
}
|
||||||
if (cfg->family == STM32F0) {
|
if (cfg->family == STM32F0) {
|
||||||
printf("#define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV%u /* max %uMHz */\n"
|
printf("#define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV%u /* max %uMHz */\n"
|
||||||
"#define CLOCK_APB1 (CLOCK_CORECLOCK / %u)\n",
|
"#define CLOCK_APB1 (CLOCK_CORECLOCK / %u)\n",
|
||||||
apb1_pre, cfg->max_apb1 / 1000000U, apb1_pre);
|
apb1_pre, cfg->max_apb1 / 1000000U, apb1_pre);
|
||||||
printf("#define CLOCK_APB2 (CLOCK_APB1)\n");
|
printf("#define CLOCK_APB2 (CLOCK_APB1)\n");
|
||||||
}
|
}
|
||||||
|
else if (cfg->family == STM32MP1) {
|
||||||
|
/* TODO: Set to 1 by default, conf_clk is not able to handle this parameter */
|
||||||
|
printf("#define CLOCK_MCU_DIV RCC_MCUDIVR_MCUDIV_1 /* max %uMHz */\n"
|
||||||
|
"#define CLOCK_MCU (CLOCK_CORECLOCK / 1)\n",
|
||||||
|
cfg->max_coreclock / 1000000U);
|
||||||
|
printf("#define CLOCK_APB1_DIV RCC_APB1DIVR_APB1DIV_%u /* max %uMHz */\n"
|
||||||
|
"#define CLOCK_APB1 (CLOCK_CORECLOCK / %u)\n",
|
||||||
|
apb1_pre, cfg->max_apb1 / 1000000U, apb1_pre);
|
||||||
|
printf("#define CLOCK_APB2_DIV RCC_APB2DIVR_APB2DIV_%u /* max %uMHz */\n"
|
||||||
|
"#define CLOCK_APB2 (CLOCK_CORECLOCK / %u)\n",
|
||||||
|
apb2_pre, cfg->max_apb2 / 1000000U, apb2_pre);
|
||||||
|
printf("#define CLOCK_APB3_DIV RCC_APB3DIVR_APB3DIV_%u /* max %uMHz */\n"
|
||||||
|
"#define CLOCK_APB3 (CLOCK_CORECLOCK / %u)\n",
|
||||||
|
apb3_pre, cfg->max_apb3 / 1000000U, apb3_pre);
|
||||||
|
}
|
||||||
else {
|
else {
|
||||||
printf("#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV%u /* max %uMHz */\n"
|
printf("#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV%u /* max %uMHz */\n"
|
||||||
"#define CLOCK_APB1 (CLOCK_CORECLOCK / %u)\n",
|
"#define CLOCK_APB1 (CLOCK_CORECLOCK / %u)\n",
|
||||||
|
|||||||
64
cpu/stm32/dist/clk_conf/clk_conf.h
vendored
64
cpu/stm32/dist/clk_conf/clk_conf.h
vendored
@ -35,6 +35,7 @@ enum fam {
|
|||||||
STM32F3,
|
STM32F3,
|
||||||
STM32F4,
|
STM32F4,
|
||||||
STM32F7,
|
STM32F7,
|
||||||
|
STM32MP1,
|
||||||
FAM_MAX,
|
FAM_MAX,
|
||||||
};
|
};
|
||||||
/** @} */
|
/** @} */
|
||||||
@ -106,8 +107,15 @@ enum {
|
|||||||
STM32F777,
|
STM32F777,
|
||||||
STM32F779,
|
STM32F779,
|
||||||
|
|
||||||
MODEL_MAX,
|
MODEL_F_MAX,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
enum {
|
||||||
|
STM32MP157,
|
||||||
|
|
||||||
|
MODEL_MP_MAX,
|
||||||
|
};
|
||||||
|
|
||||||
/** @} */
|
/** @} */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
@ -167,6 +175,7 @@ typedef struct {
|
|||||||
unsigned max_coreclock; /**< Max coreclock */
|
unsigned max_coreclock; /**< Max coreclock */
|
||||||
unsigned max_apb1; /**< Max APB1 clock */
|
unsigned max_apb1; /**< Max APB1 clock */
|
||||||
unsigned max_apb2; /**< Max APB2 clock */
|
unsigned max_apb2; /**< Max APB2 clock */
|
||||||
|
unsigned max_apb3; /**< Max APB3 clock */
|
||||||
|
|
||||||
unsigned hsi; /**< HSI frequency */
|
unsigned hsi; /**< HSI frequency */
|
||||||
|
|
||||||
@ -200,7 +209,7 @@ typedef struct {
|
|||||||
#define STM32F0(x) [STM32F0##x] = x
|
#define STM32F0(x) [STM32F0##x] = x
|
||||||
|
|
||||||
/** List of supported models */
|
/** List of supported models */
|
||||||
static const unsigned stm32_model[] = {
|
static const unsigned stm32_f_model[] = {
|
||||||
STM32F0(30),
|
STM32F0(30),
|
||||||
STM32F0(70),
|
STM32F0(70),
|
||||||
STM32F0(31),
|
STM32F0(31),
|
||||||
@ -264,6 +273,13 @@ static const unsigned stm32_model[] = {
|
|||||||
STM32F(779),
|
STM32F(779),
|
||||||
};
|
};
|
||||||
|
|
||||||
|
#define STM32MP(x) [STM32MP##x] = x
|
||||||
|
|
||||||
|
/** List of supported models */
|
||||||
|
static const unsigned stm32_model_mp[] = {
|
||||||
|
STM32MP(157),
|
||||||
|
};
|
||||||
|
|
||||||
/** STM32F2xx / STM32F401 PLL config */
|
/** STM32F2xx / STM32F401 PLL config */
|
||||||
#define stm32f2_4_192_pll_cfg { \
|
#define stm32f2_4_192_pll_cfg { \
|
||||||
.min_vco_input = 1000000U, \
|
.min_vco_input = 1000000U, \
|
||||||
@ -304,10 +320,30 @@ static const unsigned stm32_model[] = {
|
|||||||
.inc_q = 1, \
|
.inc_q = 1, \
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/** STM32MP1 PLL config */
|
||||||
|
#define stm32mp1_pll_cfg { \
|
||||||
|
.min_vco_input = 4000000U, \
|
||||||
|
.max_vco_input = 16000000U, \
|
||||||
|
.min_vco_output = 400000000U, \
|
||||||
|
.max_vco_output = 800000000U, \
|
||||||
|
.min_n = 25, \
|
||||||
|
.max_n = 100, \
|
||||||
|
.inc_n = 1, \
|
||||||
|
.min_m = 2, \
|
||||||
|
.max_m = 63, \
|
||||||
|
.inc_m = 1, \
|
||||||
|
.min_p = 2, \
|
||||||
|
.max_p = 127, \
|
||||||
|
.inc_p = 1, \
|
||||||
|
.min_q = 2, \
|
||||||
|
.max_q = 127, \
|
||||||
|
.inc_q = 1, \
|
||||||
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Clock config for supported cpu
|
* @brief Clock config for supported cpu
|
||||||
*/
|
*/
|
||||||
static const clk_cfg_t stm32_clk_cfg[] = {
|
static const clk_cfg_t stm32_f_clk_cfg[] = {
|
||||||
[STM32F030 ... STM32F098] = {
|
[STM32F030 ... STM32F098] = {
|
||||||
.family = STM32F0,
|
.family = STM32F0,
|
||||||
.max_coreclock = 48000000U,
|
.max_coreclock = 48000000U,
|
||||||
@ -595,6 +631,28 @@ static const clk_cfg_t stm32_clk_cfg[] = {
|
|||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clock config for supported cpu
|
||||||
|
*/
|
||||||
|
static const clk_cfg_t stm32_mp_clk_cfg[] = {
|
||||||
|
[STM32MP157] = {
|
||||||
|
.family = STM32MP1,
|
||||||
|
.max_coreclock = 209000000U,
|
||||||
|
.max_apb1 = 104500000U,
|
||||||
|
.max_apb2 = 104500000U,
|
||||||
|
.max_apb3 = 104500000U,
|
||||||
|
.hsi = 64000000U,
|
||||||
|
.pll = stm32mp1_pll_cfg,
|
||||||
|
.has_pll_i2s = false,
|
||||||
|
.has_pll_sai = false,
|
||||||
|
.has_pll_i2s_m = false,
|
||||||
|
.has_pll_sai_m = false,
|
||||||
|
.has_pll_i2s_alt_input = false,
|
||||||
|
.has_alt_48MHz = 0,
|
||||||
|
.need_48MHz = true,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|||||||
6
cpu/stm32/dist/irqs/gen_vectors.py
vendored
6
cpu/stm32/dist/irqs/gen_vectors.py
vendored
@ -54,6 +54,10 @@ def parse_cmsis(cpu_line):
|
|||||||
# STM32F030x4 is provided in the RIOT codebase in a different location
|
# STM32F030x4 is provided in the RIOT codebase in a different location
|
||||||
cpu_line_cmsis = os.path.join(
|
cpu_line_cmsis = os.path.join(
|
||||||
STM32_VENDOR_DIR, "{}.h".format(cpu_line.lower()))
|
STM32_VENDOR_DIR, "{}.h".format(cpu_line.lower()))
|
||||||
|
elif cpu_line.startswith("STM32MP1"):
|
||||||
|
# STM32MP157Cxx is provided in the RIOT codebase in a different location
|
||||||
|
cpu_line_cmsis = os.path.join(
|
||||||
|
STM32_VENDOR_DIR, "{}_cm4.h".format(cpu_line.lower()))
|
||||||
else:
|
else:
|
||||||
cpu_line_cmsis = STM32_CMSIS_FILE.format(
|
cpu_line_cmsis = STM32_CMSIS_FILE.format(
|
||||||
cpu_fam.lower(), cpu_line.lower())
|
cpu_fam.lower(), cpu_line.lower())
|
||||||
@ -70,7 +74,7 @@ def parse_cmsis(cpu_line):
|
|||||||
# skip line that contains non unicode characters
|
# skip line that contains non unicode characters
|
||||||
continue
|
continue
|
||||||
# start filling lines after interrupt Doxygen comment
|
# start filling lines after interrupt Doxygen comment
|
||||||
if line.startswith("typedef enum"):
|
if "typedef enum" in line:
|
||||||
use_line = True
|
use_line = True
|
||||||
|
|
||||||
# use a regexp to get the available IRQs
|
# use a regexp to get the available IRQs
|
||||||
|
|||||||
@ -38,6 +38,8 @@
|
|||||||
#elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32L5) || \
|
#elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32L5) || \
|
||||||
defined(CPU_FAM_STM32WB)
|
defined(CPU_FAM_STM32WB)
|
||||||
#include "l4l5wb/cfg_clock_default.h"
|
#include "l4l5wb/cfg_clock_default.h"
|
||||||
|
#elif defined(CPU_FAM_STM32MP1)
|
||||||
|
#include "mp1/cfg_clock_default.h"
|
||||||
#else
|
#else
|
||||||
#error "No clock configuration available"
|
#error "No clock configuration available"
|
||||||
#endif
|
#endif
|
||||||
|
|||||||
77
cpu/stm32/include/clk/mp1/cfg_clock_common.h
Normal file
77
cpu/stm32/include/clk/mp1/cfg_clock_common.h
Normal file
@ -0,0 +1,77 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (C) 2020 Savoir-faire Linux
|
||||||
|
*
|
||||||
|
* This file is subject to the terms and conditions of the GNU Lesser General
|
||||||
|
* Public License v2.1. See the file LICENSE in the top level directory for more
|
||||||
|
* details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @ingroup boards_common_stm32
|
||||||
|
* @{
|
||||||
|
*
|
||||||
|
* @file
|
||||||
|
* @brief Base STM32MP1 clock configuration
|
||||||
|
*
|
||||||
|
* @author Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef CLK_MP1_CFG_CLOCK_COMMON_H
|
||||||
|
#define CLK_MP1_CFG_CLOCK_COMMON_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @name Clock common configuration
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Select the desired system clock source between PLL, HSE or HSI */
|
||||||
|
#ifndef CONFIG_USE_CLOCK_PLL
|
||||||
|
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
|
||||||
|
#define CONFIG_USE_CLOCK_PLL 0
|
||||||
|
#else
|
||||||
|
#define CONFIG_USE_CLOCK_PLL 1 /* Use PLL by default */
|
||||||
|
#endif
|
||||||
|
#endif /* CONFIG_USE_CLOCK_PLL */
|
||||||
|
|
||||||
|
#ifndef CONFIG_USE_CLOCK_HSE
|
||||||
|
#define CONFIG_USE_CLOCK_HSE 0
|
||||||
|
#endif /* CONFIG_USE_CLOCK_HSE */
|
||||||
|
|
||||||
|
#ifndef CONFIG_USE_CLOCK_HSI
|
||||||
|
#define CONFIG_USE_CLOCK_HSI 0
|
||||||
|
#endif /* CONFIG_USE_CLOCK_HSI */
|
||||||
|
|
||||||
|
#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && \
|
||||||
|
(IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
|
||||||
|
#error "Cannot use PLL as clock source with other clock configurations"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) && \
|
||||||
|
(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
|
||||||
|
#error "Cannot use HSE as clock source with other clock configurations"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) && \
|
||||||
|
(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE))
|
||||||
|
#error "Cannot use HSI as clock source with other clock configurations"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef CONFIG_BOARD_HAS_HSE
|
||||||
|
#define CONFIG_BOARD_HAS_HSE 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef CLOCK_HSE
|
||||||
|
#define CLOCK_HSE MHZ(24)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define CLOCK_HSI MHZ(64)
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* CLK_MP1_CFG_CLOCK_COMMON_H */
|
||||||
|
/** @} */
|
||||||
38
cpu/stm32/include/clk/mp1/cfg_clock_default.h
Normal file
38
cpu/stm32/include/clk/mp1/cfg_clock_default.h
Normal file
@ -0,0 +1,38 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (C) 2020 Savoir-faire Linux
|
||||||
|
*
|
||||||
|
* This file is subject to the terms and conditions of the GNU Lesser General
|
||||||
|
* Public License v2.1. See the file LICENSE in the top level directory for more
|
||||||
|
* details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @ingroup cpu_stm32
|
||||||
|
* @{
|
||||||
|
*
|
||||||
|
* @file
|
||||||
|
* @brief Main header for STM32MP1 clock configuration
|
||||||
|
*
|
||||||
|
* @author Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef CLK_MP1_CFG_CLOCK_DEFAULT_H
|
||||||
|
#define CLK_MP1_CFG_CLOCK_DEFAULT_H
|
||||||
|
|
||||||
|
#if defined(CPU_LINE_STM32MP157Cxx)
|
||||||
|
#include "mp1/cfg_clock_default_208.h"
|
||||||
|
#else
|
||||||
|
#error "No clock configuration available for this family"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* CLK_MP1_CFG_CLOCK_DEFAULT_H */
|
||||||
|
/** @} */
|
||||||
85
cpu/stm32/include/clk/mp1/cfg_clock_default_208.h
Normal file
85
cpu/stm32/include/clk/mp1/cfg_clock_default_208.h
Normal file
@ -0,0 +1,85 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (C) 2020 Savoir-faire Linux
|
||||||
|
*
|
||||||
|
* This file is subject to the terms and conditions of the GNU Lesser General
|
||||||
|
* Public License v2.1. See the file LICENSE in the top level directory for more
|
||||||
|
* details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @ingroup boards_common_stm32
|
||||||
|
* @{
|
||||||
|
*
|
||||||
|
* @file
|
||||||
|
* @brief Default STM32MP1 clock configuration for 208MHz boards
|
||||||
|
*
|
||||||
|
* @author Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef CLK_MP1_CFG_CLOCK_DEFAULT_208_H
|
||||||
|
#define CLK_MP1_CFG_CLOCK_DEFAULT_208_H
|
||||||
|
|
||||||
|
#include "mp1/cfg_clock_common.h"
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @name Clock PLL settings (208MHz)
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* The following parameters configure a 208MHz system clock with HSE (24MHz)
|
||||||
|
* or HSI (16MHz) as PLL input clock */
|
||||||
|
#ifndef CONFIG_CLOCK_PLL_M
|
||||||
|
#define CONFIG_CLOCK_PLL_M (2)
|
||||||
|
#endif
|
||||||
|
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(24))
|
||||||
|
#ifndef CONFIG_CLOCK_PLL_N
|
||||||
|
#define CONFIG_CLOCK_PLL_N (52)
|
||||||
|
#endif
|
||||||
|
#else /* HSI */
|
||||||
|
#ifndef CONFIG_CLOCK_PLL_N
|
||||||
|
#define CONFIG_CLOCK_PLL_N (78)
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
#ifndef CONFIG_CLOCK_PLL_P
|
||||||
|
#define CONFIG_CLOCK_PLL_P (3)
|
||||||
|
#endif
|
||||||
|
#ifndef CONFIG_CLOCK_PLL_Q
|
||||||
|
#define CONFIG_CLOCK_PLL_Q (13)
|
||||||
|
#endif
|
||||||
|
#ifndef CONFIG_CLOCK_PLL_R
|
||||||
|
#define CONFIG_CLOCK_PLL_R (3)
|
||||||
|
#endif
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @name Clock bus settings (MCU, APB1, APB2 and APB3)
|
||||||
|
*/
|
||||||
|
#ifndef CONFIG_CLOCK_MCU_DIV
|
||||||
|
#define CONFIG_CLOCK_MCU_DIV (1) /* max 208MHz */
|
||||||
|
#endif
|
||||||
|
#ifndef CONFIG_CLOCK_APB1_DIV
|
||||||
|
#define CONFIG_CLOCK_APB1_DIV (2) /* max 104MHz */
|
||||||
|
#endif
|
||||||
|
#ifndef CONFIG_CLOCK_APB2_DIV
|
||||||
|
#define CONFIG_CLOCK_APB2_DIV (2) /* max 104MHz */
|
||||||
|
#endif
|
||||||
|
#ifndef CONFIG_CLOCK_APB3_DIV
|
||||||
|
#define CONFIG_CLOCK_APB3_DIV (2) /* max 104MHz */
|
||||||
|
#endif
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "mp1/cfg_clock_values.h"
|
||||||
|
|
||||||
|
#if CLOCK_CORECLOCK > MHZ(208)
|
||||||
|
#error "SYSCLK cannot exceed 208MHz"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* CLK_MP1_CFG_CLOCK_DEFAULT_208_H */
|
||||||
|
/** @} */
|
||||||
65
cpu/stm32/include/clk/mp1/cfg_clock_values.h
Normal file
65
cpu/stm32/include/clk/mp1/cfg_clock_values.h
Normal file
@ -0,0 +1,65 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (C) 2020 Savoir-faire Linux
|
||||||
|
*
|
||||||
|
* This file is subject to the terms and conditions of the GNU Lesser General
|
||||||
|
* Public License v2.1. See the file LICENSE in the top level directory for more
|
||||||
|
* details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @ingroup boards_common_stm32
|
||||||
|
* @{
|
||||||
|
*
|
||||||
|
* @file
|
||||||
|
* @brief STM32MP1 clock values definitions
|
||||||
|
*
|
||||||
|
* @author Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef CLK_MP1_CFG_CLOCK_VALUES_H
|
||||||
|
#define CLK_MP1_CFG_CLOCK_VALUES_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @name Clock values
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
|
||||||
|
#define CLOCK_PLL_SRC (CLOCK_HSE)
|
||||||
|
#else /* CLOCK_HSI */
|
||||||
|
#define CLOCK_PLL_SRC (CLOCK_HSI)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
|
||||||
|
#define CLOCK_CORECLOCK (CLOCK_HSI)
|
||||||
|
|
||||||
|
#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
|
||||||
|
#if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
|
||||||
|
#error "The board doesn't provide an HSE oscillator"
|
||||||
|
#endif
|
||||||
|
#define CLOCK_CORECLOCK (CLOCK_HSE)
|
||||||
|
|
||||||
|
#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
|
||||||
|
#define CLOCK_CORECLOCK (((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) \
|
||||||
|
* CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_P)
|
||||||
|
#endif /* CONFIG_USE_CLOCK_PLL */
|
||||||
|
|
||||||
|
#define CLOCK_PLLQ (((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) \
|
||||||
|
* CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_Q)
|
||||||
|
|
||||||
|
#define CLOCK_APB1 (CLOCK_CORECLOCK \
|
||||||
|
/ CONFIG_CLOCK_APB1_DIV)
|
||||||
|
#define CLOCK_APB2 (CLOCK_CORECLOCK \
|
||||||
|
/ CONFIG_CLOCK_APB2_DIV)
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* CLK_MP1_CFG_CLOCK_VALUES_H */
|
||||||
|
/** @} */
|
||||||
@ -25,6 +25,8 @@
|
|||||||
|
|
||||||
#if defined(CPU_LINE_STM32F030x4)
|
#if defined(CPU_LINE_STM32F030x4)
|
||||||
#include "vendor/stm32f030x4.h"
|
#include "vendor/stm32f030x4.h"
|
||||||
|
#elif defined(CPU_LINE_STM32MP157Cxx)
|
||||||
|
#include "vendor/stm32mp157cxx_cm4.h"
|
||||||
#elif CPU_FAM_STM32F0
|
#elif CPU_FAM_STM32F0
|
||||||
#include "stm32f0xx.h"
|
#include "stm32f0xx.h"
|
||||||
#include "irqs/f0/irqs.h"
|
#include "irqs/f0/irqs.h"
|
||||||
@ -77,11 +79,16 @@ extern "C" {
|
|||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#define CPU_DEFAULT_IRQ_PRIO (1U)
|
#define CPU_DEFAULT_IRQ_PRIO (1U)
|
||||||
|
/* STM32MP1 family has no flah */
|
||||||
|
#if !defined(CPU_FAM_STM32MP1)
|
||||||
#define CPU_FLASH_BASE FLASH_BASE
|
#define CPU_FLASH_BASE FLASH_BASE
|
||||||
|
#endif
|
||||||
|
|
||||||
/* CPU_IRQ_NUMOF cannot be determined automatically from cmsis header */
|
/* CPU_IRQ_NUMOF cannot be determined automatically from cmsis header */
|
||||||
#if defined(CPU_LINE_STM32F030x4)
|
#if defined(CPU_LINE_STM32F030x4)
|
||||||
#define CPU_IRQ_NUMOF (28U)
|
#define CPU_IRQ_NUMOF (28U)
|
||||||
|
#elif defined(CPU_MODEL_STM32MP157CAC)
|
||||||
|
#define CPU_IRQ_NUMOF (150U)
|
||||||
#endif
|
#endif
|
||||||
/** @} */
|
/** @} */
|
||||||
|
|
||||||
|
|||||||
@ -67,7 +67,8 @@ extern "C" {
|
|||||||
#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
|
#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
|
||||||
defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L4) || \
|
defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L4) || \
|
||||||
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
|
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
|
||||||
defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5)
|
defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
|
||||||
|
defined(CPU_FAM_STM32MP1)
|
||||||
#define CLOCK_LSI (32000U)
|
#define CLOCK_LSI (32000U)
|
||||||
#else
|
#else
|
||||||
#error "error: LSI clock speed not defined for your target CPU"
|
#error "error: LSI clock speed not defined for your target CPU"
|
||||||
@ -190,10 +191,14 @@ typedef enum {
|
|||||||
AHB1, /**< AHB1 bus */
|
AHB1, /**< AHB1 bus */
|
||||||
AHB2, /**< AHB2 bus */
|
AHB2, /**< AHB2 bus */
|
||||||
AHB3, /**< AHB3 bus */
|
AHB3, /**< AHB3 bus */
|
||||||
|
#elif defined(CPU_FAM_STM32MP1)
|
||||||
|
AHB1, /**< AHB1 bus */
|
||||||
|
AHB2, /**< AHB2 bus */
|
||||||
|
AHB3, /**< AHB3 bus */
|
||||||
#else
|
#else
|
||||||
#warning "unsupported stm32XX family"
|
#warning "unsupported stm32XX family"
|
||||||
#endif
|
#endif
|
||||||
#if defined(CPU_FAM_STM32WB)
|
#if defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32MP1)
|
||||||
AHB4, /**< AHB4 bus */
|
AHB4, /**< AHB4 bus */
|
||||||
#endif
|
#endif
|
||||||
} bus_t;
|
} bus_t;
|
||||||
@ -216,7 +221,11 @@ typedef uint32_t gpio_t;
|
|||||||
/**
|
/**
|
||||||
* @brief Define a CPU specific GPIO pin generator macro
|
* @brief Define a CPU specific GPIO pin generator macro
|
||||||
*/
|
*/
|
||||||
|
#if defined(CPU_FAM_STM32MP1)
|
||||||
|
#define GPIO_PIN(x, y) ((GPIOA_BASE + (x << 12)) | y)
|
||||||
|
#else
|
||||||
#define GPIO_PIN(x, y) ((GPIOA_BASE + (x << 10)) | y)
|
#define GPIO_PIN(x, y) ((GPIOA_BASE + (x << 10)) | y)
|
||||||
|
#endif
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Available GPIO ports
|
* @brief Available GPIO ports
|
||||||
@ -283,7 +292,8 @@ enum {
|
|||||||
#define PERIPH_I2C_NEED_WRITE_REG
|
#define PERIPH_I2C_NEED_WRITE_REG
|
||||||
#define PERIPH_I2C_NEED_READ_REGS
|
#define PERIPH_I2C_NEED_READ_REGS
|
||||||
#if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || \
|
#if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || \
|
||||||
defined(CPU_FAM_STM32L1) || defined(CPU_FAM_STM32F4)
|
defined(CPU_FAM_STM32L1) || defined(CPU_FAM_STM32F4) || \
|
||||||
|
defined(CPU_FAM_STM32MP1)
|
||||||
#define PERIPH_I2C_NEED_WRITE_REGS
|
#define PERIPH_I2C_NEED_WRITE_REGS
|
||||||
#endif
|
#endif
|
||||||
/** @} */
|
/** @} */
|
||||||
@ -674,7 +684,7 @@ typedef struct {
|
|||||||
#endif
|
#endif
|
||||||
#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L4) || \
|
#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L4) || \
|
||||||
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
|
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
|
||||||
defined(CPU_FAM_STM32L5)
|
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32MP1)
|
||||||
uart_type_t type; /**< hardware module type (USART or LPUART) */
|
uart_type_t type; /**< hardware module type (USART or LPUART) */
|
||||||
uint32_t clk_src; /**< clock source used for UART */
|
uint32_t clk_src; /**< clock source used for UART */
|
||||||
#endif
|
#endif
|
||||||
@ -717,7 +727,8 @@ typedef struct {
|
|||||||
#define HAVE_I2C_SPEED_T
|
#define HAVE_I2C_SPEED_T
|
||||||
typedef enum {
|
typedef enum {
|
||||||
#if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || \
|
#if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || \
|
||||||
defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32L1)
|
defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32L1) || \
|
||||||
|
defined(CPU_FAM_STM32MP1)
|
||||||
I2C_SPEED_LOW, /**< low speed mode: ~10kit/s */
|
I2C_SPEED_LOW, /**< low speed mode: ~10kit/s */
|
||||||
#endif
|
#endif
|
||||||
I2C_SPEED_NORMAL, /**< normal mode: ~100kbit/s */
|
I2C_SPEED_NORMAL, /**< normal mode: ~100kbit/s */
|
||||||
@ -751,7 +762,8 @@ typedef struct {
|
|||||||
uint32_t rcc_sw_mask; /**< bit to switch I2C clock */
|
uint32_t rcc_sw_mask; /**< bit to switch I2C clock */
|
||||||
#endif
|
#endif
|
||||||
#if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || \
|
#if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || \
|
||||||
defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32L1)
|
defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32L1) || \
|
||||||
|
defined(CPU_FAM_STM32MP1)
|
||||||
uint32_t clk; /**< bus frequency as defined in board config */
|
uint32_t clk; /**< bus frequency as defined in board config */
|
||||||
#endif
|
#endif
|
||||||
uint8_t irqn; /**< I2C event interrupt number */
|
uint8_t irqn; /**< I2C event interrupt number */
|
||||||
|
|||||||
32050
cpu/stm32/include/vendor/stm32mp157cxx_cm4.h
vendored
Normal file
32050
cpu/stm32/include/vendor/stm32mp157cxx_cm4.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
106
cpu/stm32/include/vendor/system_stm32mp1xx.h
vendored
Normal file
106
cpu/stm32/include/vendor/system_stm32mp1xx.h
vendored
Normal file
@ -0,0 +1,106 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file system_stm32mp1xx.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @brief CMSIS Cortex-Mx Device System Source File for STM32MP1xx devices.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
|
*
|
||||||
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
|
* the "License"; You may not use this file except in compliance with the
|
||||||
|
* License. You may obtain a copy of the License at:
|
||||||
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup CMSIS
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup stm32mp1xx_system
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Define to prevent recursive inclusion
|
||||||
|
*/
|
||||||
|
#ifndef __SYSTEM_STM32MP1XX_H
|
||||||
|
#define __SYSTEM_STM32MP1XX_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup STM32MP1xx_System_Includes
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup STM32MP1xx_System_Exported_types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* This variable is updated in three ways:
|
||||||
|
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||||
|
2) by calling HAL API function HAL_RCC_GetSysClockFreq()
|
||||||
|
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||||
|
Note: If you use this function to configure the system clock; then there
|
||||||
|
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||||
|
variable is updated automatically.
|
||||||
|
*/
|
||||||
|
extern uint32_t SystemCoreClock; /*!< System Core1 Clock Frequency */
|
||||||
|
extern uint32_t SystemCore1Clock; /*!< System Core1 Clock Frequency */
|
||||||
|
extern uint32_t SystemCore2Clock; /*!< System Core2 Clock Frequency */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32MP1xx_System_Exported_Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32MP1xx_System_Exported_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32MP1xx_System_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
extern void SystemInit(void);
|
||||||
|
extern void SystemCoreClockUpdate(void);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /*__SYSTEM_STM32MP1XX_H */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -15,6 +15,9 @@ config CPU_FAM_F0
|
|||||||
select HAS_CPU_STM32F0
|
select HAS_CPU_STM32F0
|
||||||
select HAS_PERIPH_FLASHPAGE
|
select HAS_PERIPH_FLASHPAGE
|
||||||
select HAS_PERIPH_FLASHPAGE_PAGEWISE
|
select HAS_PERIPH_FLASHPAGE_PAGEWISE
|
||||||
|
select HAS_PERIPH_FLASHPAGE_RAW
|
||||||
|
select HAS_PERIPH_WDT
|
||||||
|
select HAS_BOOTLOADER_STM32
|
||||||
|
|
||||||
config HAS_CPU_STM32F0
|
config HAS_CPU_STM32F0
|
||||||
bool
|
bool
|
||||||
|
|||||||
@ -12,6 +12,9 @@ config CPU_FAM_F1
|
|||||||
select HAS_CPU_STM32F1
|
select HAS_CPU_STM32F1
|
||||||
select HAS_PERIPH_FLASHPAGE
|
select HAS_PERIPH_FLASHPAGE
|
||||||
select HAS_PERIPH_FLASHPAGE_PAGEWISE
|
select HAS_PERIPH_FLASHPAGE_PAGEWISE
|
||||||
|
select HAS_PERIPH_FLASHPAGE_RAW
|
||||||
|
select HAS_PERIPH_WDT
|
||||||
|
select HAS_BOOTLOADER_STM32
|
||||||
|
|
||||||
config CPU_FAM
|
config CPU_FAM
|
||||||
default "f1" if CPU_FAM_F1
|
default "f1" if CPU_FAM_F1
|
||||||
|
|||||||
@ -12,6 +12,8 @@ config CPU_FAM_F2
|
|||||||
select HAS_CPU_STM32F2
|
select HAS_CPU_STM32F2
|
||||||
select HAS_CORTEXM_MPU
|
select HAS_CORTEXM_MPU
|
||||||
select HAS_PERIPH_HWRNG
|
select HAS_PERIPH_HWRNG
|
||||||
|
select HAS_PERIPH_WDT
|
||||||
|
select HAS_BOOTLOADER_STM32
|
||||||
|
|
||||||
config CPU_FAM
|
config CPU_FAM
|
||||||
default "f2" if CPU_FAM_F2
|
default "f2" if CPU_FAM_F2
|
||||||
|
|||||||
@ -12,6 +12,9 @@ config CPU_FAM_F3
|
|||||||
select HAS_CPU_STM32F3
|
select HAS_CPU_STM32F3
|
||||||
select HAS_PERIPH_FLASHPAGE
|
select HAS_PERIPH_FLASHPAGE
|
||||||
select HAS_PERIPH_FLASHPAGE_PAGEWISE
|
select HAS_PERIPH_FLASHPAGE_PAGEWISE
|
||||||
|
select HAS_PERIPH_FLASHPAGE_RAW
|
||||||
|
select HAS_PERIPH_WDT
|
||||||
|
select HAS_BOOTLOADER_STM32
|
||||||
|
|
||||||
config CPU_FAM
|
config CPU_FAM
|
||||||
default "f3" if CPU_FAM_F3
|
default "f3" if CPU_FAM_F3
|
||||||
|
|||||||
@ -11,6 +11,8 @@ config CPU_FAM_F4
|
|||||||
select CPU_CORE_CORTEX_M4F
|
select CPU_CORE_CORTEX_M4F
|
||||||
select HAS_CPU_STM32F4
|
select HAS_CPU_STM32F4
|
||||||
select HAS_CORTEXM_MPU
|
select HAS_CORTEXM_MPU
|
||||||
|
select HAS_PERIPH_WDT
|
||||||
|
select HAS_BOOTLOADER_STM32
|
||||||
|
|
||||||
config CPU_FAM
|
config CPU_FAM
|
||||||
default "f4" if CPU_FAM_F4
|
default "f4" if CPU_FAM_F4
|
||||||
|
|||||||
@ -12,6 +12,8 @@ config CPU_FAM_F7
|
|||||||
select HAS_CPU_STM32F7
|
select HAS_CPU_STM32F7
|
||||||
select HAS_CORTEXM_MPU
|
select HAS_CORTEXM_MPU
|
||||||
select HAS_PERIPH_HWRNG
|
select HAS_PERIPH_HWRNG
|
||||||
|
select HAS_PERIPH_WDT
|
||||||
|
select HAS_BOOTLOADER_STM32
|
||||||
|
|
||||||
config CPU_FAM
|
config CPU_FAM
|
||||||
default "f7" if CPU_FAM_F7
|
default "f7" if CPU_FAM_F7
|
||||||
|
|||||||
@ -12,6 +12,9 @@ config CPU_FAM_G0
|
|||||||
select HAS_CPU_STM32G0
|
select HAS_CPU_STM32G0
|
||||||
select HAS_PERIPH_FLASHPAGE
|
select HAS_PERIPH_FLASHPAGE
|
||||||
select HAS_PERIPH_FLASHPAGE_PAGEWISE
|
select HAS_PERIPH_FLASHPAGE_PAGEWISE
|
||||||
|
select HAS_PERIPH_FLASHPAGE_RAW
|
||||||
|
select HAS_PERIPH_WDT
|
||||||
|
select HAS_BOOTLOADER_STM32
|
||||||
|
|
||||||
config CPU_FAM
|
config CPU_FAM
|
||||||
default "g0" if CPU_FAM_G0
|
default "g0" if CPU_FAM_G0
|
||||||
|
|||||||
@ -14,6 +14,8 @@ config CPU_FAM_G4
|
|||||||
select HAS_PERIPH_FLASHPAGE
|
select HAS_PERIPH_FLASHPAGE
|
||||||
select HAS_PERIPH_FLASHPAGE_PAGEWISE
|
select HAS_PERIPH_FLASHPAGE_PAGEWISE
|
||||||
select HAS_PERIPH_HWRNG
|
select HAS_PERIPH_HWRNG
|
||||||
|
select HAS_PERIPH_WDT
|
||||||
|
select HAS_BOOTLOADER_STM32
|
||||||
|
|
||||||
config CPU_FAM
|
config CPU_FAM
|
||||||
default "g4" if CPU_FAM_G4
|
default "g4" if CPU_FAM_G4
|
||||||
|
|||||||
@ -13,6 +13,8 @@ config CPU_FAM_L0
|
|||||||
select HAS_PERIPH_FLASHPAGE
|
select HAS_PERIPH_FLASHPAGE
|
||||||
select HAS_PERIPH_FLASHPAGE_PAGEWISE
|
select HAS_PERIPH_FLASHPAGE_PAGEWISE
|
||||||
select HAS_PERIPH_EEPROM
|
select HAS_PERIPH_EEPROM
|
||||||
|
select HAS_PERIPH_WDT
|
||||||
|
select HAS_BOOTLOADER_STM32
|
||||||
|
|
||||||
config CPU_FAM
|
config CPU_FAM
|
||||||
default "l0" if CPU_FAM_L0
|
default "l0" if CPU_FAM_L0
|
||||||
|
|||||||
@ -14,6 +14,8 @@ config CPU_FAM_L1
|
|||||||
select HAS_PERIPH_FLASHPAGE
|
select HAS_PERIPH_FLASHPAGE
|
||||||
select HAS_PERIPH_FLASHPAGE_PAGEWISE
|
select HAS_PERIPH_FLASHPAGE_PAGEWISE
|
||||||
select HAS_PERIPH_EEPROM
|
select HAS_PERIPH_EEPROM
|
||||||
|
select HAS_PERIPH_WDT
|
||||||
|
select HAS_BOOTLOADER_STM32
|
||||||
|
|
||||||
config CPU_FAM
|
config CPU_FAM
|
||||||
default "l1" if CPU_FAM_L1
|
default "l1" if CPU_FAM_L1
|
||||||
|
|||||||
@ -14,6 +14,8 @@ config CPU_FAM_L4
|
|||||||
select HAS_PERIPH_FLASHPAGE
|
select HAS_PERIPH_FLASHPAGE
|
||||||
select HAS_PERIPH_FLASHPAGE_PAGEWISE
|
select HAS_PERIPH_FLASHPAGE_PAGEWISE
|
||||||
select HAS_PERIPH_HWRNG
|
select HAS_PERIPH_HWRNG
|
||||||
|
select HAS_PERIPH_WDT
|
||||||
|
select HAS_BOOTLOADER_STM32
|
||||||
|
|
||||||
config CPU_FAM
|
config CPU_FAM
|
||||||
default "l4" if CPU_FAM_L4
|
default "l4" if CPU_FAM_L4
|
||||||
|
|||||||
@ -13,6 +13,8 @@ config CPU_FAM_L5
|
|||||||
select HAS_PERIPH_FLASHPAGE
|
select HAS_PERIPH_FLASHPAGE
|
||||||
select HAS_PERIPH_FLASHPAGE_PAGEWISE
|
select HAS_PERIPH_FLASHPAGE_PAGEWISE
|
||||||
select HAS_PERIPH_HWRNG
|
select HAS_PERIPH_HWRNG
|
||||||
|
select HAS_PERIPH_WDT
|
||||||
|
select HAS_BOOTLOADER_STM32
|
||||||
|
|
||||||
config CPU_FAM
|
config CPU_FAM
|
||||||
default "l5" if CPU_FAM_L5
|
default "l5" if CPU_FAM_L5
|
||||||
|
|||||||
20
cpu/stm32/kconfigs/mp1/Kconfig
Normal file
20
cpu/stm32/kconfigs/mp1/Kconfig
Normal file
@ -0,0 +1,20 @@
|
|||||||
|
# Copyright (C) 2020 Savoir-faire Linux
|
||||||
|
#
|
||||||
|
# This file is subject to the terms and conditions of the GNU Lesser General
|
||||||
|
# Public License v2.1. See the file LICENSE in the top level directory for more
|
||||||
|
# details.
|
||||||
|
|
||||||
|
config CPU_FAM_MP1
|
||||||
|
bool
|
||||||
|
select CPU_STM32
|
||||||
|
select CPU_CORE_CORTEX_M4F
|
||||||
|
select HAS_CORTEXM_MPU
|
||||||
|
select HAS_CPU_STM32MP1
|
||||||
|
|
||||||
|
config CPU_FAM
|
||||||
|
default "mp1" if CPU_FAM_MP1
|
||||||
|
|
||||||
|
config HAS_CPU_STM32MP1
|
||||||
|
bool
|
||||||
|
help
|
||||||
|
Indicates that the cpu being used belongs to the 'stm32mp1' family.
|
||||||
10
cpu/stm32/kconfigs/mp1/Kconfig.lines
Normal file
10
cpu/stm32/kconfigs/mp1/Kconfig.lines
Normal file
@ -0,0 +1,10 @@
|
|||||||
|
# Copyright (C) 2020 Savoir-faire Linux
|
||||||
|
#
|
||||||
|
# This file is subject to the terms and conditions of the GNU Lesser General
|
||||||
|
# Public License v2.1. See the file LICENSE in the top level directory for more
|
||||||
|
# details.
|
||||||
|
|
||||||
|
# CPU lines
|
||||||
|
config CPU_LINE_STM32MP157CXX
|
||||||
|
bool
|
||||||
|
select CPU_FAM_MP1
|
||||||
14
cpu/stm32/kconfigs/mp1/Kconfig.models
Normal file
14
cpu/stm32/kconfigs/mp1/Kconfig.models
Normal file
@ -0,0 +1,14 @@
|
|||||||
|
# Copyright (C) 2020 Savoir-faire Linux
|
||||||
|
#
|
||||||
|
# This file is subject to the terms and conditions of the GNU Lesser General
|
||||||
|
# Public License v2.1. See the file LICENSE in the top level directory for more
|
||||||
|
# details.
|
||||||
|
|
||||||
|
# CPU models
|
||||||
|
config CPU_MODEL_STM32MP157CAC
|
||||||
|
bool
|
||||||
|
select CPU_LINE_STM32MP157CXX
|
||||||
|
|
||||||
|
# Configure CPU model
|
||||||
|
config CPU_MODEL
|
||||||
|
default "stm32mp157cac" if CPU_MODEL_STM32MP157CAC
|
||||||
@ -13,6 +13,8 @@ config CPU_FAM_WB
|
|||||||
select HAS_PERIPH_FLASHPAGE
|
select HAS_PERIPH_FLASHPAGE
|
||||||
select HAS_PERIPH_FLASHPAGE_PAGEWISE
|
select HAS_PERIPH_FLASHPAGE_PAGEWISE
|
||||||
select HAS_PERIPH_HWRNG
|
select HAS_PERIPH_HWRNG
|
||||||
|
select HAS_PERIPH_WDT
|
||||||
|
select HAS_BOOTLOADER_STM32
|
||||||
|
|
||||||
config CPU_FAM
|
config CPU_FAM
|
||||||
default "wb" if CPU_FAM_WB
|
default "wb" if CPU_FAM_WB
|
||||||
|
|||||||
@ -26,7 +26,6 @@
|
|||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
|
||||||
#include "cpu.h"
|
#include "cpu.h"
|
||||||
#include "bitarithm.h"
|
#include "bitarithm.h"
|
||||||
#include "periph/gpio.h"
|
#include "periph/gpio.h"
|
||||||
@ -51,6 +50,11 @@ static gpio_isr_ctx_t isr_ctx[EXTI_NUMOF];
|
|||||||
#define EXTI_REG_FTSR (EXTI->FTSR1)
|
#define EXTI_REG_FTSR (EXTI->FTSR1)
|
||||||
#define EXTI_REG_PR (EXTI->PR1)
|
#define EXTI_REG_PR (EXTI->PR1)
|
||||||
#define EXTI_REG_IMR (EXTI->IMR1)
|
#define EXTI_REG_IMR (EXTI->IMR1)
|
||||||
|
#elif defined(CPU_FAM_STM32MP1)
|
||||||
|
#define EXTI_REG_RTSR (EXTI->RTSR1)
|
||||||
|
#define EXTI_REG_FTSR (EXTI->FTSR1)
|
||||||
|
#define EXTI_REG_PR (EXTI->PR1)
|
||||||
|
#define EXTI_REG_IMR (EXTI_C2->IMR1)
|
||||||
#else
|
#else
|
||||||
#define EXTI_REG_RTSR (EXTI->RTSR)
|
#define EXTI_REG_RTSR (EXTI->RTSR)
|
||||||
#define EXTI_REG_FTSR (EXTI->FTSR)
|
#define EXTI_REG_FTSR (EXTI->FTSR)
|
||||||
@ -74,7 +78,11 @@ static inline GPIO_TypeDef *_port(gpio_t pin)
|
|||||||
*/
|
*/
|
||||||
static inline int _port_num(gpio_t pin)
|
static inline int _port_num(gpio_t pin)
|
||||||
{
|
{
|
||||||
|
#if defined(CPU_FAM_STM32MP1)
|
||||||
|
return (((pin - GPIOA_BASE) >> 12) & 0x0f);
|
||||||
|
#else
|
||||||
return ((pin >> 10) & 0x0f);
|
return ((pin >> 10) & 0x0f);
|
||||||
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
@ -102,6 +110,8 @@ static inline void port_init_clock(GPIO_TypeDef *port, gpio_t pin)
|
|||||||
PWR->CR2 |= PWR_CR2_IOSV;
|
PWR->CR2 |= PWR_CR2_IOSV;
|
||||||
}
|
}
|
||||||
#endif /* PWR_CR2_IOSV */
|
#endif /* PWR_CR2_IOSV */
|
||||||
|
#elif defined(CPU_FAM_STM32MP1)
|
||||||
|
periph_clk_en(AHB4, (RCC_MC_AHB4ENSETR_GPIOAEN << _port_num(pin)));
|
||||||
#else
|
#else
|
||||||
periph_clk_en(AHB1, (RCC_AHB1ENR_GPIOAEN << _port_num(pin)));
|
periph_clk_en(AHB1, (RCC_AHB1ENR_GPIOAEN << _port_num(pin)));
|
||||||
#endif
|
#endif
|
||||||
@ -161,6 +171,8 @@ void gpio_init_analog(gpio_t pin)
|
|||||||
#elif defined (CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
|
#elif defined (CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
|
||||||
defined (CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5)
|
defined (CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5)
|
||||||
periph_clk_en(AHB2, (RCC_AHB2ENR_GPIOAEN << _port_num(pin)));
|
periph_clk_en(AHB2, (RCC_AHB2ENR_GPIOAEN << _port_num(pin)));
|
||||||
|
#elif defined(CPU_FAM_STM32MP1)
|
||||||
|
periph_clk_en(AHB4, (RCC_MC_AHB4ENSETR_GPIOAEN << _port_num(pin)));
|
||||||
#else
|
#else
|
||||||
periph_clk_en(AHB1, (RCC_AHB1ENR_GPIOAEN << _port_num(pin)));
|
periph_clk_en(AHB1, (RCC_AHB1ENR_GPIOAEN << _port_num(pin)));
|
||||||
#endif
|
#endif
|
||||||
@ -223,7 +235,7 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
|
|||||||
isr_ctx[pin_num].arg = arg;
|
isr_ctx[pin_num].arg = arg;
|
||||||
|
|
||||||
/* enable clock of the SYSCFG module for EXTI configuration */
|
/* enable clock of the SYSCFG module for EXTI configuration */
|
||||||
#ifndef CPU_FAM_STM32WB
|
#if !defined(CPU_FAM_STM32WB) && !defined(CPU_FAM_STM32MP1)
|
||||||
#ifdef CPU_FAM_STM32F0
|
#ifdef CPU_FAM_STM32F0
|
||||||
periph_clk_en(APB2, RCC_APB2ENR_SYSCFGCOMPEN);
|
periph_clk_en(APB2, RCC_APB2ENR_SYSCFGCOMPEN);
|
||||||
#elif defined(CPU_FAM_STM32G0)
|
#elif defined(CPU_FAM_STM32G0)
|
||||||
@ -250,6 +262,31 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
|
|||||||
else {
|
else {
|
||||||
NVIC_EnableIRQ(EXTI4_15_IRQn);
|
NVIC_EnableIRQ(EXTI4_15_IRQn);
|
||||||
}
|
}
|
||||||
|
#elif defined(CPU_FAM_STM32MP1)
|
||||||
|
if (pin_num < 5) {
|
||||||
|
NVIC_EnableIRQ(EXTI0_IRQn + pin_num);
|
||||||
|
}
|
||||||
|
else if (pin_num < 6) {
|
||||||
|
NVIC_EnableIRQ(EXTI5_IRQn);
|
||||||
|
}
|
||||||
|
else if (pin_num < 10) {
|
||||||
|
NVIC_EnableIRQ(EXTI6_IRQn + pin_num - 6);
|
||||||
|
}
|
||||||
|
else if (pin_num < 11) {
|
||||||
|
NVIC_EnableIRQ(EXTI10_IRQn);
|
||||||
|
}
|
||||||
|
else if (pin_num < 12) {
|
||||||
|
NVIC_EnableIRQ(EXTI11_IRQn);
|
||||||
|
}
|
||||||
|
else if (pin_num < 14) {
|
||||||
|
NVIC_EnableIRQ(EXTI12_IRQn + pin_num - 12);
|
||||||
|
}
|
||||||
|
else if (pin_num < 15) {
|
||||||
|
NVIC_EnableIRQ(EXTI14_IRQn);
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
NVIC_EnableIRQ(EXTI15_IRQn);
|
||||||
|
}
|
||||||
#else
|
#else
|
||||||
if (pin_num < 5) {
|
if (pin_num < 5) {
|
||||||
NVIC_EnableIRQ(EXTI0_IRQn + pin_num);
|
NVIC_EnableIRQ(EXTI0_IRQn + pin_num);
|
||||||
@ -271,13 +308,22 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
|
|||||||
/* enable specific pin as exti sources */
|
/* enable specific pin as exti sources */
|
||||||
EXTI->EXTICR[pin_num >> 2] &= ~(0xf << ((pin_num & 0x03) * 8));
|
EXTI->EXTICR[pin_num >> 2] &= ~(0xf << ((pin_num & 0x03) * 8));
|
||||||
EXTI->EXTICR[pin_num >> 2] |= (port_num << ((pin_num & 0x03) * 8));
|
EXTI->EXTICR[pin_num >> 2] |= (port_num << ((pin_num & 0x03) * 8));
|
||||||
/* clear any pending requests */
|
#elif defined(CPU_FAM_STM32MP1)
|
||||||
EXTI->RPR1 = (1 << pin_num);
|
/* enable specific pin as exti sources */
|
||||||
EXTI->FPR1 = (1 << pin_num);
|
EXTI->EXTICR[pin_num >> 2] &= ~(0xf << ((pin_num & 0x03) * 4));
|
||||||
|
EXTI->EXTICR[pin_num >> 2] |= (port_num << ((pin_num & 0x03) * 4));
|
||||||
#else
|
#else
|
||||||
/* enable specific pin as exti sources */
|
/* enable specific pin as exti sources */
|
||||||
SYSCFG->EXTICR[pin_num >> 2] &= ~(0xf << ((pin_num & 0x03) * 4));
|
SYSCFG->EXTICR[pin_num >> 2] &= ~(0xf << ((pin_num & 0x03) * 4));
|
||||||
SYSCFG->EXTICR[pin_num >> 2] |= (port_num << ((pin_num & 0x03) * 4));
|
SYSCFG->EXTICR[pin_num >> 2] |= (port_num << ((pin_num & 0x03) * 4));
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
|
||||||
|
defined(CPU_FAM_STM32MP1)
|
||||||
|
/* clear any pending requests */
|
||||||
|
EXTI->RPR1 = (1 << pin_num);
|
||||||
|
EXTI->FPR1 = (1 << pin_num);
|
||||||
|
#else
|
||||||
/* clear any pending requests */
|
/* clear any pending requests */
|
||||||
EXTI_REG_PR = (1 << pin_num);
|
EXTI_REG_PR = (1 << pin_num);
|
||||||
#endif
|
#endif
|
||||||
@ -289,7 +335,8 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
|
|||||||
|
|
||||||
void isr_exti(void)
|
void isr_exti(void)
|
||||||
{
|
{
|
||||||
#if defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5)
|
#if defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
|
||||||
|
defined(CPU_FAM_STM32MP1)
|
||||||
/* only generate interrupts against lines which have their IMR set */
|
/* only generate interrupts against lines which have their IMR set */
|
||||||
uint32_t pending_rising_isr = (EXTI->RPR1 & EXTI_REG_IMR);
|
uint32_t pending_rising_isr = (EXTI->RPR1 & EXTI_REG_IMR);
|
||||||
uint32_t pending_falling_isr = (EXTI->FPR1 & EXTI_REG_IMR);
|
uint32_t pending_falling_isr = (EXTI->FPR1 & EXTI_REG_IMR);
|
||||||
|
|||||||
@ -53,7 +53,8 @@
|
|||||||
#define PM_STOP_CONFIG (PWR_CR1_LPMS_0)
|
#define PM_STOP_CONFIG (PWR_CR1_LPMS_0)
|
||||||
#elif defined(CPU_FAM_STM32F7)
|
#elif defined(CPU_FAM_STM32F7)
|
||||||
#define PM_STOP_CONFIG (PWR_CR1_LPDS | PWR_CR1_FPDS | PWR_CR1_LPUDS)
|
#define PM_STOP_CONFIG (PWR_CR1_LPDS | PWR_CR1_FPDS | PWR_CR1_LPUDS)
|
||||||
#elif defined(CPU_FAM_STM32WB)
|
#elif defined(CPU_FAM_STM32MP1)
|
||||||
|
#define PM_STOP_CONFIG (0)
|
||||||
#else
|
#else
|
||||||
#define PM_STOP_CONFIG (PWR_CR_LPDS | PWR_CR_FPDS)
|
#define PM_STOP_CONFIG (PWR_CR_LPDS | PWR_CR_FPDS)
|
||||||
#endif
|
#endif
|
||||||
@ -74,6 +75,8 @@
|
|||||||
#define PM_STANDBY_CONFIG (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1)
|
#define PM_STANDBY_CONFIG (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1)
|
||||||
#elif defined(CPU_FAM_STM32F7)
|
#elif defined(CPU_FAM_STM32F7)
|
||||||
#define PM_STANDBY_CONFIG (PWR_CR1_PDDS | PWR_CR1_CSBF)
|
#define PM_STANDBY_CONFIG (PWR_CR1_PDDS | PWR_CR1_CSBF)
|
||||||
|
#elif defined(CPU_FAM_STM32MP1)
|
||||||
|
#define PM_STANDBY_CONFIG (0)
|
||||||
#else
|
#else
|
||||||
#define PM_STANDBY_CONFIG (PWR_CR_PDDS | PWR_CR_CWUF | PWR_CR_CSBF)
|
#define PM_STANDBY_CONFIG (PWR_CR_PDDS | PWR_CR_CWUF | PWR_CR_CSBF)
|
||||||
#endif
|
#endif
|
||||||
@ -92,6 +95,9 @@
|
|||||||
#elif defined(CPU_FAM_STM32F7)
|
#elif defined(CPU_FAM_STM32F7)
|
||||||
#define PWR_CR_REG PWR->CR1
|
#define PWR_CR_REG PWR->CR1
|
||||||
#define PWR_WUP_REG PWR->CSR2
|
#define PWR_WUP_REG PWR->CSR2
|
||||||
|
#elif defined(CPU_FAM_STM32MP1)
|
||||||
|
#define PWR_CR_REG PWR->CR1
|
||||||
|
#define PWR_WUP_REG PWR->MCUWKUPENR
|
||||||
#else
|
#else
|
||||||
#define PWR_CR_REG PWR->CR
|
#define PWR_CR_REG PWR->CR
|
||||||
#define PWR_WUP_REG PWR->CSR
|
#define PWR_WUP_REG PWR->CSR
|
||||||
@ -102,7 +108,7 @@ void pm_set(unsigned mode)
|
|||||||
int deep;
|
int deep;
|
||||||
|
|
||||||
switch (mode) {
|
switch (mode) {
|
||||||
#ifdef STM32_PM_STANDBY
|
#if !defined(CPU_FAM_STM32MP1)
|
||||||
case STM32_PM_STANDBY:
|
case STM32_PM_STANDBY:
|
||||||
PWR_CR_REG &= ~(PM_STOP_CONFIG | PM_STANDBY_CONFIG);
|
PWR_CR_REG &= ~(PM_STOP_CONFIG | PM_STANDBY_CONFIG);
|
||||||
PWR_CR_REG |= PM_STANDBY_CONFIG;
|
PWR_CR_REG |= PM_STANDBY_CONFIG;
|
||||||
@ -125,14 +131,12 @@ void pm_set(unsigned mode)
|
|||||||
deep = 1;
|
deep = 1;
|
||||||
break;
|
break;
|
||||||
#endif
|
#endif
|
||||||
#ifdef STM32_PM_STOP
|
|
||||||
case STM32_PM_STOP:
|
case STM32_PM_STOP:
|
||||||
PWR_CR_REG &= ~(PM_STOP_CONFIG | PM_STANDBY_CONFIG);
|
PWR_CR_REG &= ~(PM_STOP_CONFIG | PM_STANDBY_CONFIG);
|
||||||
PWR_CR_REG |= PM_STOP_CONFIG;
|
PWR_CR_REG |= PM_STOP_CONFIG;
|
||||||
/* Set SLEEPDEEP bit of system control block */
|
/* Set SLEEPDEEP bit of system control block */
|
||||||
deep = 1;
|
deep = 1;
|
||||||
break;
|
break;
|
||||||
#endif
|
|
||||||
default:
|
default:
|
||||||
deep = 0;
|
deep = 0;
|
||||||
break;
|
break;
|
||||||
@ -142,7 +146,9 @@ void pm_set(unsigned mode)
|
|||||||
|
|
||||||
if (deep) {
|
if (deep) {
|
||||||
/* Re-init clock after STOP */
|
/* Re-init clock after STOP */
|
||||||
|
#if !defined(CPU_FAM_STM32MP1) || IS_USED(MODULE_STM32MP1_ENG_MODE)
|
||||||
stmclk_init_sysclk();
|
stmclk_init_sysclk();
|
||||||
|
#endif
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|||||||
@ -45,7 +45,7 @@
|
|||||||
#elif defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0) || \
|
#elif defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0) || \
|
||||||
defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L4) || \
|
defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L4) || \
|
||||||
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32F7) || \
|
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32F7) || \
|
||||||
defined(CPU_FAM_STM32G4)
|
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32MP1)
|
||||||
#define ISR_REG ISR
|
#define ISR_REG ISR
|
||||||
#define ISR_TXE USART_ISR_TXE
|
#define ISR_TXE USART_ISR_TXE
|
||||||
#define ISR_RXNE USART_ISR_RXNE
|
#define ISR_RXNE USART_ISR_RXNE
|
||||||
@ -297,7 +297,24 @@ static inline void uart_init_usart(uart_t uart, uint32_t baudrate)
|
|||||||
uint32_t clk;
|
uint32_t clk;
|
||||||
|
|
||||||
/* calculate and apply baudrate */
|
/* calculate and apply baudrate */
|
||||||
|
#ifdef CPU_FAM_STM32MP1
|
||||||
|
RCC->UART35CKSELR = uart_config[uart].clk_src;
|
||||||
|
|
||||||
|
switch (uart_config[uart].clk_src) {
|
||||||
|
case RCC_UART35CKSELR_UART35SRC_2: /* HSI */
|
||||||
|
clk = CLOCK_HSI;
|
||||||
|
break;
|
||||||
|
case RCC_UART35CKSELR_UART35SRC_4: /* HSE */
|
||||||
|
clk = CLOCK_HSE;
|
||||||
|
break;
|
||||||
|
default: /* return */
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
clk /= baudrate;
|
||||||
|
#else
|
||||||
clk = periph_apb_clk(uart_config[uart].bus) / baudrate;
|
clk = periph_apb_clk(uart_config[uart].bus) / baudrate;
|
||||||
|
#endif
|
||||||
mantissa = (uint16_t)(clk / 16);
|
mantissa = (uint16_t)(clk / 16);
|
||||||
fraction = (uint8_t)(clk - (mantissa * 16));
|
fraction = (uint8_t)(clk - (mantissa * 16));
|
||||||
dev(uart)->BRR = ((mantissa & 0x0fff) << 4) | (fraction & 0x0f);
|
dev(uart)->BRR = ((mantissa & 0x0fff) << 4) | (fraction & 0x0f);
|
||||||
|
|||||||
@ -8,15 +8,20 @@
|
|||||||
# - STM32_PINCOUNT: R (64)
|
# - STM32_PINCOUNT: R (64)
|
||||||
# - STM32_ROMSIZE: G (1024K)
|
# - STM32_ROMSIZE: G (1024K)
|
||||||
CPU_MODEL_UPPERCASE = $(call uppercase,$(CPU_MODEL))
|
CPU_MODEL_UPPERCASE = $(call uppercase,$(CPU_MODEL))
|
||||||
STM32_INFO := $(shell echo $(CPU_MODEL_UPPERCASE) | sed -E -e 's/^STM32(F|L|W|G)([0-7]|B)([A-Z0-9])([0-9])(.)(.)(_A)?/\1 \2 \2\3\4 \3 \4 \5 \6 \7/')
|
STM32_INFO := $(shell echo $(CPU_MODEL_UPPERCASE) | sed -E -e 's/^STM32(F|L|W|G|MP)([0-7]|B)([A-Z0-9])([0-9])(.)(.)?(_A)?/\1 \2 \2\3\4 \3 \4 \5 \6 \7/')
|
||||||
STM32_TYPE = $(word 1, $(STM32_INFO))
|
STM32_TYPE = $(word 1, $(STM32_INFO))
|
||||||
STM32_FAMILY = $(word 2, $(STM32_INFO))
|
STM32_FAMILY = $(word 2, $(STM32_INFO))
|
||||||
STM32_MODEL = $(word 3, $(STM32_INFO))
|
STM32_MODEL = $(word 3, $(STM32_INFO))
|
||||||
STM32_MODEL2 = $(word 4, $(STM32_INFO))
|
ifneq (MP, $(STM32_TYPE))
|
||||||
STM32_MODEL3 = $(word 5, $(STM32_INFO))
|
STM32_MODEL2 = $(word 4, $(STM32_INFO))
|
||||||
STM32_PINCOUNT = $(word 6, $(STM32_INFO))
|
STM32_MODEL3 = $(word 5, $(STM32_INFO))
|
||||||
STM32_ROMSIZE = $(word 7, $(STM32_INFO))
|
STM32_PINCOUNT = $(word 6, $(STM32_INFO))
|
||||||
STM32_RAMMOD = $(word 8, $(STM32_INFO))
|
STM32_ROMSIZE = $(word 7, $(STM32_INFO))
|
||||||
|
STM32_RAMMOD = $(word 8, $(STM32_INFO))
|
||||||
|
else
|
||||||
|
STM32_MODEL2 = $(word 6, $(STM32_INFO))
|
||||||
|
STM32_PINCOUNT = $(word 7, $(STM32_INFO))$(word 8, $(STM32_INFO))
|
||||||
|
endif
|
||||||
|
|
||||||
CPU_FAM = $(call lowercase,$(STM32_TYPE)$(STM32_FAMILY))
|
CPU_FAM = $(call lowercase,$(STM32_TYPE)$(STM32_FAMILY))
|
||||||
|
|
||||||
@ -24,7 +29,7 @@ ifeq (f0,$(CPU_FAM))
|
|||||||
CPU_CORE = cortex-m0
|
CPU_CORE = cortex-m0
|
||||||
else ifneq (,$(filter $(CPU_FAM),f1 f2 l1))
|
else ifneq (,$(filter $(CPU_FAM),f1 f2 l1))
|
||||||
CPU_CORE = cortex-m3
|
CPU_CORE = cortex-m3
|
||||||
else ifneq (,$(filter $(CPU_FAM),f3 f4 l4))
|
else ifneq (,$(filter $(CPU_FAM),f3 f4 l4 mp1))
|
||||||
CPU_CORE = cortex-m4f
|
CPU_CORE = cortex-m4f
|
||||||
else ifneq (,$(filter $(CPU_FAM),g4 wb))
|
else ifneq (,$(filter $(CPU_FAM),g4 wb))
|
||||||
CPU_CORE = cortex-m4
|
CPU_CORE = cortex-m4
|
||||||
|
|||||||
@ -137,3 +137,10 @@ ifeq (L,$(STM32_TYPE))
|
|||||||
endif
|
endif
|
||||||
endif
|
endif
|
||||||
endif
|
endif
|
||||||
|
ifeq (MP,$(STM32_TYPE))
|
||||||
|
ifeq (157,$(STM32_MODEL))
|
||||||
|
ifeq (C,$(STM32_MODEL2))
|
||||||
|
CPU_LINE = STM32MP157Cxx
|
||||||
|
endif
|
||||||
|
endif
|
||||||
|
endif
|
||||||
|
|||||||
@ -1,7 +1,3 @@
|
|||||||
# Set the common memory addresses for stm32 MCU family
|
|
||||||
ROM_START_ADDR ?= 0x08000000
|
|
||||||
RAM_START_ADDR ?= 0x20000000
|
|
||||||
|
|
||||||
# The next block takes care of setting the rigth lengths of RAM and ROM
|
# The next block takes care of setting the rigth lengths of RAM and ROM
|
||||||
# for the stm32 family. Most of the CPUs should have been taken into
|
# for the stm32 family. Most of the CPUs should have been taken into
|
||||||
# account here, so no need to assign the lengths per model.
|
# account here, so no need to assign the lengths per model.
|
||||||
@ -278,6 +274,13 @@ else ifeq ($(STM32_TYPE), W)
|
|||||||
endif
|
endif
|
||||||
endif
|
endif
|
||||||
endif
|
endif
|
||||||
|
else ifeq ($(STM32_TYPE), MP)
|
||||||
|
ifeq ($(STM32_FAMILY), 1)
|
||||||
|
ifeq ($(STM32_MODEL), 157)
|
||||||
|
RAM_START_ADDR = 0x10000000
|
||||||
|
RAM_LEN = 384K
|
||||||
|
endif
|
||||||
|
endif
|
||||||
endif
|
endif
|
||||||
|
|
||||||
ifeq ($(RAM_LEN), )
|
ifeq ($(RAM_LEN), )
|
||||||
@ -308,6 +311,26 @@ else ifeq ($(STM32_ROMSIZE), H)
|
|||||||
ROM_LEN = 1536K
|
ROM_LEN = 1536K
|
||||||
else ifeq ($(STM32_ROMSIZE), I)
|
else ifeq ($(STM32_ROMSIZE), I)
|
||||||
ROM_LEN = 2048K
|
ROM_LEN = 2048K
|
||||||
|
else ifeq ($(STM32_TYPE), MP)
|
||||||
|
ifeq ($(STM32_FAMILY), 1)
|
||||||
|
# STM32MP1 family has no flash ROM memory.
|
||||||
|
# Thus a part of SRAM must be considered as ROM.
|
||||||
|
# RETRAM (0x0 address) is setup as ROM by default.
|
||||||
|
# However in RIOT, vector table is relocated using VTOR register.
|
||||||
|
# Considering the minimum alignment is 128 words and knowing the number of
|
||||||
|
# interrupt vectors for a given MCU, if a device has for example 150 interrupt
|
||||||
|
# channels:
|
||||||
|
# Vector table has a size of 150 * 4 = 600 = 0x258
|
||||||
|
# As the table should be 128 word aligned, vector table size reserved is 0x400.
|
||||||
|
ifeq ($(STM32_MODEL), 157)
|
||||||
|
ROM_START_ADDR ?= 0x0
|
||||||
|
ifneq (,$(filter stm32mp1_eng_mode,$(USEMODULE)))
|
||||||
|
ROM_OFFSET ?= 0x400
|
||||||
|
endif
|
||||||
|
ROM_LEN ?= 64K
|
||||||
|
endif
|
||||||
|
endif
|
||||||
|
else
|
||||||
endif
|
endif
|
||||||
|
|
||||||
ifeq ($(STM32_PINCOUNT), A)
|
ifeq ($(STM32_PINCOUNT), A)
|
||||||
@ -348,4 +371,10 @@ else ifeq ($(STM32_PINCOUNT), V)
|
|||||||
STM32_PIN = 100
|
STM32_PIN = 100
|
||||||
else ifeq ($(STM32_PINCOUNT), Z)
|
else ifeq ($(STM32_PINCOUNT), Z)
|
||||||
STM32_PIN = 144
|
STM32_PIN = 144
|
||||||
|
else ifeq ($(STM32_PINCOUNT), AC)
|
||||||
|
STM32_PIN = 361
|
||||||
endif
|
endif
|
||||||
|
|
||||||
|
# Set the common memory addresses for stm32 MCU family
|
||||||
|
ROM_START_ADDR ?= 0x08000000
|
||||||
|
RAM_START_ADDR ?= 0x20000000
|
||||||
|
|||||||
@ -1,6 +1,8 @@
|
|||||||
MODULE = stm32_clk
|
MODULE = stm32_clk
|
||||||
|
|
||||||
SRC = stmclk_common.c
|
ifneq (mp1,$(CPU_FAM))
|
||||||
|
SRC = stmclk_common.c
|
||||||
|
endif
|
||||||
|
|
||||||
ifneq (,$(filter $(CPU_FAM),f2 f4 f7))
|
ifneq (,$(filter $(CPU_FAM),f2 f4 f7))
|
||||||
SRC += stmclk_f2f4f7.c
|
SRC += stmclk_f2f4f7.c
|
||||||
@ -14,6 +16,13 @@ else ifneq (,$(filter $(CPU_FAM),l5))
|
|||||||
SRC += stmclk_l5.c
|
SRC += stmclk_l5.c
|
||||||
else ifneq (,$(filter $(CPU_FAM),g0 g4))
|
else ifneq (,$(filter $(CPU_FAM),g0 g4))
|
||||||
SRC += stmclk_gx.c
|
SRC += stmclk_gx.c
|
||||||
|
else ifneq (,$(filter $(CPU_FAM),mp1))
|
||||||
|
ifneq (,$(filter stm32mp1_eng_mode,$(USEMODULE)))
|
||||||
|
SRC = stmclk_mp1.c
|
||||||
|
else
|
||||||
|
# Do not use *.c as SRC if SRC is empty (see Makefile.base)
|
||||||
|
NO_AUTO_SRC = 1
|
||||||
|
endif
|
||||||
endif
|
endif
|
||||||
|
|
||||||
include $(RIOTBASE)/Makefile.base
|
include $(RIOTBASE)/Makefile.base
|
||||||
|
|||||||
220
cpu/stm32/stmclk/stmclk_mp1.c
Normal file
220
cpu/stm32/stmclk/stmclk_mp1.c
Normal file
@ -0,0 +1,220 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (C) 2020 Savoir-faire Linux
|
||||||
|
*
|
||||||
|
* This file is subject to the terms and conditions of the GNU Lesser General
|
||||||
|
* Public License v2.1. See the file LICENSE in the top level directory for more
|
||||||
|
* details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @ingroup cpu_stm32
|
||||||
|
* @{
|
||||||
|
*
|
||||||
|
* @file
|
||||||
|
* @brief Implementation of STM32 clock configuration for STM32MP1
|
||||||
|
*
|
||||||
|
* @author Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
|
||||||
|
*
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "cpu.h"
|
||||||
|
#include "stmclk.h"
|
||||||
|
#include "periph_conf.h"
|
||||||
|
|
||||||
|
/* PLL configuration */
|
||||||
|
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
|
||||||
|
#define PLL_SRC RCC_RCK3SELR_PLL3SRC_1
|
||||||
|
#else
|
||||||
|
#define PLL_SRC RCC_RCK3SELR_PLL3SRC_0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Compute the bitfields for the PLL configuration */
|
||||||
|
#define PLL_P (((CONFIG_CLOCK_PLL_P / 2)) \
|
||||||
|
<< RCC_PLL3CFGR2_DIVP_Pos)
|
||||||
|
#define PLL_M ((CONFIG_CLOCK_PLL_M) \
|
||||||
|
<< RCC_PLL3CFGR1_DIVM3_Pos)
|
||||||
|
#define PLL_N ((CONFIG_CLOCK_PLL_N) \
|
||||||
|
<< RCC_PLL3CFGR1_DIVN_Pos)
|
||||||
|
#define PLL_Q ((CONFIG_CLOCK_PLL_Q) \
|
||||||
|
<< RCC_PLL3CFGR2_DIVQ_Pos)
|
||||||
|
#if defined(RCC_PLL3CFGR2_DIVR) && defined(CONFIG_CLOCK_PLL_R)
|
||||||
|
#define PLL_R ((CONFIG_CLOCK_PLL_R) \
|
||||||
|
<< RCC_PLL3CFGR2_DIVR_Pos)
|
||||||
|
#else
|
||||||
|
#define PLL_R (0)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Configure HLCK and PCLK prescalers */
|
||||||
|
#if CONFIG_CLOCK_MCU_DIV == 1
|
||||||
|
#define CLOCK_MCU_DIV (RCC_MCUDIVR_MCUDIV_0)
|
||||||
|
#elif CONFIG_CLOCK_MCU_DIV == 2
|
||||||
|
#define CLOCK_MCU_DIV (RCC_MCUDIVR_MCUDIV_1)
|
||||||
|
#elif CONFIG_CLOCK_MCU_DIV == 4
|
||||||
|
#define CLOCK_MCU_DIV (RCC_MCUDIVR_MCUDIV_2)
|
||||||
|
#elif CONFIG_CLOCK_MCU_DIV == 8
|
||||||
|
#define CLOCK_MCU_DIV (RCC_MCUDIVR_MCUDIV_3)
|
||||||
|
#elif CONFIG_CLOCK_MCU_DIV == 16
|
||||||
|
#define CLOCK_MCU_DIV (RCC_MCUDIVR_MCUDIV_4)
|
||||||
|
#elif CONFIG_CLOCK_MCU_DIV == 32
|
||||||
|
#define CLOCK_MCU_DIV (RCC_MCUDIVR_MCUDIV_5)
|
||||||
|
#elif CONFIG_CLOCK_MCU_DIV == 64
|
||||||
|
#define CLOCK_MCU_DIV (RCC_MCUDIVR_MCUDIV_6)
|
||||||
|
#elif CONFIG_CLOCK_MCU_DIV == 128
|
||||||
|
#define CLOCK_MCU_DIV (RCC_MCUDIVR_MCUDIV_7)
|
||||||
|
#elif CONFIG_CLOCK_MCU_DIV == 256
|
||||||
|
#define CLOCK_MCU_DIV (RCC_MCUDIVR_MCUDIV_8)
|
||||||
|
#elif CONFIG_CLOCK_MCU_DIV == 512
|
||||||
|
#define CLOCK_MCU_DIV (RCC_MCUDIVR_MCUDIV_9)
|
||||||
|
#else
|
||||||
|
#error "Invalid MCU prescaler value (only 1, 2, 4, 8, 16, 32, 64, 128, 256 \
|
||||||
|
and 512 allowed)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CONFIG_CLOCK_APB1_DIV == 1
|
||||||
|
#define CLOCK_APB1_DIV (RCC_APB1DIVR_APB1DIV_0)
|
||||||
|
#elif CONFIG_CLOCK_APB1_DIV == 2
|
||||||
|
#define CLOCK_APB1_DIV (RCC_APB1DIVR_APB1DIV_1)
|
||||||
|
#elif CONFIG_CLOCK_APB1_DIV == 4
|
||||||
|
#define CLOCK_APB1_DIV (RCC_APB1DIVR_APB1DIV_2)
|
||||||
|
#elif CONFIG_CLOCK_APB1_DIV == 8
|
||||||
|
#define CLOCK_APB1_DIV (RCC_APB1DIVR_APB1DIV_3)
|
||||||
|
#elif CONFIG_CLOCK_APB1_DIV == 16
|
||||||
|
#define CLOCK_APB1_DIV (RCC_APB1DIVR_APB1DIV_4)
|
||||||
|
#else
|
||||||
|
#error "Invalid APB1 prescaler value (only 1, 2, 4, 8 and 16 allowed)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CONFIG_CLOCK_APB2_DIV == 1
|
||||||
|
#define CLOCK_APB2_DIV (RCC_APB2DIVR_APB2DIV_0)
|
||||||
|
#elif CONFIG_CLOCK_APB2_DIV == 2
|
||||||
|
#define CLOCK_APB2_DIV (RCC_APB2DIVR_APB2DIV_1)
|
||||||
|
#elif CONFIG_CLOCK_APB2_DIV == 4
|
||||||
|
#define CLOCK_APB2_DIV (RCC_APB2DIVR_APB2DIV_2)
|
||||||
|
#elif CONFIG_CLOCK_APB2_DIV == 8
|
||||||
|
#define CLOCK_APB2_DIV (RCC_APB2DIVR_APB2DIV_3)
|
||||||
|
#elif CONFIG_CLOCK_APB2_DIV == 16
|
||||||
|
#define CLOCK_APB2_DIV (RCC_APB2DIVR_APB2DIV_4)
|
||||||
|
#else
|
||||||
|
#error "Invalid APB2 prescaler value (only 1, 2, 4, 8 and 16 allowed)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CONFIG_CLOCK_APB3_DIV == 1
|
||||||
|
#define CLOCK_APB3_DIV (RCC_APB3DIVR_APB3DIV_0)
|
||||||
|
#elif CONFIG_CLOCK_APB3_DIV == 2
|
||||||
|
#define CLOCK_APB3_DIV (RCC_APB3DIVR_APB3DIV_1)
|
||||||
|
#elif CONFIG_CLOCK_APB3_DIV == 4
|
||||||
|
#define CLOCK_APB3_DIV (RCC_APB3DIVR_APB3DIV_2)
|
||||||
|
#elif CONFIG_CLOCK_APB3_DIV == 8
|
||||||
|
#define CLOCK_APB3_DIV (RCC_APB3DIVR_APB3DIV_3)
|
||||||
|
#elif CONFIG_CLOCK_APB3_DIV == 16
|
||||||
|
#define CLOCK_APB3_DIV (RCC_APB3DIVR_APB3DIV_4)
|
||||||
|
#else
|
||||||
|
#error "Invalid APB3 prescaler value (only 1, 2, 4, 8 and 16 allowed)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Check whether PLL must be enabled:
|
||||||
|
- When PLL is used as SYSCLK
|
||||||
|
- When PLLQ is required
|
||||||
|
*/
|
||||||
|
#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_CLOCK_ENABLE_PLLQ)
|
||||||
|
#define CONFIG_CLOCK_USE_PLL 1
|
||||||
|
#else
|
||||||
|
#define CONFIG_CLOCK_USE_PLL 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Check whether HSE must be enabled:
|
||||||
|
- When HSE is used as SYSCLK
|
||||||
|
- When PLL is used as SYSCLK and the board provides HSE (since HSE will be
|
||||||
|
used as PLL input clock)
|
||||||
|
*/
|
||||||
|
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || \
|
||||||
|
(IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && IS_ACTIVE(CONFIG_CLOCK_USE_PLL))
|
||||||
|
#define CONFIG_CLOCK_USE_HSE 1
|
||||||
|
#else
|
||||||
|
#define CONFIG_CLOCK_USE_HSE 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
void stmclk_enable_hsi(void)
|
||||||
|
{
|
||||||
|
RCC->OCENSETR |= RCC_OCENSETR_HSION;
|
||||||
|
while (!(RCC->OCRDYR & RCC_OCRDYR_HSIRDY)) {}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void stmclk_enable_hse(void)
|
||||||
|
{
|
||||||
|
RCC->OCENSETR |= RCC_OCENSETR_HSEON;
|
||||||
|
while (!(RCC->OCRDYR & RCC_OCRDYR_HSERDY)) {}
|
||||||
|
}
|
||||||
|
|
||||||
|
void stmclk_init_sysclk(void)
|
||||||
|
{
|
||||||
|
/* disable any interrupts. Global interrupts could be enabled if this is
|
||||||
|
* called from some kind of bootloader... */
|
||||||
|
unsigned is = irq_disable();
|
||||||
|
RCC->MC_CIFR = 0;
|
||||||
|
|
||||||
|
/* enable HSI clock for the duration of initialization */
|
||||||
|
stmclk_enable_hsi();
|
||||||
|
|
||||||
|
/* use HSI as system clock while we do any further configuration and
|
||||||
|
* configure the AHB and APB clock dividers as configured by the board */
|
||||||
|
/* MCUDIV */
|
||||||
|
RCC->MCUDIVR = CLOCK_MCU_DIV;
|
||||||
|
while ((RCC->MCUDIVR & RCC_MCUDIVR_MCUDIVRDY)
|
||||||
|
!= RCC_MCUDIVR_MCUDIVRDY) {}
|
||||||
|
/* APB1DIV */
|
||||||
|
RCC->APB1DIVR = CLOCK_APB1_DIV;
|
||||||
|
while ((RCC->APB1DIVR & RCC_APB1DIVR_APB1DIVRDY)
|
||||||
|
!= RCC_APB1DIVR_APB1DIVRDY) {}
|
||||||
|
/* APB2DIV */
|
||||||
|
RCC->APB2DIVR = CLOCK_APB2_DIV;
|
||||||
|
while ((RCC->APB2DIVR & RCC_APB2DIVR_APB2DIVRDY)
|
||||||
|
!= RCC_APB2DIVR_APB2DIVRDY) {}
|
||||||
|
/* APB3DIV */
|
||||||
|
RCC->APB3DIVR = CLOCK_APB3_DIV;
|
||||||
|
while ((RCC->APB3DIVR & RCC_APB3DIVR_APB3DIVRDY)
|
||||||
|
!= RCC_APB3DIVR_APB3DIVRDY) {}
|
||||||
|
|
||||||
|
/* MCU clock source */
|
||||||
|
RCC->MSSCKSELR = RCC_MSSCKSELR_MCUSSRC_0; /* HSI */
|
||||||
|
while ((RCC->MSSCKSELR & RCC_MSSCKSELR_MCUSSRCRDY)
|
||||||
|
!= RCC_MSSCKSELR_MCUSSRCRDY) {}
|
||||||
|
|
||||||
|
/* disable all active clocks except HSI -> resets the clk configuration */
|
||||||
|
RCC->OCENCLRR = ~(RCC_OCENSETR_HSION);
|
||||||
|
|
||||||
|
/* if configured, we need to enable the HSE clock now */
|
||||||
|
if (IS_ACTIVE(CONFIG_CLOCK_USE_HSE)) {
|
||||||
|
stmclk_enable_hse();
|
||||||
|
}
|
||||||
|
|
||||||
|
if (IS_ACTIVE(CONFIG_CLOCK_USE_PLL)) {
|
||||||
|
/* now we can safely configure the PLL */
|
||||||
|
RCC->PLL3CFGR1 = (PLL_M | PLL_N);
|
||||||
|
RCC->PLL3CFGR2 = (PLL_P | PLL_Q | PLL_R);
|
||||||
|
|
||||||
|
RCC->RCK3SELR |= PLL_SRC;
|
||||||
|
while (!(RCC->RCK3SELR & RCC_RCK3SELR_PLL3SRCRDY)) {}
|
||||||
|
|
||||||
|
/* and start the PLL */
|
||||||
|
RCC->PLL3CR |= (RCC_PLL3CR_DIVPEN | RCC_PLL3CR_DIVQEN
|
||||||
|
| RCC_PLL3CR_DIVREN | RCC_PLL3CR_PLLON);
|
||||||
|
while (!(RCC->PLL3CR & RCC_PLL3CR_PLL3RDY)) {}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Configure SYSCLK */
|
||||||
|
if (IS_ACTIVE(CONFIG_CLOCK_USE_PLL)) {
|
||||||
|
RCC->MSSCKSELR = RCC_MSSCKSELR_MCUSSRC_3; /* PLL3 */
|
||||||
|
}
|
||||||
|
else if (IS_ACTIVE(CONFIG_CLOCK_USE_HSE)) {
|
||||||
|
RCC->MSSCKSELR = RCC_MSSCKSELR_MCUSSRC_1; /* HSE */
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
RCC->MSSCKSELR = RCC_MSSCKSELR_MCUSSRC_0; /* HSI by default */
|
||||||
|
}
|
||||||
|
/* Wait SYSCLK to be ready */
|
||||||
|
while (!(RCC->MSSCKSELR & RCC_MSSCKSELR_MCUSSRCRDY)) {}
|
||||||
|
|
||||||
|
irq_restore(is);
|
||||||
|
}
|
||||||
3
dist/tools/openocd/adapters/stlink-dap.cfg
vendored
Normal file
3
dist/tools/openocd/adapters/stlink-dap.cfg
vendored
Normal file
@ -0,0 +1,3 @@
|
|||||||
|
try {
|
||||||
|
source [find interface/stlink-dap.cfg]
|
||||||
|
}
|
||||||
76
dist/tools/openocd/openocd.sh
vendored
76
dist/tools/openocd/openocd.sh
vendored
@ -51,6 +51,15 @@
|
|||||||
# DBG: debugger client command, default: 'gdb -q'
|
# DBG: debugger client command, default: 'gdb -q'
|
||||||
# TUI: if TUI!=null, the -tui option will be used
|
# TUI: if TUI!=null, the -tui option will be used
|
||||||
#
|
#
|
||||||
|
# debugr: debug <elfile>
|
||||||
|
# debug given file on the target but flash it first directly
|
||||||
|
# in RAM.
|
||||||
|
#
|
||||||
|
# flashr: flash <image_file>
|
||||||
|
# flash given file to the target but directly in RAM.
|
||||||
|
#
|
||||||
|
# See 'flash' command above for options
|
||||||
|
#
|
||||||
# debug-server: starts OpenOCD as GDB server, but does not connect to
|
# debug-server: starts OpenOCD as GDB server, but does not connect to
|
||||||
# to it with any frontend. This might be useful when using
|
# to it with any frontend. This might be useful when using
|
||||||
# IDEs.
|
# IDEs.
|
||||||
@ -67,6 +76,8 @@
|
|||||||
|
|
||||||
# Default GDB port, set to 0 to disable, required != 0 for debug and debug-server targets
|
# Default GDB port, set to 0 to disable, required != 0 for debug and debug-server targets
|
||||||
: ${GDB_PORT:=3333}
|
: ${GDB_PORT:=3333}
|
||||||
|
# Default GDB port core offset
|
||||||
|
: ${GDB_PORT_CORE_OFFSET:=0}
|
||||||
# Default telnet port, set to 0 to disable
|
# Default telnet port, set to 0 to disable
|
||||||
: ${TELNET_PORT:=4444}
|
: ${TELNET_PORT:=4444}
|
||||||
# Default TCL port, set to 0 to disable
|
# Default TCL port, set to 0 to disable
|
||||||
@ -86,7 +97,7 @@
|
|||||||
# Debugger client command, can be used to wrap GDB in a front-end
|
# Debugger client command, can be used to wrap GDB in a front-end
|
||||||
: ${DBG:=${GDB}}
|
: ${DBG:=${GDB}}
|
||||||
# Default debugger flags,
|
# Default debugger flags,
|
||||||
: ${DBG_DEFAULT_FLAGS:=-q -ex \"tar ext :${GDB_PORT}\"}
|
: ${DBG_DEFAULT_FLAGS:=-q -ex \"tar ext :$(( GDB_PORT + GDB_PORT_CORE_OFFSET ))\"}
|
||||||
# Extra debugger flags, added by the user
|
# Extra debugger flags, added by the user
|
||||||
: ${DBG_EXTRA_FLAGS:=}
|
: ${DBG_EXTRA_FLAGS:=}
|
||||||
# Debugger flags, will be passed to sh -c, remember to escape any quotation signs.
|
# Debugger flags, will be passed to sh -c, remember to escape any quotation signs.
|
||||||
@ -100,6 +111,8 @@
|
|||||||
: ${OPENOCD_DBG_EXTRA_CMD:=}
|
: ${OPENOCD_DBG_EXTRA_CMD:=}
|
||||||
# command used to reset the board
|
# command used to reset the board
|
||||||
: ${OPENOCD_CMD_RESET_RUN:="-c 'reset run'"}
|
: ${OPENOCD_CMD_RESET_RUN:="-c 'reset run'"}
|
||||||
|
# Select core on multi-core processors.
|
||||||
|
: ${OPENOCD_CORE:=}
|
||||||
# This is an optional offset to the base address that can be used to flash an
|
# This is an optional offset to the base address that can be used to flash an
|
||||||
# image in a different location than it is linked at. This feature can be useful
|
# image in a different location than it is linked at. This feature can be useful
|
||||||
# when flashing images for firmware swapping/remapping boot loaders.
|
# when flashing images for firmware swapping/remapping boot loaders.
|
||||||
@ -254,6 +267,52 @@ _flash_address() {
|
|||||||
_flash_list | awk "NR==${bank_num}"'{printf "0x%08x\n", $4}'
|
_flash_list | awk "NR==${bank_num}"'{printf "0x%08x\n", $4}'
|
||||||
}
|
}
|
||||||
|
|
||||||
|
do_flashr() {
|
||||||
|
IMAGE_FILE=$1
|
||||||
|
test_config
|
||||||
|
test_imagefile
|
||||||
|
if [ -n "${PRE_FLASH_CHECK_SCRIPT}" ]; then
|
||||||
|
sh -c "${PRE_FLASH_CHECK_SCRIPT} '${IMAGE_FILE}'"
|
||||||
|
RETVAL=$?
|
||||||
|
if [ $RETVAL -ne 0 ]; then
|
||||||
|
echo "pre-flash checks failed, status=$RETVAL"
|
||||||
|
exit $RETVAL
|
||||||
|
fi
|
||||||
|
fi
|
||||||
|
|
||||||
|
# In case of binary file, IMAGE_OFFSET should include the flash base address
|
||||||
|
# This allows flashing normal binary files without env configuration
|
||||||
|
if _is_binfile "${IMAGE_FILE}" "${IMAGE_TYPE}"; then
|
||||||
|
# hardwritten to use the first bank
|
||||||
|
FLASH_ADDR=$(_flash_address 1)
|
||||||
|
echo "Binfile detected, adding ROM base address: ${FLASH_ADDR}"
|
||||||
|
IMAGE_TYPE=bin
|
||||||
|
IMAGE_OFFSET=$(printf "0x%08x\n" "$((${IMAGE_OFFSET} + ${FLASH_ADDR}))")
|
||||||
|
fi
|
||||||
|
|
||||||
|
if [ "${IMAGE_OFFSET}" != "0" ]; then
|
||||||
|
echo "Flashing with IMAGE_OFFSET: ${IMAGE_OFFSET}"
|
||||||
|
fi
|
||||||
|
|
||||||
|
# flash device
|
||||||
|
sh -c "${OPENOCD} \
|
||||||
|
${OPENOCD_ADAPTER_INIT} \
|
||||||
|
-f '${OPENOCD_CONFIG}' \
|
||||||
|
${OPENOCD_EXTRA_INIT} \
|
||||||
|
${OPENOCD_EXTRA_RESET_INIT} \
|
||||||
|
-c 'tcl_port 0' \
|
||||||
|
-c 'telnet_port 0' \
|
||||||
|
-c 'gdb_port 0' \
|
||||||
|
-c 'init' \
|
||||||
|
-c 'targets ${OPENOCD_CORE}' \
|
||||||
|
-c 'reset' \
|
||||||
|
-c 'halt' \
|
||||||
|
-c 'load_image \"${IMAGE_FILE}\" ' \
|
||||||
|
-c 'resume ${START_ADDR}' \
|
||||||
|
-c 'shutdown'" &&
|
||||||
|
echo "'Done flashing"
|
||||||
|
}
|
||||||
|
|
||||||
#
|
#
|
||||||
# now comes the actual actions
|
# now comes the actual actions
|
||||||
#
|
#
|
||||||
@ -332,7 +391,7 @@ do_debug() {
|
|||||||
-c 'gdb_port ${GDB_PORT}' \
|
-c 'gdb_port ${GDB_PORT}' \
|
||||||
-c 'init' \
|
-c 'init' \
|
||||||
${OPENOCD_DBG_EXTRA_CMD} \
|
${OPENOCD_DBG_EXTRA_CMD} \
|
||||||
-c 'targets' \
|
-c 'targets ${OPENOCD_CORE}' \
|
||||||
${OPENOCD_DBG_START_CMD} \
|
${OPENOCD_DBG_START_CMD} \
|
||||||
-l /dev/null & \
|
-l /dev/null & \
|
||||||
echo \$! > $OCD_PIDFILE" &
|
echo \$! > $OCD_PIDFILE" &
|
||||||
@ -391,6 +450,19 @@ case "${ACTION}" in
|
|||||||
echo "### Flashing Target ###"
|
echo "### Flashing Target ###"
|
||||||
do_flash "$@"
|
do_flash "$@"
|
||||||
;;
|
;;
|
||||||
|
flashr)
|
||||||
|
START_ADDR=$(objdump -f $1 | sed '/^$/d' | tail -1 | grep -o "0x[0-9a-fA-F].*")
|
||||||
|
echo "### Flashing target RAM ###"
|
||||||
|
do_flashr "$@"
|
||||||
|
;;
|
||||||
|
debugr)
|
||||||
|
START_ADDR=$(objdump -f $1 | sed '/^$/d' | tail -1 | grep -o "0x[0-9a-fA-F].*")
|
||||||
|
echo "Start address: $START_ADDR"
|
||||||
|
DBG_FLAGS="$DBG_FLAGS \
|
||||||
|
-ex 'load $1' \
|
||||||
|
"
|
||||||
|
do_debug "$@"
|
||||||
|
;;
|
||||||
debug)
|
debug)
|
||||||
echo "### Starting Debugging ###"
|
echo "### Starting Debugging ###"
|
||||||
do_debug "$@"
|
do_debug "$@"
|
||||||
|
|||||||
@ -37,5 +37,6 @@ BOARD_INSUFFICIENT_MEMORY := \
|
|||||||
stm32f030f4-demo \
|
stm32f030f4-demo \
|
||||||
stm32f0discovery \
|
stm32f0discovery \
|
||||||
stm32l0538-disco \
|
stm32l0538-disco \
|
||||||
|
stm32mp157c-dk2 \
|
||||||
yunjia-nrf51822 \
|
yunjia-nrf51822 \
|
||||||
#
|
#
|
||||||
|
|||||||
@ -40,5 +40,6 @@ BOARD_INSUFFICIENT_MEMORY := \
|
|||||||
stm32f0discovery \
|
stm32f0discovery \
|
||||||
stm32l0538-disco \
|
stm32l0538-disco \
|
||||||
stm32mindev \
|
stm32mindev \
|
||||||
|
stm32mp157c-dk2 \
|
||||||
yunjia-nrf51822 \
|
yunjia-nrf51822 \
|
||||||
#
|
#
|
||||||
|
|||||||
@ -35,5 +35,6 @@ BOARD_INSUFFICIENT_MEMORY := \
|
|||||||
stm32f0discovery \
|
stm32f0discovery \
|
||||||
stm32l0538-disco \
|
stm32l0538-disco \
|
||||||
stm32mindev \
|
stm32mindev \
|
||||||
|
stm32mp157c-dk2 \
|
||||||
yunjia-nrf51822 \
|
yunjia-nrf51822 \
|
||||||
#
|
#
|
||||||
|
|||||||
@ -52,6 +52,7 @@ BOARD_INSUFFICIENT_MEMORY := \
|
|||||||
stm32f030f4-demo \
|
stm32f030f4-demo \
|
||||||
stm32f0discovery \
|
stm32f0discovery \
|
||||||
stm32l0538-disco \
|
stm32l0538-disco \
|
||||||
|
stm32mp157c-dk2 \
|
||||||
telosb \
|
telosb \
|
||||||
waspmote-pro \
|
waspmote-pro \
|
||||||
weio \
|
weio \
|
||||||
|
|||||||
@ -38,6 +38,7 @@ BOARD_INSUFFICIENT_MEMORY := \
|
|||||||
stm32f030f4-demo \
|
stm32f030f4-demo \
|
||||||
stm32f0discovery \
|
stm32f0discovery \
|
||||||
stm32l0538-disco \
|
stm32l0538-disco \
|
||||||
|
stm32mp157c-dk2 \
|
||||||
telosb \
|
telosb \
|
||||||
waspmote-pro \
|
waspmote-pro \
|
||||||
z1 \
|
z1 \
|
||||||
|
|||||||
@ -47,5 +47,6 @@ BOARD_INSUFFICIENT_MEMORY := \
|
|||||||
stm32f030f4-demo \
|
stm32f030f4-demo \
|
||||||
stm32f0discovery \
|
stm32f0discovery \
|
||||||
stm32l0538-disco \
|
stm32l0538-disco \
|
||||||
|
stm32mp157c-dk2 \
|
||||||
yunjia-nrf51822 \
|
yunjia-nrf51822 \
|
||||||
#
|
#
|
||||||
|
|||||||
@ -91,6 +91,7 @@ BOARD_INSUFFICIENT_MEMORY := \
|
|||||||
stm32f0discovery \
|
stm32f0discovery \
|
||||||
stm32f3discovery \
|
stm32f3discovery \
|
||||||
stm32l0538-disco \
|
stm32l0538-disco \
|
||||||
|
stm32mp157c-dk2 \
|
||||||
wemos-zero \
|
wemos-zero \
|
||||||
yarm \
|
yarm \
|
||||||
yunjia-nrf51822 \
|
yunjia-nrf51822 \
|
||||||
|
|||||||
@ -38,4 +38,5 @@ BOARD_INSUFFICIENT_MEMORY := \
|
|||||||
stm32f030f4-demo \
|
stm32f030f4-demo \
|
||||||
stm32f0discovery \
|
stm32f0discovery \
|
||||||
stm32l0538-disco \
|
stm32l0538-disco \
|
||||||
|
stm32mp157c-dk2 \
|
||||||
#
|
#
|
||||||
|
|||||||
@ -26,4 +26,5 @@ BOARD_INSUFFICIENT_MEMORY := \
|
|||||||
stm32f030f4-demo \
|
stm32f030f4-demo \
|
||||||
stm32f0discovery \
|
stm32f0discovery \
|
||||||
stm32l0538-disco \
|
stm32l0538-disco \
|
||||||
|
stm32mp157c-dk2 \
|
||||||
#
|
#
|
||||||
|
|||||||
@ -27,5 +27,6 @@ BOARD_INSUFFICIENT_MEMORY := \
|
|||||||
stm32f030f4-demo \
|
stm32f030f4-demo \
|
||||||
stm32f0discovery \
|
stm32f0discovery \
|
||||||
stm32l0538-disco \
|
stm32l0538-disco \
|
||||||
|
stm32mp157c-dk2 \
|
||||||
yunjia-nrf51822 \
|
yunjia-nrf51822 \
|
||||||
#
|
#
|
||||||
|
|||||||
@ -34,5 +34,6 @@ BOARD_INSUFFICIENT_MEMORY := \
|
|||||||
stm32f030f4-demo \
|
stm32f030f4-demo \
|
||||||
stm32f0discovery \
|
stm32f0discovery \
|
||||||
stm32l0538-disco \
|
stm32l0538-disco \
|
||||||
|
stm32mp157c-dk2 \
|
||||||
yunjia-nrf51822 \
|
yunjia-nrf51822 \
|
||||||
#
|
#
|
||||||
|
|||||||
@ -125,6 +125,7 @@ PSEUDOMODULES += stdio_uart_rx
|
|||||||
PSEUDOMODULES += stm32_eth
|
PSEUDOMODULES += stm32_eth
|
||||||
PSEUDOMODULES += stm32_eth_auto
|
PSEUDOMODULES += stm32_eth_auto
|
||||||
PSEUDOMODULES += stm32_eth_link_up
|
PSEUDOMODULES += stm32_eth_link_up
|
||||||
|
PSEUDOMODULES += stm32mp1_eng_mode
|
||||||
PSEUDOMODULES += suit_transport_%
|
PSEUDOMODULES += suit_transport_%
|
||||||
PSEUDOMODULES += suit_storage_%
|
PSEUDOMODULES += suit_storage_%
|
||||||
PSEUDOMODULES += wakaama_objects_%
|
PSEUDOMODULES += wakaama_objects_%
|
||||||
|
|||||||
5
makefiles/tools/openocd-adapters/stlink-dap.inc.mk
Normal file
5
makefiles/tools/openocd-adapters/stlink-dap.inc.mk
Normal file
@ -0,0 +1,5 @@
|
|||||||
|
OPENOCD_ADAPTER_INIT ?= -c 'set stlink_version $(STLINK_VERSION);source $(RIOTBASE)/dist/tools/openocd/adapters/stlink-dap.cfg'
|
||||||
|
|
||||||
|
OPENOCD_TRANSPORT ?= dapdirect_swd
|
||||||
|
|
||||||
|
include $(RIOTMAKE)/tools/openocd-adapters/stlink.inc.mk
|
||||||
@ -16,10 +16,17 @@ endif
|
|||||||
|
|
||||||
OPENOCD_CONFIG ?= $(BOARDDIR)/dist/openocd.cfg
|
OPENOCD_CONFIG ?= $(BOARDDIR)/dist/openocd.cfg
|
||||||
|
|
||||||
# Export OPENOCD_CONFIG to required targets
|
|
||||||
OPENOCD_TARGETS = debug% flash% reset
|
OPENOCD_TARGETS = debug% flash% reset
|
||||||
|
|
||||||
|
# Export GDB_PORT_CORE_OFFSET to required targets
|
||||||
|
$(call target-export-variables,$(OPENOCD_TARGETS),GDB_PORT_CORE_OFFSET)
|
||||||
|
|
||||||
|
# Export OPENOCD_CONFIG to required targets
|
||||||
$(call target-export-variables,$(OPENOCD_TARGETS),OPENOCD_CONFIG)
|
$(call target-export-variables,$(OPENOCD_TARGETS),OPENOCD_CONFIG)
|
||||||
|
|
||||||
|
# Export OPENOCD_CORE to required targets
|
||||||
|
$(call target-export-variables,$(OPENOCD_TARGETS),OPENOCD_CORE)
|
||||||
|
|
||||||
# Export OPENOCD_ADAPTER_INIT to required targets
|
# Export OPENOCD_ADAPTER_INIT to required targets
|
||||||
$(call target-export-variables,$(OPENOCD_TARGETS),OPENOCD_ADAPTER_INIT)
|
$(call target-export-variables,$(OPENOCD_TARGETS),OPENOCD_ADAPTER_INIT)
|
||||||
|
|
||||||
|
|||||||
@ -11,11 +11,12 @@ diff --git a/MQTTClient-C/src/MQTTClient.h b/MQTTClient-C/src/MQTTClient.h
|
|||||||
index b612341..4f1dfba 100755
|
index b612341..4f1dfba 100755
|
||||||
--- a/MQTTClient-C/src/MQTTClient.h
|
--- a/MQTTClient-C/src/MQTTClient.h
|
||||||
+++ b/MQTTClient-C/src/MQTTClient.h
|
+++ b/MQTTClient-C/src/MQTTClient.h
|
||||||
@@ -54,7 +54,13 @@
|
@@ -54,7 +54,14 @@
|
||||||
enum QoS { QOS0, QOS1, QOS2, SUBFAIL=0x80 };
|
enum QoS { QOS0, QOS1, QOS2, SUBFAIL=0x80 };
|
||||||
|
|
||||||
/* all failure return codes must be negative */
|
/* all failure return codes must be negative */
|
||||||
+#if !defined(CPU_LINE_STM32F030x4) && defined(CPU_STM32)
|
+#if !defined(CPU_LINE_STM32F030x4) && !defined(CPU_LINE_STM32MP157Cxx) && \
|
||||||
|
+ defined(CPU_STM32)
|
||||||
+/* the SUCCESS enum is defined for all stm32.
|
+/* the SUCCESS enum is defined for all stm32.
|
||||||
+ Since it contains the same value, we just skip its definition here for them. */
|
+ Since it contains the same value, we just skip its definition here for them. */
|
||||||
+enum returnCode { BUFFER_OVERFLOW = -2, FAILURE = -1};
|
+enum returnCode { BUFFER_OVERFLOW = -2, FAILURE = -1};
|
||||||
|
|||||||
@ -51,6 +51,7 @@ BOARD_INSUFFICIENT_MEMORY := \
|
|||||||
stm32f030f4-demo \
|
stm32f030f4-demo \
|
||||||
stm32f0discovery \
|
stm32f0discovery \
|
||||||
stm32l0538-disco \
|
stm32l0538-disco \
|
||||||
|
stm32mp157c-dk2 \
|
||||||
telosb \
|
telosb \
|
||||||
waspmote-pro \
|
waspmote-pro \
|
||||||
yunjia-nrf51822 \
|
yunjia-nrf51822 \
|
||||||
|
|||||||
@ -34,6 +34,7 @@ BOARD_INSUFFICIENT_MEMORY := \
|
|||||||
stm32f030f4-demo \
|
stm32f030f4-demo \
|
||||||
stm32f0discovery \
|
stm32f0discovery \
|
||||||
stm32l0538-disco \
|
stm32l0538-disco \
|
||||||
|
stm32mp157c-dk2 \
|
||||||
telosb \
|
telosb \
|
||||||
waspmote-pro \
|
waspmote-pro \
|
||||||
z1 \
|
z1 \
|
||||||
|
|||||||
@ -52,6 +52,7 @@ BOARD_INSUFFICIENT_MEMORY := \
|
|||||||
stm32f030f4-demo \
|
stm32f030f4-demo \
|
||||||
stm32f0discovery \
|
stm32f0discovery \
|
||||||
stm32l0538-disco \
|
stm32l0538-disco \
|
||||||
|
stm32mp157c-dk2 \
|
||||||
telosb \
|
telosb \
|
||||||
waspmote-pro \
|
waspmote-pro \
|
||||||
yunjia-nrf51822 \
|
yunjia-nrf51822 \
|
||||||
|
|||||||
@ -41,6 +41,7 @@ BOARD_INSUFFICIENT_MEMORY := \
|
|||||||
stm32f030f4-demo \
|
stm32f030f4-demo \
|
||||||
stm32f0discovery \
|
stm32f0discovery \
|
||||||
stm32l0538-disco \
|
stm32l0538-disco \
|
||||||
|
stm32mp157c-dk2 \
|
||||||
telosb \
|
telosb \
|
||||||
waspmote-pro \
|
waspmote-pro \
|
||||||
yunjia-nrf51822 \
|
yunjia-nrf51822 \
|
||||||
|
|||||||
@ -21,5 +21,6 @@ BOARD_INSUFFICIENT_MEMORY := \
|
|||||||
stm32f030f4-demo \
|
stm32f030f4-demo \
|
||||||
stm32f0discovery \
|
stm32f0discovery \
|
||||||
stm32l0538-disco \
|
stm32l0538-disco \
|
||||||
|
stm32mp157c-dk2 \
|
||||||
yunjia-nrf51822 \
|
yunjia-nrf51822 \
|
||||||
#
|
#
|
||||||
|
|||||||
@ -17,4 +17,5 @@ BOARD_INSUFFICIENT_MEMORY := \
|
|||||||
stm32f030f4-demo \
|
stm32f030f4-demo \
|
||||||
stm32f0discovery \
|
stm32f0discovery \
|
||||||
stm32l0538-disco \
|
stm32l0538-disco \
|
||||||
|
stm32mp157c-dk2 \
|
||||||
#
|
#
|
||||||
|
|||||||
@ -32,6 +32,7 @@ BOARD_INSUFFICIENT_MEMORY := \
|
|||||||
stm32f030f4-demo \
|
stm32f030f4-demo \
|
||||||
stm32f0discovery \
|
stm32f0discovery \
|
||||||
stm32l0538-disco \
|
stm32l0538-disco \
|
||||||
|
stm32mp157c-dk2 \
|
||||||
usb-kw41z \
|
usb-kw41z \
|
||||||
yunjia-nrf51822 \
|
yunjia-nrf51822 \
|
||||||
#
|
#
|
||||||
|
|||||||
@ -40,5 +40,6 @@ BOARD_INSUFFICIENT_MEMORY := \
|
|||||||
stm32f0discovery \
|
stm32f0discovery \
|
||||||
stm32l0538-disco \
|
stm32l0538-disco \
|
||||||
stm32mindev \
|
stm32mindev \
|
||||||
|
stm32mp157c-dk2 \
|
||||||
yunjia-nrf51822 \
|
yunjia-nrf51822 \
|
||||||
#
|
#
|
||||||
|
|||||||
@ -38,4 +38,5 @@ BOARD_INSUFFICIENT_MEMORY := \
|
|||||||
stm32f030f4-demo \
|
stm32f030f4-demo \
|
||||||
stm32f0discovery \
|
stm32f0discovery \
|
||||||
stm32l0538-disco \
|
stm32l0538-disco \
|
||||||
|
stm32mp157c-dk2 \
|
||||||
#
|
#
|
||||||
|
|||||||
@ -17,4 +17,5 @@ BOARD_INSUFFICIENT_MEMORY := \
|
|||||||
stm32f030f4-demo \
|
stm32f030f4-demo \
|
||||||
stm32f0discovery \
|
stm32f0discovery \
|
||||||
stm32l0538-disco \
|
stm32l0538-disco \
|
||||||
|
stm32mp157c-dk2 \
|
||||||
#
|
#
|
||||||
|
|||||||
@ -100,6 +100,7 @@ BOARD_INSUFFICIENT_MEMORY := \
|
|||||||
stm32f0discovery \
|
stm32f0discovery \
|
||||||
stm32f3discovery \
|
stm32f3discovery \
|
||||||
stm32l0538-disco \
|
stm32l0538-disco \
|
||||||
|
stm32mp157c-dk2 \
|
||||||
teensy31 \
|
teensy31 \
|
||||||
telosb \
|
telosb \
|
||||||
waspmote-pro \
|
waspmote-pro \
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user