Merge pull request #6790 from gebart/pr/kinetis-drop-mk60dz

k60: drop broken support for mk60dz10

boards/mulle/Makefile.include

@@ -5,22 +5,7 @@ export CPU = k60
 export GDBPORT ?= 3333
 
 # MULLE_SERIAL is used to select which specific Mulle board we are compiling for.
-# This was called MULLE_BOARD_SERIAL_NUMBER previously, renamed because
-# MULLE_BOARD_SERIAL_NUMBER is too long to type.
 ifdef MULLE_SERIAL
-  ifeq "200" "$(word 1, $(sort 200 $(MULLE_SERIAL)))"
-    # >= 200
-    ifneq "220" "$(word 1, $(sort 220 $(MULLE_SERIAL)))"
-      # < 220
-      CPU_MODEL = K60DN256ZVLL10
-      # It seems some of the MK60DZ10 devices have problems with JTAG speeds >= around 400 KHz
-      # when programming, we reduce the speed to 300 KHz with this command.
-      CPU_OOCD_FLAGS += -c 'adapter_khz 300'
-    else
-      # >= 220
-      CPU_MODEL = K60DN512VLL10
-    endif
-  endif
   CFLAGS += -DMULLE_SERIAL=$(MULLE_SERIAL)
 endif
 

boards/mulle/board.c

@@ -191,24 +191,10 @@ static inline void set_fll_source(void)
     /* Select FLL as source (as opposed to PLL) */
     SIM->SOPT2 &= ~(SIM_SOPT2_PLLFLLSEL_MASK);
     /* Use external 32kHz RTC clock as source for OSC32K */
-#if K60_CPU_REV == 1
-    SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL_MASK;
-#elif K60_CPU_REV == 2
     SIM->SOPT1 = (SIM->SOPT1 & ~(SIM_SOPT1_OSC32KSEL_MASK)) | SIM_SOPT1_OSC32KSEL(2);
-#else
-#error Unknown K60 CPU revision
-#endif
 
     /* Select RTC 32kHz clock as reference clock for the FLL */
-#if K60_CPU_REV == 1
-    /* Rev 1 parts */
-    SIM->SOPT2 |= SIM_SOPT2_MCGCLKSEL_MASK;
-#elif K60_CPU_REV == 2
-    /* Rev 2 parts */
     MCG->C7 = (MCG_C7_OSCSEL_MASK);
-#else
-#error Unknown K60 CPU revision
-#endif
 }
 
 static int mulle_nvram_init(void)

cpu/k60/cpu.c

@@ -6,7 +6,6 @@
  * details.
  */
 
-#include <stdint.h>
 #include "cpu.h"
 #include "board.h"
 #include "periph/init.h"
@@ -21,12 +20,6 @@
  * @author      Joakim Nohlgård <joakim.nohlgard@eistec.se>
  */
 
-/**
- * @brief Check the running CPU identification to find if we are running on the
- *        wrong hardware.
- */
-static void check_running_cpu_revision(void);
-
 /**
  * @brief Initialize the CPU, set IRQ priorities
  */
@@ -34,30 +27,8 @@ void cpu_init(void)
 {
     /* initialize the Cortex-M core */
     cortexm_init();
-    /* Check that we are running on the CPU that this code was built for */
-    check_running_cpu_revision();
     /* trigger static peripheral initialization */
     periph_init();
 }
 
-static void check_running_cpu_revision(void)
-{
-    /* Check that the running CPU revision matches the compiled revision */
-    if (SCB->CPUID != K60_EXPECTED_CPUID) {
-        uint32_t CPUID = SCB->CPUID; /* This is only to ease debugging, type
-                   * "print /x CPUID" in gdb */
-        uint32_t SILICON_REVISION = (SCB->CPUID & SCB_CPUID_REVISION_Msk) + 1;
-        (void)CPUID; /* prevents compiler warnings about an unused variable. */
-        (void)SILICON_REVISION;
-
-        /* Running on the wrong CPU, the clock initialization is different
-         * between silicon revision 1.x and 2.x (LSB of CPUID) */
-        /* If you unexpectedly end up on this line when debugging:
-         * Rebuild the code using the correct value for K60_CPU_REV */
-        __asm__ volatile ("bkpt #99\n");
-
-        while (1);
-    }
-}
-
 /** @} */

cpu/k60/include/MK60-comp.h

@@ -1,69 +0,0 @@
-/*
- * Copyright (C) 2015 Eistec AB
- *
- * This file is subject to the terms and conditions of the GNU Lesser General
- * Public License v2.1. See the file LICENSE in the top level directory for more
- * details.
- */
-
-/**
- * @ingroup         cpu_k60
- * @{
- *
- * @file
- * @brief           Compatibility definitions between MK60D10.h and MK60DZ10.h
- *
- * @author          Joakim Nohlgård <joakim.nohlgard@eistec.se>
- */
-
-#ifndef MK60_COMP_H
-#define MK60_COMP_H
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-#if K60_CPU_REV == 1
-
-/* Some compatibility defines to minimize the ifdefs needed for the register
- * name changes */
-
-#define SIM_SCGC6_SPI0_MASK SIM_SCGC6_DSPI0_MASK
-#define SIM_SCGC6_SPI0_SHIFT SIM_SCGC6_DSPI0_SHIFT
-
-#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
-#define MCG_C5_PRDIV0_MASK MCG_C5_PRDIV_MASK
-#define MCG_C6_VDIV0_MASK MCG_C6_VDIV_MASK
-
-#define UART_BASES { UART0, UART1, UART2, UART3, UART4, UART5 }
-
-#define LPTMR0_IRQn LPTimer_IRQn
-
-/* Rev 2.x made the OSC32KSEL field into a bitfield (is a single bit in 1.x) */
-#define SIM_SOPT1_OSC32KSEL(a) (SIM_SOPT1_OSC32KSEL_MASK)
-
-#endif /* K60_CPU_REV == 1 */
-
-
-/* Compatibility defines for compatibility with differing module names between
- * MK60 and MKW22 headers */
-#define SIM_SCGC5_LPTMR_MASK SIM_SCGC5_LPTIMER_MASK
-#define SIM_SCGC5_LPTMR_SHIFT SIM_SCGC5_LPTIMER_SHIFT
-
-#ifndef OSC0
-/* Compatibility definition */
-#define OSC0 OSC
-#endif
-#ifndef MCG_C2_RANGE0
-/* Rev 2 parts renamed the parameter RANGE -> RANGE0 */
-#define MCG_C2_RANGE0 MCG_C2_RANGE
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* MK60_COMP_H */
-/** @} */

cpu/k60/include/cpu_conf.h

@@ -31,9 +31,6 @@ extern "C"
 #include <stdint.h>
 
 #if defined(CPU_MODEL_K60DN512VLL10) || defined(CPU_MODEL_K60DN256VLL10)
-
-/* Rev. 2.x silicon */
-#define K60_CPU_REV 2
 #include "vendor/MK60D10.h"
 
 /** The expected CPUID value, can be used to implement a check that we are
@@ -42,27 +39,10 @@ extern "C"
 
 /* K60 rev 2.x replaced the RNG module in 1.x by the RNGA PRNG module */
 #define KINETIS_RNGA            (RNG)
-
-#elif defined(CPU_MODEL_K60DN512ZVLL10) || defined(CPU_MODEL_K60DN256ZVLL10)
-
-/* Rev. 1.x silicon */
-#define K60_CPU_REV 1
-#include "vendor/MK60DZ10.h"
-
-/** The expected CPUID value, can be used to implement a check that we are
- * running on the right hardware */
-#define K60_EXPECTED_CPUID 0x410fc240u
-
-/* K60 rev 1.x has the cryptographically strong RNGB module */
-#define KINETIS_RNGB            (RNG)
-
 #else
 #error Unknown CPU model. Update Makefile.include in the board directory.
 #endif
 
-/* Compatibility definitions between the two different Freescale headers */
-#include "MK60-comp.h"
-
 /**
  * @brief   ARM Cortex-M specific CPU configuration
  * @{
@@ -146,20 +126,12 @@ extern "C"
  * @name Power mode hardware details
  */
 /** @{ */
-#if K60_CPU_REV == 1
+#define KINETIS_PMCTRL SMC->PMCTRL
-#define KINETIS_PMCTRL MC->PMCTRL
+#define KINETIS_PMCTRL_SET_MODE(x) (KINETIS_PMCTRL = SMC_PMCTRL_STOPM(x) | SMC_PMCTRL_LPWUI_MASK)
-#define KINETIS_PMCTRL_SET_MODE(x) (KINETIS_PMCTRL = MC_PMCTRL_LPLLSM(x) | MC_PMCTRL_LPWUI_MASK)
 /* Clear LLS protection, clear VLPS, VLPW, VLPR protection */
 /* Note: This register can only be written once after each reset, so we must
  * enable all power modes that we wish to use. */
-#define KINETIS_UNLOCK_PMPROT() (MC->PMPROT |= MC_PMPROT_ALLS_MASK | MC_PMPROT_AVLP_MASK)
-#elif K60_CPU_REV == 2
-#define KINETIS_PMCTRL SMC->PMCTRL
-#define KINETIS_PMCTRL_SET_MODE(x) (KINETIS_PMCTRL = SMC_PMCTRL_STOPM(x) | SMC_PMCTRL_LPWUI_MASK)
 #define KINETIS_PMPROT_UNLOCK() (SMC->PMPROT |= SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK)
-#else
-#error Unknown K60 CPU revision!
-#endif
 
 /**
  * @name STOP mode bitfield values

cpu/k60/include/vendor/MK60D10.h

@@ -14576,6 +14576,12 @@ typedef struct {
 #define LPTimer_IRQn                             LPTMR0_IRQn
 #define LPTimer_IRQHandler                       LPTMR0_IRQHandler
 
+/* Compatibility defines for compatibility with differing module names between
+ * MK60 and MKW22 headers */
+#define SIM_SCGC5_LPTMR_MASK SIM_SCGC5_LPTIMER_MASK
+#define SIM_SCGC5_LPTMR_SHIFT SIM_SCGC5_LPTIMER_SHIFT
+#define OSC0 OSC
+
 /*!
  * @}
  */ /* end of group Backward_Compatibility_Symbols */

cpu/k60/ldscripts/K60DN256ZVLL10.ld

@@ -1 +0,0 @@
-K60DN256VLL10.ld

cpu/k60/ldscripts/K60DN512ZVLL10.ld

@@ -1 +0,0 @@
-K60DN512VLL10.ld