Merge pull request #14967 from aabadie/pr/boards/stm32f0_clock_kconfig_only

boards/stm32f0: add Kconfig for clock configuration

boards/nucleo-f030r8/Kconfig

@@ -21,4 +21,8 @@ config BOARD_NUCLEO_F030R8
     select HAS_PERIPH_TIMER
     select HAS_PERIPH_UART
 
+    # Clock configuration
+    select BOARD_HAS_HSE
+    select BOARD_HAS_LSE
+
 source "$(RIOTBOARD)/common/nucleo64/Kconfig"

boards/nucleo-f031k6/include/periph_conf.h

@@ -20,14 +20,6 @@
 #ifndef PERIPH_CONF_H
 #define PERIPH_CONF_H
 
-/* Adjust PLL factors:
-  - On nucleo-f031k6, there's no HSE and PREDIV is hard-wired to 2
-  - to reach 48MHz set PLL_MUL to 12 so core clock = (HSI8 / 2) * 12 = 48MHz */
-#define CONFIG_CLOCK_PLL_PREDIV     (2)
-#ifndef CONFIG_CLOCK_PLL_MUL
-#define CONFIG_CLOCK_PLL_MUL        (12)
-#endif
-
 #include "periph_cpu.h"
 #include "f0/cfg_clock_default.h"
 #include "cfg_timer_tim2.h"

boards/nucleo-f042k6/include/periph_conf.h

@@ -19,14 +19,6 @@
 #ifndef PERIPH_CONF_H
 #define PERIPH_CONF_H
 
-/* Adjust PLL factors:
-  - On nucleo-f042k6, there's no HSE and PREDIV is hard-wired to 2
-  - to reach 48MHz set PLL_MUL to 12 so core clock = (HSI8 / 2) * 12 = 48MHz */
-#define CONFIG_CLOCK_PLL_PREDIV     (2)
-#ifndef CONFIG_CLOCK_PLL_MUL
-#define CONFIG_CLOCK_PLL_MUL        (12)
-#endif
-
 #include "periph_cpu.h"
 #include "f0/cfg_clock_default.h"
 #include "cfg_timer_tim2.h"

boards/nucleo-f070rb/Kconfig

@@ -22,4 +22,8 @@ config BOARD_NUCLEO_F070RB
     select HAS_PERIPH_TIMER
     select HAS_PERIPH_UART
 
+    # Clock configuration
+    select BOARD_HAS_HSE
+    select BOARD_HAS_LSE
+
 source "$(RIOTBOARD)/common/nucleo64/Kconfig"

boards/nucleo-f072rb/Kconfig

@@ -23,4 +23,8 @@ config BOARD_NUCLEO_F072RB
     select HAS_PERIPH_UART
     select HAS_PERIPH_SPI
 
+    # Clock configuration
+    select BOARD_HAS_HSE
+    select BOARD_HAS_LSE
+
 source "$(RIOTBOARD)/common/nucleo64/Kconfig"

boards/nucleo-f091rc/Kconfig

@@ -22,4 +22,8 @@ config BOARD_NUCLEO_F091RC
     select HAS_PERIPH_UART
     select HAS_PERIPH_SPI
 
+    # Clock configuration
+    select BOARD_HAS_HSE
+    select BOARD_HAS_LSE
+
 source "$(RIOTBOARD)/common/nucleo64/Kconfig"

boards/stm32f030f4-demo/Kconfig

@@ -20,3 +20,8 @@ config BOARD_STM32F030F4_DEMO
     select HAS_PERIPH_UART
     select HAS_PERIPH_SPI
     select HAS_PERIPH_RTC
+
+    # Clock configuration
+    select BOARD_HAS_HSE
+
+source "$(RIOTBOARD)/common/stm32/Kconfig"

boards/stm32f0discovery/Kconfig

@@ -19,3 +19,8 @@ config BOARD_STM32F0DISCOVERY
     select HAS_PERIPH_SPI
     select HAS_PERIPH_TIMER
     select HAS_PERIPH_UART
+
+    # Clock configuration
+    select BOARD_HAS_HSE
+
+source "$(RIOTBOARD)/common/stm32/Kconfig"

cpu/stm32/include/clk/f0/cfg_clock_default.h

@@ -78,13 +78,23 @@ extern "C" {
 
 #define CLOCK_HSI                       MHZ(8)
 
-/* The following parameters configure a 48MHz system clock with HSI (or default HSE) as input clock */
+/* The following parameters configure a 48MHz system clock with HSI (or default HSE) as input clock
+On stm32f031x6 and stm32f042x6 lines, there's no HSE and PREDIV is hard-wired to 2,
+so to reach 48MHz set PLL_PREDIV to 2 and PLL_MUL to 12 so core clock = (HSI8 / 2) * 12 = 48MHz */
 #ifndef CONFIG_CLOCK_PLL_PREDIV
+#if defined(CPU_LINE_STM32F031x6) || defined(CPU_LINE_STM32F042x6)
+#define CONFIG_CLOCK_PLL_PREDIV         (2)
+#else
 #define CONFIG_CLOCK_PLL_PREDIV         (1)
 #endif
+#endif
 #ifndef CONFIG_CLOCK_PLL_MUL
+#if defined(CPU_LINE_STM32F031x6) || defined(CPU_LINE_STM32F042x6)
+#define CONFIG_CLOCK_PLL_MUL            (12)
+#else
 #define CONFIG_CLOCK_PLL_MUL            (6)
 #endif
+#endif
 
 #if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
 #define CLOCK_CORECLOCK                 (CLOCK_HSI)

cpu/stm32/kconfigs/Kconfig.clk

@@ -6,7 +6,7 @@
 #
 
 menu "STM32 clock configuration"
-    depends on CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
+    depends on CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_F0 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
 
 choice
 bool "Clock source selection"
@@ -47,11 +47,11 @@ endchoice
 
 endif  # CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
 
-if CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
 config CUSTOM_PLL_PARAMS
     bool "Configure PLL parameters"
     depends on USE_CLOCK_PLL
 
+if CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
 config CLOCK_PLL_M
     int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS
     default 1 if CPU_FAM_G0
@@ -112,14 +112,28 @@ endif  # CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5
 
 endif  # CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
 
+if CPU_FAM_F0
+config CLOCK_PLL_PREDIV
+    int "PLLIN division factor" if CUSTOM_PLL_PARAMS && !CPU_LINE_STM32F031X6 && !CPU_LINE_STM32F042X6
+    default 2 if CPU_LINE_STM32F031X6 || CPU_LINE_STM32F042X6
+    default 1
+    range 1 16
+
+config CLOCK_PLL_MUL
+    int "PLLIN multiply factor" if CUSTOM_PLL_PARAMS
+    default 12 if CPU_LINE_STM32F031X6 || CPU_LINE_STM32F042X6
+    default 6
+    range 2 16
+endif
+
 if CPU_FAM_L0 || CPU_FAM_L1
 config CLOCK_PLL_DIV
-    int "Main PLL division factor" if USE_CLOCK_PLL
+    int "Main PLL division factor" if CUSTOM_PLL_PARAMS
     default 2
     range 2 4
 
 choice
-bool "Main PLL multiply factor" if USE_CLOCK_PLL
+bool "Main PLL multiply factor" if CUSTOM_PLL_PARAMS
 default PLL_MUL_4
 
 config PLL_MUL_3