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cpu/arm7_common: Make irq_*() compiler barriers

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Previously the compiler was allowed to reorder access to the interrupt control
registers in regard to memory access not marked as `volatile` (at least some
people - most notably some compiler developers - read the C standard this way).
In practise this did not happen as irq_disable(), irq_restore(), irq_enable()
are part of a separate compilation unit: Calls to external functions unknown to
the compiler are treated as if they were memory barriers. But if link time
optimization (LTO) is enabled, this no longer would work: The compiler could
inline the code accessing the interrupt control registers and reorder the memory
accesses wrapped in irq_disable() and irq_restore() outside of their protection.

This commit adds the "memory" clobber to the inline assembly accessing the
interrupt control registers. This makes those accesses explicit compiler memory
barriers. The machine code generated without LTO enabled should not differ in
any way by this commit. But the use of irq_*() should now be safe with LTO.
This commit is contained in:
Marian Buschsieweke 2019-04-24 16:29:30 +02:00
parent 59b4dcffed
commit 5f355e7210
No known key found for this signature in database
GPG Key ID: 61F64C6599B1539F
1 changed files with 3 additions and 3 deletions
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6
cpu/arm7_common/VIC.c
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@ -14,20 +14,20 @@
static inline unsigned __get_cpsr(void)
{
unsigned long retval;
__asm__ volatile(" mrs %0, cpsr" : "=r"(retval) : /* no inputs */);
__asm__ volatile(" mrs %0, cpsr" : "=r"(retval) : /* no inputs */ : "memory");
return retval;
}
int irq_is_in(void)
{
int retval;
__asm__ volatile(" mrs %0, cpsr" : "=r"(retval) : /* no inputs */);
__asm__ volatile(" mrs %0, cpsr" : "=r"(retval) : /* no inputs */ : "memory");
return (retval & INTMode) == 18;
}
static inline void __set_cpsr(unsigned val)
{
__asm__ volatile(" msr cpsr, %0" : /* no outputs */ : "r"(val));
__asm__ volatile(" msr cpsr, %0" : /* no outputs */ : "r"(val) : "memory");
}
unsigned irq_disable(void)