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cpu/saml1x: set wait state according to datasheet

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dylad 2019-03-23 21:33:41 +01:00
parent 10b783d82c
commit 82aa6c0280
1 changed files with 14 additions and 5 deletions
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19
cpu/saml1x/cpu.c
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@ -22,6 +22,12 @@
#include "periph/init.h" #include "periph/init.h"
#include "board.h" #include "board.h"
#ifdef CPU_FAM_SAML11
#define _NVMCTRL NVMCTRL_SEC
#else
#define _NVMCTRL NVMCTRL
#endif
static void _gclk_setup(int gclk, uint32_t reg) static void _gclk_setup(int gclk, uint32_t reg)
{ {
GCLK->GENCTRL[gclk].reg = reg; GCLK->GENCTRL[gclk].reg = reg;
@ -40,6 +46,7 @@ void cpu_init(void)
MCLK->APBAMASK.reg = MCLK_APBAMASK_MCLK MCLK->APBAMASK.reg = MCLK_APBAMASK_MCLK
| MCLK_APBAMASK_OSCCTRL | MCLK_APBAMASK_OSCCTRL
| MCLK_APBAMASK_GCLK | MCLK_APBAMASK_GCLK
| MCLK_APBAMASK_PM
#ifdef MODULE_PERIPH_GPIO_IRQ #ifdef MODULE_PERIPH_GPIO_IRQ
| MCLK_APBAMASK_EIC | MCLK_APBAMASK_EIC
#endif #endif
@ -53,6 +60,13 @@ void cpu_init(void)
while (GCLK->CTRLA.reg & GCLK_CTRLA_SWRST) {} while (GCLK->CTRLA.reg & GCLK_CTRLA_SWRST) {}
while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) {} while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) {}
PM->PLCFG.reg = PM_PLCFG_PLSEL_PL2;
while (0 == PM->INTFLAG.bit.PLRDY) {}
MCLK->APBBMASK.reg |= MCLK_APBBMASK_NVMCTRL;
_NVMCTRL->CTRLB.reg |= NVMCTRL_CTRLB_RWS(1);
MCLK->APBBMASK.reg &= ~MCLK_APBBMASK_NVMCTRL;
/* set OSC16M to 16MHz */ /* set OSC16M to 16MHz */
OSCCTRL->OSC16MCTRL.bit.FSEL = 3; OSCCTRL->OSC16MCTRL.bit.FSEL = 3;
OSCCTRL->OSC16MCTRL.bit.ONDEMAND = 0; OSCCTRL->OSC16MCTRL.bit.ONDEMAND = 0;
@ -61,11 +75,6 @@ void cpu_init(void)
/* Setup GCLK generators */ /* Setup GCLK generators */
_gclk_setup(0, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSC16M); _gclk_setup(0, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSC16M);
#ifdef MODULE_PERIPH_PM
/* enable power managemet module */
MCLK->APBAMASK.reg |= MCLK_APBAMASK_PM;
#endif
/* trigger static peripheral initialization */ /* trigger static peripheral initialization */
periph_init(); periph_init();
} }