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cpu/stm32: add transition phase when raising +80MHz clock

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Alexandre Abadie 2020-08-24 14:06:15 +02:00
parent 500bb83d16
commit 84bbee784d
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1 changed files with 14 additions and 0 deletions
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14
cpu/stm32/stmclk/stmclk_gx.c
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@ -155,9 +155,23 @@ void stmclk_init_sysclk(void)
RCC->CR |= RCC_CR_PLLON; RCC->CR |= RCC_CR_PLLON;
while (!(RCC->CR & RCC_CR_PLLRDY)) {} while (!(RCC->CR & RCC_CR_PLLRDY)) {}
#if CLOCK_AHB > MHZ(80)
/* Divide HCLK by before enabling the PLL */
RCC->CFGR |= RCC_CFGR_HPRE_DIV2;
#endif
/* now that the PLL is running, we use it as system clock */ /* now that the PLL is running, we use it as system clock */
RCC->CFGR |= RCC_CFGR_SW_PLL; RCC->CFGR |= RCC_CFGR_SW_PLL;
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {} while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {}
#if CLOCK_AHB > MHZ(80)
/* Wait 1us before switching back to full speed */
/* Use volatile to prevent the compiler from optimizing the loop */
volatile uint8_t count = CLOCK_CORECLOCK / MHZ(1);
while (count--) {}
RCC->CFGR &= ~RCC_CFGR_HPRE_DIV2;
#endif
#endif #endif
stmclk_disable_hsi(); stmclk_disable_hsi();