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Merge pull request #6812 from haukepetersen/fix_cortexm_usecommonsleep

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cpu/sam0|stm32: use common cortexm_sleep()
This commit is contained in:
Kaspar Schleiser 2017-05-11 14:44:05 +02:00 committed by GitHub
commit 8f239e4c61
3 changed files with 10 additions and 22 deletions
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12
cpu/samd21/periph/pm.c
View File

@ -52,38 +52,34 @@ enum system_sleepmode {
void pm_set(unsigned mode)
{
int deep = 0;
switch (mode) {
case 0:
/* Standby Mode
* Potential Wake Up sources: asynchronous
*/
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
deep = 1;
break;
case 1:
/* Sleep mode Idle 2
* Potential Wake Up sources: asynchronous
*/
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
PM->SLEEP.reg = SYSTEM_SLEEPMODE_IDLE_2;
break;
case 2:
/* Sleep mode Idle 1
* Potential Wake Up sources: Synchronous (APB), asynchronous
*/
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
PM->SLEEP.reg = SYSTEM_SLEEPMODE_IDLE_1;
break;
case 3:
/* Sleep mode Idle 0
* Potential Wake Up sources: Synchronous (APB, AHB), asynchronous
*/
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
PM->SLEEP.reg = SYSTEM_SLEEPMODE_IDLE_0;
break;
}
/* Executes a device DSB (Data Synchronization Barrier) */
__DSB();
/* Enter standby mode */
__WFI();
cortexm_sleep(deep);
}

5
cpu/saml21/periph/pm.c
View File

@ -49,8 +49,5 @@ void pm_set(unsigned mode)
while (PM->SLEEPCFG.bit.SLEEPMODE != _mode) {}
}
/* Executes a device DSB (Data Synchronization Barrier) */
__DSB();
/* Enter standby mode */
__WFI();
cortexm_sleep(0);
}

15
cpu/stm32_common/periph/pm.c
View File

@ -30,6 +30,8 @@
void pm_set(unsigned mode)
{
int deep = 0;
/* I just copied it from stm32f1/2/4, but I suppose it would work for the
* others... /KS */
#if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4)
@ -40,26 +42,19 @@ void pm_set(unsigned mode)
/* Enable WKUP pin to use for wakeup from standby mode */
PWR->CSR |= PWR_CSR_EWUP;
/* Set SLEEPDEEP bit of system control block */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
deep = 1;
break;
case 1: /* STM Stop mode */
/* Clear PDDS and LPDS bits to enter stop mode on */
/* deepsleep with voltage regulator on */
PWR->CR &= ~(PWR_CR_PDDS | PWR_CR_LPDS);
/* Set SLEEPDEEP bit of system control block */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
break;
case 2: /* STM Sleep mode */
/* Reset SLEEPDEEP bit of system control block */
SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk);
deep = 1;
break;
}
#endif
/* Executes a device DSB (Data Synchronization Barrier) */
__DSB();
/* Enter standby mode */
__WFI();
cortexm_sleep(deep);
}
#if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4)