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boards/stm32l1: use shared clock configuration header

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This commit is contained in:
Alexandre Abadie 2020-08-27 16:01:10 +02:00
parent 9d1ebb54d4
commit 8f39a4a310
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GPG Key ID: 1C919A403CAE1405
7 changed files with 24 additions and 142 deletions
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3
boards/im880b/Makefile.include
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@ -1,3 +1,6 @@
# this board uses shared STM32 configuration snippets
INCLUDES += -I$(RIOTBOARD)/common/stm32/include
# define the default port depending on the host OS # define the default port depending on the host OS
PORT_LINUX ?= /dev/ttyUSB0 PORT_LINUX ?= /dev/ttyUSB0
PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*))) PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*)))

37
boards/im880b/include/periph_conf.h
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@ -19,42 +19,19 @@
#ifndef PERIPH_CONF_H #ifndef PERIPH_CONF_H
#define PERIPH_CONF_H #define PERIPH_CONF_H
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock system configuration
* @{
**/
#define CLOCK_HSE (16000000U) /* external oscillator */
#define CLOCK_CORECLOCK (32000000U) /* desired core clock frequency */
/* /*
* 0: no external low speed crystal available, * This board provides an LSE, so enable it before including the default clock config
* 1: external crystal available (always 32.768kHz)
*/ */
#ifndef CLOCK_LSE #ifndef CLOCK_LSE
#define CLOCK_LSE (1) #define CLOCK_LSE (1)
#endif #endif
/* configuration of PLL prescaler and multiply values */
/* CORECLOCK := HSE / CLOCK_PLL_DIV * CLOCK_PLL_MUL */
#define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2
#define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4
/* configuration of peripheral bus clock prescalers */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */
/* configuration of flash access cycles */
#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */ #include "periph_cpu.h"
#define CLOCK_AHB (CLOCK_CORECLOCK / 1) #include "l1/cfg_clock_default.h"
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) #ifdef __cplusplus
/** @} */ extern "C" {
#endif
/** /**
* @name Timer configuration * @name Timer configuration

3
boards/limifrog-v1/Makefile.include
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@ -1,3 +1,6 @@
# this board uses shared STM32 configuration snippets
INCLUDES += -I$(RIOTBOARD)/common/stm32/include
# define the default port depending on the host OS # define the default port depending on the host OS
PORT_LINUX ?= /dev/ttyUSB0 PORT_LINUX ?= /dev/ttyUSB0
PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*))) PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*)))

25
boards/limifrog-v1/include/periph_conf.h
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@ -20,35 +20,12 @@
#define PERIPH_CONF_H #define PERIPH_CONF_H
#include "periph_cpu.h" #include "periph_cpu.h"
#include "l1/cfg_clock_default.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/**
* @name Clock system configuration
* @{
**/
#define CLOCK_HSI (16000000U) /* internal oscillator */
#define CLOCK_CORECLOCK (32000000U) /* desired core clock frequency */
/* configuration of PLL prescaler and multiply values */
/* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */
#define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2
#define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4
/* configuration of peripheral bus clock prescalers */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */
/* configuration of flash access cycles */
#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
/** @} */
/** /**
* @name Timer configuration * @name Timer configuration
* @{ * @{

38
boards/lobaro-lorabox/include/periph_conf.h
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@ -24,43 +24,21 @@
#ifndef PERIPH_CONF_H #ifndef PERIPH_CONF_H
#define PERIPH_CONF_H #define PERIPH_CONF_H
/*
* This board provides an LSE, so enable it before including the default clock config
*/
#ifndef CLOCK_LSE
#define CLOCK_LSE (1)
#endif
#include "periph_cpu.h" #include "periph_cpu.h"
#include "l1/cfg_clock_default.h"
#include "cfg_timer_tim2.h" #include "cfg_timer_tim2.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/**
* @name Clock system configuration
* @{
**/
#define CLOCK_HSI (16000000U) /* frequency of internal oscillator */
#define CLOCK_CORECLOCK (32000000U) /* targeted core clock frequency */
/*
* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz)
*/
#ifndef CLOCK_LSE
#define CLOCK_LSE (1)
#endif
/* configuration of PLL prescaler and multiply values */
/* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */
#define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2
#define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4
/* configuration of peripheral bus clock prescalers */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */
/* configuration of flash access cycles */
#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
/** @} */
/** /**
* @name UART configuration * @name UART configuration
* @{ * @{

35
boards/nucleo-l152re/include/periph_conf.h
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@ -21,46 +21,13 @@
#define PERIPH_CONF_H #define PERIPH_CONF_H
#include "periph_cpu.h" #include "periph_cpu.h"
#include "l1/cfg_clock_default.h"
#include "cfg_timer_tim5.h" #include "cfg_timer_tim5.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/**
* @name Clock system configuration
* @{
**/
#define CLOCK_HSI (16000000U) /* frequency of internal oscillator */
#define CLOCK_CORECLOCK (32000000U) /* targeted core clock frequency */
/*
* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz)
*
* LSE might not be available by default in early (C-01) Nucleo boards.
* For newer revisions, an LSE crystal is present and CLOCK_LSE can be set to 1
* if one wants to use it.
*/
#ifndef CLOCK_LSE
#define CLOCK_LSE (0)
#endif
/* configuration of PLL prescaler and multiply values */
/* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */
#define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2
#define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4
/* configuration of peripheral bus clock prescalers */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */
/* configuration of flash access cycles */
#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
/** @} */
/** /**
* @name DMA streams configuration * @name DMA streams configuration
* @{ * @{

25
boards/nz32-sc151/include/periph_conf.h
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@ -20,36 +20,13 @@
#define PERIPH_CONF_H #define PERIPH_CONF_H
#include "periph_cpu.h" #include "periph_cpu.h"
#include "l1/cfg_clock_default.h"
#include "cfg_timer_tim5.h" #include "cfg_timer_tim5.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/**
* @name Clock system configuration
* @{
**/
#define CLOCK_HSI (16000000U) /* internal oscillator */
#define CLOCK_CORECLOCK (32000000U) /* desired core clock frequency */
/* configuration of PLL prescaler and multiply values */
/* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */
#define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2
#define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4
/* configuration of peripheral bus clock prescalers */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */
/* configuration of flash access cycles */
#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/** @} */
/** /**
* @name UART configuration * @name UART configuration
* @{ * @{