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cpu/stm32: use CONFIG_BOARD_HAS_LSE instead of CLOCK_LSE

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This commit is contained in:
Alexandre Abadie 2020-10-20 22:02:13 +02:00
parent fed1c4dbbe
commit 9f985e8e56
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GPG Key ID: 1C919A403CAE1405
3 changed files with 9 additions and 9 deletions
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6
cpu/stm32/periph/rtc_all.c
View File

@ -147,7 +147,7 @@
#endif #endif
/* figure out sync and async prescaler */ /* figure out sync and async prescaler */
#if CLOCK_LSE #if IS_ACTIVE(CONFIG_BOARD_HAS_LSE)
#define PRE_SYNC (255) #define PRE_SYNC (255)
#define PRE_ASYNC (127) #define PRE_ASYNC (127)
#elif (CLOCK_LSI == 40000) #elif (CLOCK_LSI == 40000)
@ -168,7 +168,7 @@
/* Use a magic number to determine the initial RTC source. This will be used /* Use a magic number to determine the initial RTC source. This will be used
to know if a reset of the RTC is required at initialization. */ to know if a reset of the RTC is required at initialization. */
#if CLOCK_LSE #if IS_ACTIVE(CONFIG_BOARD_HAS_LSE)
#define MAGIC_CLCK_NUMBER (0x1970) #define MAGIC_CLCK_NUMBER (0x1970)
#else #else
#define MAGIC_CLCK_NUMBER (0x1971) #define MAGIC_CLCK_NUMBER (0x1971)
@ -241,7 +241,7 @@ void rtc_init(void)
/* select input clock and enable the RTC */ /* select input clock and enable the RTC */
stmclk_dbp_unlock(); stmclk_dbp_unlock();
EN_REG &= ~(CLKSEL_MASK); EN_REG &= ~(CLKSEL_MASK);
#if CLOCK_LSE #if IS_ACTIVE(CONFIG_BOARD_HAS_LSE)
EN_REG |= (CLKSEL_LSE | EN_BIT); EN_REG |= (CLKSEL_LSE | EN_BIT);
#else #else
EN_REG |= (CLKSEL_LSI | EN_BIT); EN_REG |= (CLKSEL_LSI | EN_BIT);

4
cpu/stm32/periph/rtt_all.c
View File

@ -52,7 +52,7 @@
#if defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7) #if defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7)
#define CLOCK_SRC_REG RCC->DCKCFGR2 #define CLOCK_SRC_REG RCC->DCKCFGR2
#define CLOCK_SRC_MASK RCC_DCKCFGR2_LPTIM1SEL #define CLOCK_SRC_MASK RCC_DCKCFGR2_LPTIM1SEL
#if CLOCK_LSE #if IS_ACTIVE(CONFIG_BOARD_HAS_LSE)
#define CLOCK_SRC_CFG (RCC_DCKCFGR2_LPTIM1SEL_1 | RCC_DCKCFGR2_LPTIM1SEL_0) #define CLOCK_SRC_CFG (RCC_DCKCFGR2_LPTIM1SEL_1 | RCC_DCKCFGR2_LPTIM1SEL_0)
#else #else
#define CLOCK_SRC_CFG (RCC_DCKCFGR2_LPTIM1SEL_0) #define CLOCK_SRC_CFG (RCC_DCKCFGR2_LPTIM1SEL_0)
@ -60,7 +60,7 @@
#else #else
#define CLOCK_SRC_REG RCC->CCIPR #define CLOCK_SRC_REG RCC->CCIPR
#define CLOCK_SRC_MASK RCC_CCIPR_LPTIM1SEL #define CLOCK_SRC_MASK RCC_CCIPR_LPTIM1SEL
#if CLOCK_LSE #if IS_ACTIVE(CONFIG_BOARD_HAS_LSE)
#define CLOCK_SRC_CFG (RCC_CCIPR_LPTIM1SEL_1 | RCC_CCIPR_LPTIM1SEL_0) #define CLOCK_SRC_CFG (RCC_CCIPR_LPTIM1SEL_1 | RCC_CCIPR_LPTIM1SEL_0)
#else #else
#define CLOCK_SRC_CFG (RCC_CCIPR_LPTIM1SEL_0) #define CLOCK_SRC_CFG (RCC_CCIPR_LPTIM1SEL_0)

8
cpu/stm32/stmclk/stmclk_common.c
View File

@ -49,8 +49,8 @@
#define RCC_CSR_LSIRDY RCC_CSR_LSI1RDY #define RCC_CSR_LSIRDY RCC_CSR_LSI1RDY
#endif #endif
#ifndef CLOCK_LSE #ifndef CONFIG_BOARD_HAS_LSE
#define CLOCK_LSE (0U) #define CONFIG_BOARD_HAS_LSE 0
#endif #endif
void stmclk_enable_hsi(void) void stmclk_enable_hsi(void)
@ -66,7 +66,7 @@ void stmclk_disable_hsi(void)
void stmclk_enable_lfclk(void) void stmclk_enable_lfclk(void)
{ {
if (CLOCK_LSE) { if (IS_ACTIVE(CONFIG_BOARD_HAS_LSE)) {
stmclk_dbp_unlock(); stmclk_dbp_unlock();
RCC->REG_LSE |= BIT_LSEON; RCC->REG_LSE |= BIT_LSEON;
while (!(RCC->REG_LSE & BIT_LSERDY)) {} while (!(RCC->REG_LSE & BIT_LSERDY)) {}
@ -80,7 +80,7 @@ void stmclk_enable_lfclk(void)
void stmclk_disable_lfclk(void) void stmclk_disable_lfclk(void)
{ {
if (CLOCK_LSE) { if (IS_ACTIVE(CONFIG_BOARD_HAS_LSE)) {
stmclk_dbp_unlock(); stmclk_dbp_unlock();
RCC->REG_LSE &= ~(BIT_LSEON); RCC->REG_LSE &= ~(BIT_LSEON);
while (!(RCC->REG_LSE & BIT_LSERDY)) {} while (!(RCC->REG_LSE & BIT_LSERDY)) {}