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boards/stm32g0/g4: cleanup Kconfig clock configuration

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Alexandre Abadie 2020-09-05 11:49:56 +02:00
parent 2d603269dd
commit a50eab59c4
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GPG Key ID: 1C919A403CAE1405
2 changed files with 10 additions and 15 deletions
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15
boards/common/stm32/Kconfig.g0
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@ -24,28 +24,25 @@ config USE_CLOCK_HSI
endchoice endchoice
if USE_CLOCK_PLL
config CLOCK_PLL_M config CLOCK_PLL_M
int "M: PLLIN division factor" int "M: PLLIN division factor" if USE_CLOCK_PLL
default 1 default 1
range 1 8 range 1 8
config CLOCK_PLL_N config CLOCK_PLL_N
int "N: PLLIN multiply factor" int "N: PLLIN multiply factor" if USE_CLOCK_PLL
default 20 default 20
range 8 86 range 8 86
config CLOCK_PLL_R config CLOCK_PLL_R
int "Q: VCO division factor" int "Q: VCO division factor" if USE_CLOCK_PLL
default 6 if BOARD_HAS_HSE default 6 if BOARD_HAS_HSE
default 5 if !BOARD_HAS_HSE default 5
range 2 8 range 2 8
endif
choice choice
bool "HSISYS division factor" bool "HSISYS division factor" if USE_CLOCK_HSI
default CLOCK_HSISYS_DIV_1 default CLOCK_HSISYS_DIV_1
depends on USE_CLOCK_HSI
config CLOCK_HSISYS_DIV_1 config CLOCK_HSISYS_DIV_1
bool "Divide HSISYS by 1" bool "Divide HSISYS by 1"
@ -75,7 +72,7 @@ endchoice
config CLOCK_HSISYS_DIV config CLOCK_HSISYS_DIV
int int
default 1 if CLOCK_HSISYS_DIV_1 default 1
default 2 if CLOCK_HSISYS_DIV_2 default 2 if CLOCK_HSISYS_DIV_2
default 4 if CLOCK_HSISYS_DIV_4 default 4 if CLOCK_HSISYS_DIV_4
default 8 if CLOCK_HSISYS_DIV_8 default 8 if CLOCK_HSISYS_DIV_8

10
boards/common/stm32/Kconfig.g4
View File

@ -24,20 +24,19 @@ config USE_CLOCK_HSI
endchoice endchoice
if USE_CLOCK_PLL
config CLOCK_PLL_M config CLOCK_PLL_M
int "M: Division factor for the main PLL input clock" int "M: Division factor for the main PLL input clock" if USE_CLOCK_PLL
default 6 if BOARD_HAS_HSE default 6 if BOARD_HAS_HSE
default 4 if !BOARD_HAS_HSE default 4
range 1 16 range 1 16
config CLOCK_PLL_N config CLOCK_PLL_N
int "N: Multiply factor for the VCO" int "N: Multiply factor for the VCO" if USE_CLOCK_PLL
default 40 default 40
range 8 127 range 8 127
choice choice
bool "R: Main PLL division factor for PLL 'R' clock (system clock)" bool "R: Main PLL division factor for PLL 'R' clock (system clock)" if USE_CLOCK_PLL
default PLL_R_DIV_2 default PLL_R_DIV_2
config PLL_R_DIV_2 config PLL_R_DIV_2
@ -60,7 +59,6 @@ config CLOCK_PLL_R
default 4 if PLL_R_DIV_4 default 4 if PLL_R_DIV_4
default 6 if PLL_R_DIV_6 default 6 if PLL_R_DIV_6
default 8 if PLL_R_DIV_8 default 8 if PLL_R_DIV_8
endif
choice choice
bool "APB1 prescaler (division factor of HCLK to produce PCLK1)" bool "APB1 prescaler (division factor of HCLK to produce PCLK1)"