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Merge pull request #14892 from aabadie/pr/boards/stm32f1f3_default_clock

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boards/stm32f1: stm32f3: use shared default clock configuration header
This commit is contained in:
Francisco 2020-09-02 09:48:43 +02:00 committed by GitHub
commit a75d32692c
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GPG Key ID: 4AEE18F83AFDEB23
22 changed files with 151 additions and 407 deletions
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1
boards/common/blxxxpill/Makefile.include
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@ -1,3 +1,4 @@
INCLUDES += -I$(RIOTBOARD)/common/stm32/include
INCLUDES += -I$(RIOTBOARD)/common/blxxxpill/include
ifeq (dfu-util,$(PROGRAMMER))

33
boards/common/blxxxpill/include/periph_conf.h
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@ -24,41 +24,16 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* blxxxpill boards provide an LSE */
#define CLOCK_LSE (1)
#include "periph_cpu.h"
#include "f1f3/cfg_clock_default.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 72MHz */
#define CLOCK_CORECLOCK (72000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1U)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (9)
/** @} */
/**
* @name Real time counter configuration
* @{

1
boards/common/iotlab/Makefile.include
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@ -17,4 +17,5 @@ OPENOCD_CONFIG ?= $(RIOTBOARD)/common/iotlab/dist/openocd.cfg
include $(RIOTMAKE)/tools/openocd.inc.mk
# add the common header files to the include path
INCLUDES += -I$(RIOTBOARD)/common/stm32/include
INCLUDES += -I$(RIOTBOARD)/common/iotlab/include

40
boards/common/iotlab/include/periph_conf_common.h
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@ -20,42 +20,22 @@
#ifndef PERIPH_CONF_COMMON_H
#define PERIPH_CONF_COMMON_H
/* iotlab boards provide an LSE */
#define CLOCK_LSE (1)
/* HSE is clocked at 16MHz */
#define CLOCK_HSE MHZ(16)
/* Adjust PLL predevider to reach 72MHz sysclock */
#define CLOCK_PLL_PREDIV (2)
#include "periph_cpu.h"
#include "f1f3/cfg_clock_default.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 72MHz */
#define CLOCK_CORECLOCK (72000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (16000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (2)
#define CLOCK_PLL_MUL (9)
/** @} */
/**
* @name ADC configuration
* @{

74
boards/common/stm32/include/f1f3/cfg_clock_default.h Normal file
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@ -0,0 +1,74 @@
/*
* Copyright (C) 2015 TriaGnoSys GmbH
* 2017 Alexander Kurth, Sören Tempel, Tristan Bruns
* 2020 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief Default clock configuration for STM32F1/F3
*
* @author Víctor Ariño <victor.arino@triagnosys.com>
* @author Sören Tempel <tempel@uni-bremen.de>
* @author Tristan Bruns <tbruns@uni-bremen.de>
* @author Alexander Kurth <kurth1@uni-bremen.de>
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*
*/
#ifndef F1F3_CFG_CLOCK_DEFAULT_H
#define F1F3_CFG_CLOCK_DEFAULT_H
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 72MHz */
#define CLOCK_CORECLOCK MHZ(72)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#ifndef CLOCK_HSE
#define CLOCK_HSE MHZ(8)
#endif
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#ifndef CLOCK_LSE
#define CLOCK_LSE (0)
#endif
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* PLL factors */
#ifndef CLOCK_PLL_PREDIV
#define CLOCK_PLL_PREDIV (1)
#endif
#ifndef CLOCK_PLL_MUL
#define CLOCK_PLL_MUL (9)
#endif
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* F1F3_CFG_CLOCK_DEFAULT_H */
/** @} */

3
boards/fox/Makefile.include
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@ -1,3 +1,6 @@
# Include shared STM32 headers
INCLUDES += -I$(RIOTBOARD)/common/stm32/include
# set default port depending on operating system
PORT_LINUX ?= /dev/ttyUSB1
PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbserial*)))

39
boards/fox/include/periph_conf.h
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@ -19,41 +19,22 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* iotlab boards provide an LSE */
#define CLOCK_LSE (1)
/* HSE is clocked at 16MHz */
#define CLOCK_HSE MHZ(16)
/* Adjust PLL predevider to reach 72MHz sysclock */
#define CLOCK_PLL_PREDIV (2)
#include "periph_cpu.h"
#include "f1f3/cfg_clock_default.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 72MHz */
#define CLOCK_CORECLOCK (72000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (16000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1U)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (2)
#define CLOCK_PLL_MUL (9)
/** @} */
/**
* @name Timer configuration
* @{

3
boards/maple-mini/Makefile.include
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@ -1,3 +1,6 @@
# Include shared STM32 headers
INCLUDES += -I$(RIOTBOARD)/common/stm32/include
# define the default port depending on the host OS
PORT_LINUX ?= /dev/ttyACM0
PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*)))

30
boards/maple-mini/include/periph_conf.h
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@ -20,40 +20,12 @@
#define PERIPH_CONF_H
#include "periph_cpu.h"
#include "f1f3/cfg_clock_default.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 72MHz */
#define CLOCK_CORECLOCK (72000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (0U)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (9)
/** @} */
/**
* @name Timer configuration
* @{

33
boards/nucleo-f103rb/include/periph_conf.h
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@ -19,41 +19,16 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#define CLOCK_LSE (1)
#include "periph_cpu.h"
#include "f1f3/cfg_clock_default.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 72MHz */
#define CLOCK_CORECLOCK (72000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (9)
/** @} */
/**
* @name Timer configuration
* @{

33
boards/nucleo-f302r8/include/periph_conf.h
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@ -23,42 +23,17 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#define CLOCK_LSE (1)
#include "periph_cpu.h"
#include "f1f3/cfg_clock_default.h"
#include "cfg_timer_tim2.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 72MHz */
#define CLOCK_CORECLOCK (72000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (9)
/** @} */
/**
* @name UART configuration
* @{

37
boards/nucleo-f303k8/include/periph_conf.h
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@ -19,42 +19,21 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* No HSE available for this board */
#define CLOCK_HSE (0U)
/* Adjust PLL prescalers to reach 72MHz sysclock */
#define CLOCK_PLL_PREDIV (2)
#define CLOCK_PLL_MUL (16)
#include "periph_cpu.h"
#include "f1f3/cfg_clock_default.h"
#include "cfg_timer_tim2.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 72MHz */
#define CLOCK_CORECLOCK (64000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (0U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (0)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (2)
#define CLOCK_PLL_MUL (16)
/** @} */
/**
* @name DMA streams configuration
* @{

33
boards/nucleo-f303re/include/periph_conf.h
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@ -21,42 +21,17 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#define CLOCK_LSE (1)
#include "periph_cpu.h"
#include "f1f3/cfg_clock_default.h"
#include "cfg_timer_tim2.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 72MHz */
#define CLOCK_CORECLOCK (72000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (9)
/** @} */
/**
* @name UART configuration
* @{

33
boards/nucleo-f303ze/include/periph_conf.h
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@ -19,42 +19,17 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#define CLOCK_LSE (1)
#include "periph_cpu.h"
#include "f1f3/cfg_clock_default.h"
#include "cfg_timer_tim2.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 72MHz */
#define CLOCK_CORECLOCK (72000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (9)
/** @} */
/**
* @name UART configuration
* @{

33
boards/nucleo-f334r8/include/periph_conf.h
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@ -20,42 +20,17 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#define CLOCK_LSE (1)
#include "periph_cpu.h"
#include "f1f3/cfg_clock_default.h"
#include "cfg_timer_tim2.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 72MHz */
#define CLOCK_CORECLOCK (72000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (9)
/** @} */
/**
* @name DMA streams configuration
* @{

33
boards/olimexino-stm32/include/periph_conf.h
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@ -19,41 +19,16 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#define CLOCK_LSE (1)
#include "periph_cpu.h"
#include "f1f3/cfg_clock_default.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 72MHz */
#define CLOCK_CORECLOCK (72000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (9)
/** @} */
/**
* @name ADC configuration
* @{

3
boards/opencm904/Makefile.include
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@ -1,3 +1,6 @@
# Include shared STM32 headers
INCLUDES += -I$(RIOTBOARD)/common/stm32/include
# define the default port depending on the host OS
PORT_LINUX ?= /dev/ttyACM0
PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*)))

30
boards/opencm904/include/periph_conf.h
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@ -20,40 +20,12 @@
#define PERIPH_CONF_H
#include "periph_cpu.h"
#include "f1f3/cfg_clock_default.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 72MHz */
#define CLOCK_CORECLOCK (72000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (0U)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (9)
/** @} */
/**
* @name Timer configuration
* @{

3
boards/spark-core/Makefile.include
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@ -1,3 +1,6 @@
# Include shared STM32 headers
INCLUDES += -I$(RIOTBOARD)/common/stm32/include
# configure the serial interface
PORT_LINUX ?= /dev/ttyUSB0
PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*)))

30
boards/spark-core/include/periph_conf.h
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@ -20,40 +20,12 @@
#define PERIPH_CONF_H
#include "periph_cpu.h"
#include "f1f3/cfg_clock_default.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 72MHz */
#define CLOCK_CORECLOCK (72000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (0U)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (9)
/** @} */
/**
* @name Timer configuration
* @{

3
boards/stm32f3discovery/Makefile.include
View File

@ -1,3 +1,6 @@
# add the common header files to the include path
INCLUDES += -I$(RIOTBOARD)/common/stm32/include
# define the default port depending on the host OS
PORT_LINUX ?= /dev/ttyUSB0
PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*)))

30
boards/stm32f3discovery/include/periph_conf.h
View File

@ -20,40 +20,12 @@
#define PERIPH_CONF_H
#include "periph_cpu.h"
#include "f1f3/cfg_clock_default.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 72MHz */
#define CLOCK_CORECLOCK (72000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (0)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (9)
/** @} */
/**
* @name DAC configuration
* @{